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PIO 8255 (Cont..) : M Krishna Kumar MAM/M3/LU9e/V1/2004 1
PIO 8255 (Cont..) : M Krishna Kumar MAM/M3/LU9e/V1/2004 1
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The parallel input-output port chip 8255 is also called as programmable peripheral input-output port. The Intels 8255 is designed for use with Intels 8-bit, 16-bit and higher capability microprocessors. It has 24 input/output lines which may be individually programmed in two groups of twelve lines each, or three groups of eight lines. The two groups of I/O pins are named as Group A and Group B. Each of these two groups contains a subgroup of eight I/O lines called as 8-bit port and another subgroup of four lines or a 4-bit port. Thus Group A contains an 8-bit port A along with a 4-bit port. C upper.
M Krishna kumar
MAM/M3/LU9e/V1/2004
M Krishna kumar
MAM/M3/LU9e/V1/2004
M Krishna kumar
MAM/M3/LU9e/V1/2004
M Krishna kumar
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M Krishna kumar
MAM/M3/LU9e/V1/2004
M Krishna kumar
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RD 0 0 0 0 RD 1 1 1 1 RD X 1
WR 1 1 1 1 WR 0 0 0 0 WR X 1
CS 0 0 0 0 CS 0 0 0 0 CS 1 0
A1 0 0 1 1 A1 0 0 1 1 A1 X X
A0 0 1 0 1 A0 0 1 0 1 A0 X X
Input (Read) cycle Port A to Data bus Port B to Data bus Port C to Data bus CWR to Data bus Output (Write) cycle Data bus to Port A Data bus to Port B Data bus to Port C Data bus to CWR Function Data bus tristated Data bus tristated
PIO 8255.
D0-D7 : These are the data bus lines those carry data or control word to/from the microprocessor. RESET : A logic high on this line clears the control word register of 8255. All ports are set as input ports by default after reset.
M Krishna kumar
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a) b)
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d) e)
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D3 0 0 0 0 1 1 1 1
D2 0 0 1 1 0 0 1 1
D1 0 1 0 1 0 1 0 1
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PA PCU
PA PC
Mode 0
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2. 3. 4.
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1- Set
PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
PA4 PA5 PA6 PA7 WR Reset D0 D1 D2 D3 D4 D5 D6 D7 Vcc PB7 PB6 PB5 PB4 PB3
8255A
PA0-PA7
GND
Signals of 8255
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3 Group A control 1 D0-D7 Data bus Buffer 8 bit int data bus
PA0-PA7
PC7-PC4
PC0-PC3
Group B control
PB7-PB0
22
D7
D5
D4 PA
D3 PC U
D2 Mode for PB PB
D1
D0 PC L
Mode Set flag 1- active 0- BSR mode Group - A 1 Input PC u 0 Output 1 Input PA 0 Output 00 mode 0 Mode 01 mode 1 Select 10 mode 2 of PA Group - B PCL PB Mode Select 1 Input 0 Output 1 Input 0 Output 0 mode- 0 1 mode- 1
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X 1
D7 D6 D5 D4 D3 D2 D1 D0
INTRA I/O
PC0
INTR
A
MAM/M3/LU9e/V1/2004
STB
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WR OBF
INTR
ACK
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D7 D6 D5 D4 D3 D2 D1 D0 1 - Input 0 - Output For PC4 PC5 PA0 PA7 INTEA PC7 PC6 OBF A ACKA
D7 D6 D5 D4 D3 D2 D1 D0
INTRA I/O
PC0
INTRB
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IBF Data bus RD Mode 2 Bidirectional Data Transfer Data from 8085 Data towards 8255
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D7 1
D6 1
D5 X
D4 X
D3 X
D2 1/0
D1 1/0
D0 1/0
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PC3 PA0-PA7
INTR
INTE 1
PC7 PC6
INTE 2 RD WR
PC4 PC5
Mode 2 pins
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