Ramya.

R R&M

Multipliers
This is a digital signal processing hardware that is capable of multiplying two digits.
Most of the digital signal processing computations such as convolution and correlation require array multiplication. For a logic design we can classify multipliers into two main types depending on the application Serial Multipliers Parallel Multipliers

Classification of Multipliers

Multipliers
From logic point of view we can divide it into two main categories Clocked multipliers Array multipliers In both types, the product is effectively obtained through successive additions ,the difference being that sufficient parallelism exists in the array multiplier so that the final answer is obtained without intermediate results. Considering multiplications we generally choose the 2-s complement as it is most suitable for high speed performance

Add Shift Multiplier

Add Shift Multiplier

This is a (5 X 4) add shift multiplier. This device successively accumulates the rows, if corresponding bit of y column is 1 if the bit is 0 , a row of 0s is gated into the adders

x4 x3 x2 x1 x0 y0 x4 x3 x2 x1 x0 y1 x4 x3 x2 x 1 x0 y2 x4 x3 x2 x1 x 0 y3

Each time a row is gated in, the accumulated sum is shifted to the right so that successive rows contribute more significant bits.

Add Shift Multiplier

Clock 1 shifts the y bits into the and gates so that x bits or 0s are applied to the adders.

After the adder levels have established , clock 2 strobes he adder outputs into accumulator flip flops, which after settling down are shifted to one place in the right. The worst case settling time for an n bit adder is
(n-1)c+ m s +

c carry propagation time s Sum propagation time for one bit adder r settling time for the y shift register

Add Shift Multiplier

If n bits are multiplied by m bits then the total multiplication time

r c carry propagation time s Sum propagation time for one bit adder r settling time for the y shift register
A useful arithmetic representation of 2s complement number

m (n-1)c+ m s +

Add Shift Multiplier

An arithmetic expression for the product XY of a pair of 2s complement numbers where X is an (n+1) bit number and Y is an (m+1) bit number

An arithmetic expression for the product XY of a pair of 2s complement numbers where X is an (n+1) bit number and Y is an (m+1) bit number

The first and fourth terms on the right are positive numbers while the second and third expressions are negative. The fourth term is the complete result and corresponds to successive additions that are implemented .

Add Shift Multiplier

A convenient logical extension of this is given by the BOOTHs Algorithm which can be explained by writing the number Y as

Array Multiplier
The fastest multiplier consist of a 2 D array of one bit adder and are referred to as array multiplier Unlike the clocked multiplier ,the array multiplier is a complete memory less logic net that only requires a prescribed settling time after the application of the input signals before the product can be used. Each little circle is a one bit adder and each row is a full ripple carry adder and each row gives its partial sum to the row below . The settling time is 2nc+ m s c carry propagation time s Sum propagation time for one bit adder

Array Multiplier
x5y2 x5y3 x4y3 x4y2 x3y3 x3y2 x2y2 x1y3 x1y2 x0y3
0

x 0y 2
0
p2

p1

x2y3

y7 y6 y5 y4 y3 y2 y1 y0 x5x4 x3 x2 x1 x0

x0 y0 (x 0 y 1 + x 1 y 0 )

p0 p1 p2

(x0 y2 + x1 y1 + x2 y0 )

Faster Array Structure For Multiplication

The settling time is [(m-1)+(n-1)]c if m c >(n-1)s (n-1)(c+ s) if m c <(n-1)s

c carry propagation time

s Sum propagation time for one bit adder

Tree Index for Array Multiplier

Tree Array Multiplier (6X8)