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Code No: B0609, B5701 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.Tech II - Semester Regular Examinations September, 2010 ALGORITHMS FOR VLSI DESIGN AUTOMATION (COMMON TO DS AND CE, VLSI SYSTEM DESIGN) Time: 3hours Max. Marks: 60 Answer any five questions All questions carry equal marks --1. (a) Explain the process of generic IC design methodology. (b) Explain the term Computational complexity related to VLSI design automation. 2. (a) Write an algorithm for branch and bound method. (b) Give an algorithm for an exhaustive search by means of back tracking. 3. (a) Give pseudo code description of simulated annealing. (b) Explain about the Liao-Wong algorithm.

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4. (a) What is meant by modeling and simulation ? Explain with an example. (b) Distinguish between gate level simulation and switch level simulation. 5. (a) Explain about two level logic synthesis with suitable example. (b) Explain about binary-decision diagrams with an example.

6. (a) Discuss about high level transformations related to high level synthesis. (b) Explain allocation and assignment related to high level synthesis. 7. (a) Explain about various FPGA technologies. (b) What is the role of partitioning and routing for segmented and staggered models? Explain. 8. Write short notes on the following (i) Chip array based approaches. (ii) Multiple stage routing. (iii) Intractable problems. ---o0o---

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