-- MODULE 2: Code to generate various Test Datas

Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.math_real.all; use ieee.numeric_std.all; entity BIST_TestAlg is port(clk,clr: in std_logic; test_data_in : in std_logic_vector(7 downto 0); op: out std_logic); end entity;

architecture behave of BIST_TestAlg is signal dcod_cnt_prgen,clk_8,sft_clk,lat_clk_8,t_1,t_0,odd_par,even_par,parity_code:std_logic; signal psudo_code,psudo_code_1,bst_inp_one: std_logic_vector(7 downto 0); signal cnt_prgen: std_logic_vector(3 downto 0);

begin -- PseudoRandom Codes input Test pr1:process(clk,clr,dcod_cnt_prgen) begin if clr='1' or dcod_cnt_prgen='1' then cnt_prgen <= "0000"; elsif rising_edge(clk) then cnt_prgen <= cnt_prgen+1; end if; end process pr1; dcod_cnt_prgen <= cnt_prgen(3) and (not (cnt_prgen(2))) and (not (cnt_prgen(1))) and (not (cnt_prgen(0))); pr2:process(dcod_cnt_prgen,clr) begin if clr='1' then clk_8 <= '0'; elsif rising_edge(dcod_cnt_prgen) then clk_8 <= not clk_8; end if; end process pr2; sft_clk <= clk_8 and clk;

latch_clk8:process(clk,clr) begin if clr='1' then lat_clk_8<='0'; elsif falling_edge(clk) then

lat_clk_8<=clk_8; end if; end process latch_clk8;

shfter:process(sft_clk,dcod_cnt_prgen) begin if dcod_cnt_prgen='1' then t_1<='0'; t_0<='0'; psudo_code<=test_data_in; elsif rising_edge(sft_clk) then t_1<=psudo_code(0); t_0<=(psudo_code(2) xor psudo_code(4) xor psudo_code(6))xor t_1; psudo_code(7)<=t_0; psudo_code(6)<=psudo_code(7); psudo_code(5)<=psudo_code(6); psudo_code(4)<=psudo_code(5); psudo_code(3)<=psudo_code(4); psudo_code(2)<=psudo_code(3); psudo_code(1)<=psudo_code(2); psudo_code(0)<=psudo_code(1); end if; end process shfter; bst_inp_one<=psudo_code; -- Parity Check Test parity_code<=(((((((test_data_in(0) xor test_data_in(1))xor test_data_in(2))xor test_data_in(3))xor test_data_in(4))xor test_data_in(5))xor test_data_in(6))xor test_data_in(7)); parchk: process(test_data_in,clk) begin if parity_code='1' then even_par<='1'; odd_par<='0'; else even_par<='0'; odd_par<='1'; end if; end process parchk; end behave;