VLSI IMPLEMENTATION OF DISTRIBUTED ARCHITECTURE BASED DCT

Abstract Discrete cosine transform (DCT) is widely used in image and video compression standards. This paper presents distributed arithmetic (DA) based VLSI architecture of DCT for low hardware circuit cost as well as low power consumption. Low hardware cost is achieved by applying Distributed algorithm to 1D DCT using XILINX ISE software. In this project we are going to develop a DCT algorithm using partitioning the data blocks instead of row and column decomposition already presented in the reference paper. The result comparison of presented architecture and row column composition method is displayed in simulation. The comparison result also shows the considerable power as well as hardware savings in presented architecture.

Existing System In the Existing system, the proposed 1-D DCT architecture is implemented in both the Xilinx FPGA and Synopsys DC using TSMC CLN65GPLUS 65nm technology library. For power and hardware cost comparisons, recent DA based DCT architecture is also implemented. The comparison results indicate the. 2-D DCT is implemented using row column decomposition by the proposed 1-D DCT architecture.

Proposed System In the Proposed project we are going to develop a DCT algorithm using partitioning the data blocks instead of row and column decomposition already presented in the reference paper. The result comparison of presented architecture and row column composition method is displayed in simulation. The comparison result also shows the considerable power as well as hardware savings in presented architecture. XILINX ISE is used here for the implementation and synopsis ie, Modelsim is used for synthesis and simulation for different operating frequencies (speed).

Overview of Design process

As per the concept given in the reference paper , we are planning to design a DCT algorithm using Distributed architecture.Comparison of common architecture and DA based design is being obtained. 1.Design requirements of ID DCT is being generated and designed using common architecture in VHDL Code

2.design of 1x8 Dct is designed and the corresponding outputs are simulated in the Modelsim6.5a simulator 3.Distributed architecture based same 1D dct concept is need to be designed for the next phase and the comparison chart is designed using the simulation results of the both the Concept 4.The advantages in between common architecture and Distributed architecture is being tabulated 5. Power consumption for both the methods is being calculated

Modules : 1. Common architecture content includes y y y y A Clock Divider A 4bit Counter Decoder with clocked latch 16 lines Complex Accumulator

2.Trignometric value generator Logic Diagr

System Global clock

Clock Divider Reset 4 bit Counter

Clocked Latch

Complex Accumulator

Cos value generator

Decoder

DCT Output

Reference Signals

DATA FLOW OUTPUT

Clock divider & Cos gen

Complex Accumulator

Counter with Latch

Counter With Decoder

Simulation Result