JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY KAKINADA Challenge Revaluationg Results for B.

Tech Reg/Supply Examinations Nov-2012

Challenge Revaluation For B.tech I YEAR (R07,R05,RR) Supplementary Examinations Nov 2012

Sl No Htno 1 08A91A0332

Subject code Z0125

Internals 6

Externals 36

Credits Subject Name 6 MATHEMATICS - I

Challenge Revaluation For II B.Tech (R10,R07,R05,RR) I Semester Regular/Supply Examinations Nov 2012

Sl No 1 2 3 4 5 6 7

Htno 07991A0568 08PC1A0426 11331A1258 11501A0219 11501A0239 118T1A0214 118T1A0217

Subject code X0524 X0425 R21051 R21029 R21029 R21029 R21029

Internals 15 10 22 24 21 21 22

Externals 31 30 30 57 49 42 51

Credits 4 4 4 4 4 4 4

Subject Name DIGITAL LOGIC DESIGN ELECTRONICS CIRCUIT ANALYSIS DATA STRUCTURES ELECTRO MAGNETIC FIELD ELECTRO MAGNETIC FIELD ELECTRO MAGNETIC FIELD ELECTRO MAGNETIC FIELD

Challenge Revaluation For II B.Tech (R07,R05,RR) II Semester Supplementary Examinations Nov 2012

Sl No 1 2 3 4 5 6 7

Htno 03221A0456 04131A0803 04851A0213 04B15A1202 04B15A1202 06231A0576 08A11A0434

Subject code C9910 C0801 T0202 C9912 C9916 V0503 V0422

Internals 5 5 16 11 3 8 13

Externals 50 35 28 30 38 40 28

Credits 4 4 4 4 4 4 4

Subject Name EM WAVES & TRANSMISSION LINES MECHANICAL ENGINEERING ELECTRICAL MACHINES-II DATABASE MANAGEMENT SYSTEMS OPERATING SYSTEMS MICROPROCESSORS & INTERFACING OBJECT ORIENTED PROGRAMMING

Challenge Revaluation For III B.Tech (R10,R07,R05,RR) I Semester Regular/Supply Examinations Nov 2012

Sl No Htno 1 08501A1221 2 10R81A0511

Subject code V3128 R31053

Internals 9 25

Externals 35 35

Credits Subject Name 4 MICRO PROCESSORS AND INTERFACING 4 ADVANCED DATA STRUCTURES

Challenge Revaluation For III B.Tech (R07,R05,RR) II Semester Supplementary Examinations Nov 2012

Sl No 1 2 3 4 5 6 7 8

Htno 03F91A0429 04B15A1202 05131A0359 05A05A0203 06231A1224 07A61A0560 07K11A0469 08A31A0464

Subject code E9901 E9908 Q0302 E9901 Q0501 V3224 V3219 V3219

Internals 5 13 6 12 9 12 18 5

Externals 45 28 34 33 31 28 28 35

Credits 4 4 4 4 4 4 4 4

Subject Name MICROPROCESSORS AND INTERFACING COMPUTER NETWORKS DYNAMICS OF MACHINERY MICROPROCESSORS AND INTERFACING UNIX PROGRAMMING COMPUTER NETWORKS VLSI DESIGN VLSI DESIGN

Date: 28-03-2013

Controller of Examinations