DESIGN OF 9-BIT UART USING

VERILOG HDL

Submitted by:-
Himanshu Motwani (01315607312)
Mukesh Kumar Singh (01415607312)
Shubham Garg (01715607312)

Under The Guidance Of:-

Ms. Preeti Singh
 OVERVIEW

 Introduction to the universal asynchronous receiver

transmitter : UART
 Block diagram
 Receiver module
 Transmitter module
 Asynchronous FIFO module
 Results
 Merits
 Applications
 INTRODUCTION

 UART stands for UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER.
 Perform Parallel to serial conversion on data from
host processor to serial device and serial to parallel
conversion from serial device to the host processor.
 Data frame format for UART consists of a start bit
“0”, 5-8 bits data, optional parity bit and stop bit “1”.
BLOCK DIAGRAM
 RECEIVER MODULE

 During reception mode , UART will be in

listening mode and always sense for a start
bit.
 UART will determine whether to receive or
ignore the incoming data bytes.
 If a false start bit or stop bit is detected the
reception will be terminated and an
Interrupt will be send to processor.
 We use FSM to implement these steps.
 The receiver FSM has 5 states :-
RX_IDLE , RX_START , RX_DATA ,
RX_PARITY , RX_STOP.
RECEIVER MODULE FINITE STATE MACHINE
 TRANSMITTER MODULE

 When TXMODE is enabled in configuration

register of UART, it act as transmitter.
 Transmitter module converts the address and
data received from processor into serial bits .
 The address can be a broadcast address or a
unique address that belongs to a specific
device.
 The bits are transferred continuously until the
TX buffer is empty.
 An internal FSM is used to transmit the
complete 9 bit character , bit-by-bit.
 The FSM has 5 states in the transmitter :-
TX_IDLE , TX_START , TX_DATA , TX_PARITY ,
TX_STOP.
TRANSMITTER MODULE FINITE STATE MACHINE
 ASYNCHRONOUS FIFO MODULE

 A huge stream of data can come in too fast

and UART may not be quick.
 Add bunch of zeros while receiving line is
busy.
 Use RTS (Request to Send) and CTS (Clear
to Send) flow control mechanism.
 Most UART nowadays has internal buffer
with the size big enough to hold the data.
RESULTS
RTL SCHEMATIC OF RECEIVER
INTERNAL STRUCTURE OF RECEIVER
RTL SCHEMATIC FOR TRANSMITTER
INTERNAL STRUCTURE OF TRANSMITTER
TRANSMITTER SIMULATION
RTL SCHEMATIC OF ASYNCHRONOUS FIFO
INTERNAL STRUCTURE OF ASYNCHRONOUS FIFO
SIMULATION OF ASYNCHRONOUS FIFO
 MERITS

 High reliability.
 Low cost.
 Simple design.
 Easy to implement.
 APPLICATIONS

 It is mostly use for serial data communication in

computer.
 Typical serial ports used with personal computers
connected to modems use eight data bits, no parity,
and one stop bit.
 Some very low-cost embedded systems dispense with
a UART.
 Bluetooth use UART as host controller
interface(HCI).