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CHNG 1 KIN TRC C BN CA MY TNH 1. Nhng thnh phn c bn ca my tnh Biu din thng tin trong my tnh I.
. H m nh phn v phng php biu din thng tin trong my tnh. 1. H nh phn (Binary) 1.1. Khi nim: H nh phn hay h m c s 2 ch c hai con s 0 v 1. l h m da theo v tr. Gi tr ca mt s bt k no tu thuc vo v tr ca n. Cc v tr c trng s bng bc lu tha ca c s 2. Chm c s c gi l chm nh phn trong h m c s 2. Mi mt con s nh phn c gi l mt bit (Binary digit). Bit ngoi cng bn tri l bit c trng s ln nht (MSB, Most Significant Bit) v bit ngoi cng bn phi l bit c trng s nh nht (LSB, Least Significant Bit) nh di y: 23 22 21 20 2-1 2-2 MSB 1 0 1 0 . 1 1 LSB Chm nh phn S nh phn (1010.11)2 c th biu din thnh: (1010.11)2 = 1*23 + 0*22 + 1*21 + 0*20 + 1*2-1 + 1*2-2 = (10.75)10. Ch : dng du ngoc n v ch s di k hiu c s ca h m. i vi phn l ca cc s thp phn, s l c nhn vi c s v s nh c ghi li lm mt s nh phn. Trong qu trnh bin i, s nh u chnh l bit MSB v s nh cui l bit LSB. V d 2: Bin i s thp phn (0.625)10 thnh nh phn: 0.625*2 = 1.250. S nh l 1, l bit MSB. 0.250*2 = 0.500. S nh l 0 0.500*2 = 1.000. S nh l 1, l bit LSB. Vy : (0.625)10 = (0.101)2. 2. H thp lc phn (Hexadecima). 2.1. Khi nim: Cc h my tnh hin i thng dng mt h m khc l h thp lc phn. H thp lc phn l h m da vo v tr vi c s l 16. H ny dng cc con s t 0 n 9 v cc k t t A n F nh trong bng sau:
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Bng 1.1 H thp lc phn: Thp lc phn 0 1 2 3 4 5 6 7 8 9 A B C D E F Thp phn 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Nh phn 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
3. Bng m ASCII.(American Standard Code for Information Interchange). Ngi ta xy dng b m biu din cho cc k t cng nh cc con s V cc k hiu c bit khc. Cc m gi l b m k t v s. Bng m ASCII l m 7 bit c dng ph bin trong cc h my tnh hin nay. Vi m 7 bit nn c 27 = 128 t hp m. Mi k t (ch hoa v ch thng) cng nh cc con s thp phn t 0..9 v cc k hiu c bit khc u c biu din bng mt m s nh bng 2-2. Vic bin i thnh ASCII v cc m k t s khc, tt nht l s dng m tng ng trong bng. V d: i cc k t BILL thnh m ASCII: K t B I L L ASCII 1000010 1001001 1001100 1001100 HEXA 42 49 4C 4C
Bng 1.2: M ASCII. Bits(row) 111 R B4 O W 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 1 9 1 A 1 B 1 C 1 D 1 E 1 F 1 B3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 000 0 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI 1 DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US Column bits(B7B6B5) 001 010 011 100 101 2 SP ! # $ % & ( ) * + , . / 3 0 1 2 3 4 5 6 7 8 9 : ; < = > ? 4 @ A B C D E F G H I J K L M N O 5 P Q R S T U V W X Y Z [ \ ] ^ _ 6 \ A B C D E F G H I J K L M N O 110 7 p q r s t u v w x y z { | } ~ DEL
Control characters: NUL = Null; DLE = Data link escape; SOH = Start Of Heading; DC1 = Device control 1; DC2 = Device control 2; DC3 = Device control 3. DC4 = Device control 4; STX = Start of text; ETX = End of text; EOT = End of transmission; ENQ = Enquiry; NAK = Negative acknowlege. ACK = Acknowlege; SYN = Synidle; BEL = Bell. ETB = End od transmission block; BS = Backspace; CAN = Cancel. HT = Horizontal tab; EM = End of medium; LF = Line feed; SUB = Substitute. VT = Vertical tab; ESC = Escape; FF = From feed; FS = File separator. SO = Shift out; RS = Record separator; SI = Shift in; US = Unit separator. 4. Biu din gi tr s trong my tnh. 4.1. Biu din s nguyn. a. Biu din s nguyn khng du:
Tt c cc s cng nh cc m ... trong my vi tnh u c biu din bng cc ch s nh phn. biu din cc s nguyn khng du, ngi ta dng n bit. Tng ng vi di ca s bit c s dng, ta c cc khong gi tr xc nh nh sau: S bit Khong gi tr n bit: 0.. 2n - 1 8 bit 0.. 255 Byte 16 bit 0.. 65535 Word b. Biu din s nguyn c du: Ngi ta s dng bit cao nht biu din du; bit du c gi tr 0 tng ng vi s nguyn dng, bit du c gi tr 1 biu din s m. Nh vy khong gi tr s c biu din s c tnh nh sau: S bit Khong gi tr: n bit 2n-1-1 8 bit -128.. 127 Short integer 16 bit -32768.. 32767 Integer 32 bit -231.. 231-1 (-2147483648.. 2147483647) Long integer 4.2. Biu din s thc(s c du chm (phy) ng). C hai cch biu din s thc trong mt h nh phn: s c du chm c nh (fed point number) v s c du chm ng (floating point number). Cch th nht c dng trong nhng b VXL(micro processor) hay nhng b vi iu khin (micro controller) c. Cch th 2 hay c dng hin nay c chnh xc cao. i vi cch biu din s thc du chm ng c kh nng hiu chnh theo gi tr ca s thc. Cch biu din chung cho mi h m nh sau: R = m.Be. Trong m l phn nh tr, trong h thp phn gi tr tuyt i ca n phi lun nh hn 1. S e l phn m v B l c s ca h m. C hai chun nh dng du chm ng quan trng l: chun MSBIN ca Microsoft v chun IEEE. C hai chun ny u dng h m nh phn. Thng dng l theo tiu chun biu din s thc ca IEEE 7541985(Institute of Electric & Electronic Engineers), l chun c mi hng chp nhn v c dng trong b x l ton hc ca Intel. Bit du nm ti v tr cao nht; kch thc phn m v khun dng phn nh tr thay i theo tng loi s thc. Gi tr s thc IEEE c tnh nh sau: R = (-1)S*(1+M1*2-1 + ... +Mn*2-n)*2E 7...E 0 -127.
Ch : gi tr u tin M0 lun mc nh l 1. - Dng 32 bit biu din s thc, c s thc ngn: -3,4.1038 < R < 3,4.1038 31 S 30 23 22 E7 - E0 |nh tr (M1 - M23) 0
- Dng 64 bit biu din s thc, c s thc di: -1,7.10308 < R < 1,7.10308 63 S 62 52 51 E10 - E0 nh tr (M1 - M52) 0
V d tnh s thc: 0100 0010 1000 1100 1110 1001 1111 1100 Phn nh tr: 2-4+2-5+2-8+2-9+2-10+2-12+2-15+ +2-16+2-17+2-18+2-19+2-20+2-21 = 0,1008906. Gi tr ngm nh l: 1,1008906. Phn m: 28+22+20 =133 Gi tr thc (bit cao nht l bit du): 133-128=6. Du: 0 = s dng Gi tr s thc l: R = 1,1008906.26 = 70,457. Phng php i s thc sang s du phy ng 32 bit: - i s thp phn thnh s nh phn. - Biu din s nh phn di dng 1, xxxBy (B: c s 2). - Bit cao nht 31: ly gi tr 0 vi s dng, 1 vi s m. - Phn m y i sang m excess -127 ca y, c xc nh bng cch: y + (7F)16. - Phn xxx l phn nh tr, c a vo t bit 22..0. V d: Biu din s thc (9,75)10 di dng du phy ng. Ta i sang dng nh phn: (9,75)10 = (1001.11)2 = 1,00111B3. Bit du: bit 31 = 0. M excess - 127 ca 3 l: 7F + 3 = (82)16 = 82H = (10000010)2. c a vo cc bit tip theo: t bit 30 n bit 23. Bit 22 lun mc nh l 0.
Cui cng s thc (9,75)10 c biu din di dng du phy ng 32 bit nh sau: 0100 0001 0001 1100 0000 0000 0000 0000 bit |31|30 23|22 0|
2. Kin trc mt my tnh n gin 2.1. Gii thiu s lc cu trc ca my vi tnh. So vi t khi ra i, cu trc c s ca cc my vi tnh ngy nay khng thay i my. Mi my tnh s u c th coi nh c hnh thnh t su phn chnh (nh hnh 2-1): Hnh 2-1: Gii thiu s khi tng qut ca my tnh s
Data Bus Control Bus
B x l trung tm (CPU)
B nh trong (Memory) ROM-RAM
B nh ngoi (Mass store Unit)
Phi ghp vo/ra (I/O)
Thit b vo (Input Unit) Thit b ra (Output Unit)
Adrress Bus
Trong s ny, cc khi chc nng chnh ca my tnh s gm: - Khi x l trung tm (central processing unit, CPU), - B nh trong (memory), nh RAM, ROM - B nh ngoi, nh cc loi a, bng t - Khi phi ghp vi cc thit b ngoi vi (vo/ra) - Cc b phn u vo, nh bn phm, chut, my qut ... . - Cc b phn u ra, nh mn hnh, my in ... . 2.2 Lch s pht trin ca CPU 2.2.1.-BXL 4 bit 4004 l BXL u tin c Intel a ra thng 11 nm 1971, c tc 740KHz, kh nng x l 0,06 triu lnh mi giy (milion instructions per second - MIPS); c sn xut trn cng ngh 10 m, c 2.300 transistor (bng bn dn), b nh m rng n 640 byte. 2.2.2 BXL 8bit 8008 (nm 1972) c s dng trong thit b u cui Datapoint 2200 ca Computer Terminal Corporation (CTC). 8008 c tc 200kHz, sn xut trn cng ngh 10 m, vi 3.500 transistor, b nh m rng n
16KB. 8080 (nm 1974) s dng trong my tnh Altair 8800, c tc gp 10 ln 8008 (2MHz), sn xut trn cng ngh 6 m, kh nng x l 0,64 MIPS vi 6.000 transistor, c 8 bit bus d liu v 16 bit bus a ch, b nh m rng ti 64KB. 8085 c tc 2MHz, sn xut trn cng ngh 3 m, vi 6.500 transistor, c 8 bit bus d liu v 16 bit bus a ch, b nh m rng 64KB. 2.2.3.-BXL 16bit 80186 (nm 1982) cn gi l IAPX 186. S dng ch yu trong nhng ng dng nhng, b iu khin thit b u cui. Cc phin bn ca 80186 gm 10 v 12 MHz. 80286 (nm 1982) s dng cng ngh 1,5 m, 134.000 transistor, b nh m rng ti 16 MB. Cc phin bn ca 286 gm 6, 8, 10, 12,5, 16, 20 v 25MHz. 2.2.4. BXL 32bit vi kin trc NetBurst (NetBurst micro-architecture) Intel386 gm cc h 386DX, 386SX v 386SL. Intel386DX l BXL 32 bit u tin Intel gii thiu vo nm 1985, 386 s dng cc thanh ghi 32 bit, c th truyn 32 bit d liu cng lc trn bus d liu v dng 32 bit xc nh a ch. Cng nh BXL 80286, 80386 hot ng 2 ch : real mode v protect mode. 386SL (nm1990) c thit k cho thit b di ng, s dng cng ngh 1 m, 855.000 transistor, b nh m rng 4GB; gm cc phin bn 16, 20, 25 MHz. 486DX s dng cng ngh 1 m, 1,2 triu transistor, b nh m rng 4GB; gm cc phin bn 25 MHz, 35 MHz v 50 MHz (0,8 m). Pentium s dng cng ngh 0,8 m cha 3,1 triu transistor, c cc tc 60, 66 MHz (socket 4 273 chn, PGA). Cc phin bn 75, 90, 100, 120 MHz s dng cng ngh 0,6 m cha 3,3 triu transistor (socket 7, PGA). Phin bn 133, 150, 166, 200 s dng cng ngh 0,35 m cha 3,3 triu transistor (socket 7, PGA). Pentium MMX s dng cng ngh 0,35 m cha 4,5 triu transistor, c cc tc 166, 200, 233 MHz (Socket 7, PGA). 2.2.5. Pentium Pro: Ni tip s thnh cng ca dng Pentium, Pentium Pro c Intel gii thiu vo thng 9 nm 1995, s dng cng ngh 0,6 v 0,35 m cha 5,5 triu transistor, socket 8 387 chn, Dual SPGA, h tr b nh RAM ti a 4GB.
2.2.6. BXL Pentium II u tin, tn m Klamath, sn xut trn cng ngh 0,35 m, c 7,5 triu transistor, bus h thng 66 MHz, gm cc phin bn 233, 266, 300MHz. Pentium II, tn m Deschutes, s dng cng ngh 0,25 m, 7,5 triu transistor, gm cc phin bn 333MHz (bus h thng 66MHz), 350, 400, 450 MHz (bus h thng 100MHz). Celeron (nm 1998) c rt gn t kin trc BXL Pentium II, dnh cho dng my cp thp. 2.2.7. Pentium III (nm 1999) B sung 70 lnh mi (Streaming SIMD Extensions - SSE) gip tng hiu sut hot ng ca BXL trong cc tc v x l hnh nh, audio, video v nhn dng ging ni. Pentium III gm cc tn m Katmai, Coppermine v Tualatin. Coppermine s dng cng ngh 0,18 m, 28,1 triu transistor, b nh m L2 256 KB c tch hp bn trong nhm tng tc x l. Tualatin p dng cng ngh 0,13 m c 28,1 triu transistor, b nh m L1 32KB, L2 256 KB hoc 512 KB tch hp bn trong BXL, socket 370 FC-PGA (Flip-chip pin grid array), bus h thng 133 MHz. C cc tc nh 1133, 1200, 1266, 1333, 1400 MHz. Celeron Coppermine (nm 2000) c rt gn t kin trc BXL Pentium III Coppermine, cn gi l Celeron II, c b sung 70 lnh SSE. S dng cng ngh 0,18 m c 28,1 triu transistor, b nh m L1 32KB, L2 256 KB tch hp bn trong BXL, socket 370 FC-PGA, C cc tc nh 533, 566, 600, 633, 667, 700, 733, 766, 800 MHz (bus 66 MHz), 850, 900, 950, 1000, 1100, 1200, 1300 MHz (bus 100 MHz). Tualatin Celeron (Celeron S) (nm 2000) c rt gn t kin trc BXL Pentium III Tualatin, p dng cng ngh 0,13 m, b nh m L1 32KB, L2 256 KB tch hp, socket 370 FC-PGA, bus h thng 100 MHz, gm cc tc 1,0, 1,1, 1,2, 1,3 v 1,4 GHz. 2.2.8. Pentium 4 Intel Pentium 4 (P4) l BXL th h th 7 dng x86 ph thng, c gii thiu vo thng 11 nm 2000. P4 s dng vi kin trc NetBurst c thit k hon ton mi so vi cc BXL c (PII, PIII v Celeron s dng vi kin trc P6). Mt s cng ngh ni bt c p dng trong vi kin trc NetBurst nh Hyper Pipelined Technology m rng s hng lnh x l, Execution Trace Cache trnh tnh trng lnh b chm tr khi chuyn t b nh n CPU, Rapid Execution Engine tng tc b ng x l ton hc, bus h thng (system bus) 400 MHz v 533 MHz; cc cng ngh Advanced Transfer Cache, Advanced Dynamic Execution, Enhanced
Floating point v Multimedia Unit, Streaming SIMD Extensions 2 (SSE2) cng c ci tin nhm to ra nhng BXL tc cao hn, kh nng tnh ton mnh hn, x l a phng tin tt hn. Pentium 4 u tin (tn m Willamette) xut hin cui nm 2000 t du chm ht cho "triu i" Pentium III. Willamette sn xut trn cng ngh 0,18 m, c 42 triu transistor (nhiu hn gn 50% so vi Pentium III), bus h thng (system bus) 400 MHz, b nh m tch hp L2 256 KB, socket 423 v 478. P4 Willamette c mt s tc nh 1,3, 1,4, 1,5, 1,6, 1,7, 1,8, 1,9, 2,0 GHz. P4 Northwood. Xut hin vo thng 1 nm 2002, c sn xut trn cng ngh 0,13 m, c khong 55 triu transistor, b nh m tch hp L2 512 KB, socket 478. Northwood c 3 dng gm Northwood A (system bus 400 MHz), tc 1,6, 1,8, 2,0, 2,2, 2,4, 2,5, 2,6 v 2,8 GHz. Northwood B (system bus 533 MHz), tc 2,26, 2,4, 2,53, 2,66, 2,8 v 3,06 GHz (ring 3,06 GHz c h tr cng ngh siu phn lung Hyper Threading - HT). Northwood C (system bus 800 MHz, tt c h tr HT), gm 2,4, 2,6, 2,8, 3,0, 3,2, 3,4 GHz. P4 Prescott (nm 2004). L BXL u tin Intel sn xut theo cng ngh 90 nm, kch thc vi mch gim 50% so vi P4 Willamette. iu ny cho php tch hp nhiu transistor hn trn cng kch thc (125 triu transistor so vi 55 triu transistor ca P4 Northwood), tc chuyn i ca transistor nhanh hn, tng kh nng x l, tnh ton. Dung lng b nh m tch hp L2 ca P4 Prescott gp i so vi P4 Northwood (1MB so vi 512 KB). Ngoi tp lnh MMX, SSE, SSE2, Prescott c b sung tp lnh SSE3 gip cc ng dng x l video v game chy nhanh hn. y l giai on "giao thi" gia socket 478 - 775LGA, system bus 533 MHz - 800 MHz v mi sn phm c t tn ring khin ngi dng cng bi ri khi chn mua. Prescott A (FSB 533 MHz) c cc tc 2,26, 2,4, 2,66, 2,8 (socket 478), Prescott 505 (2,66 GHz), 505J (2,66 GHz), 506 (2,66 GHz), 511 (2,8 GHz), 515 (2,93 GHz), 515J (2,93 GHz), 516 (2,93 GHz), 519J (3,06 GHz), 519K (3,06 GHz) s dng socket 775LGA. Prescott E, F (nm 2004) c b nh m L2 1 MB (cc phin bn sau c m rng 2 MB), bus h thng 800 MHz. Ngoi tp lnh MMX, SSE, SSE2, SSE3 tch hp, Prescott E, F cn h tr cng ngh siu phn lung, mt s phin bn sau c h tr tnh ton 64 bit. Dng s dng socket 478 gm Pentium 4 HT 2.8E (2,8 GHz), 3.0E (3,0 GHz), 3.2E (3,2 GHz), 3.4E (3,4 GHz). Dng s dng socket 775LGA gm Pentium 4 HT 3.2F, 3.4F, 3.6F, 3.8F vi cc tc tng ng t 3,2 GHz n 3,8 GHz, Pentium 4 HT 517, 520, 520J, 521, 524, 530, 530J, 531, 540, 540J, 541, 550, 550J, 551, 560, 560J, 561, 570J, 571 vi cc tc t 2,8 GHz n 3,8 GHz.
2.2.9. BXL Celeron BXL Celeron c thit k vi mc tiu dung ha gia cng ngh v gi c, p ng cc yu cu ph thng nh truy cp Internet, Email, chat, x l cc ng dng vn phng. Celeron Willamette 128 (2002), bn "rt gn" t P4 Willamette, sn xut trn cng ngh 0,18 m, b nh m L2 128 KB, bus h thng 400 MHz, socket 478. Celeron Willamette 128 h tr tp lnh MMX, SSE, SSE2. Mt s BXL thuc dng ny nh Celeron 1.7 (1,7 GHz) v Celeron 1.8 (1,8 GHz). Celeron NorthWood 128, "rt gn" t P4 Northwood, cng ngh 0,13 m, b nh m tch hp L2 128 KB, bus h thng 400 MHz, socket 478. Celeron NorthWood 128 cng h tr cc tp lnh MMX, SSE, SSE2, gm Celeron 1.8A, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8 tng ng vi cc tc t 1,8 GHz n 2,8 GHz. Celeron D (Presscott 256), c xy dng t nn tng P4 Prescott, sn xut trn cng ngh 90nm, b nh m tch hp L2 256 KB (gp i dng Celeron NorthWood), bus h thng 533 MHz, socket 478 v 775LGA. Ngoi cc tp lnh MMX, SSE, SSE2, Celeron D h tr tp lnh SSE3, mt s phin bn sau c h tr tnh ton 64 bit. Celeron D gm 310, 315, 320, 325, 325J, 326, 330, 330J, 331, 335, 335J, 336, 340, 340J, 341, 345, 345J, 346, 350, 351, 355 vi cc tc tng ng t 2,13 GHz n 3,33 GHz. 2.2.10. Pentium 4 Extreme Edition Pentium 4 Extreme Edition (P4EE) xut hin vo thng 9 nm 2003, l BXL c Intel "u i" dnh cho game th v ngi dng cao cp. P4EE c xy dng t BXL Xeon dnh cho my ch v trm lm vic. Ngoi cng ngh HT "nh m" thi by gi, im ni bt ca P4EE l b sung b nh m L3 2 MB. Phin bn u tin ca P4 EE (nhn Gallatin) sn xut trn cng ngh 0,13 m, b nh m L2 512 KB, L3 2 MB, bus h thng 800 MHz, s dng socket 478 v 775LGA, gm P4 EE 3.2 (3,2 GHz), P4 EE 3.4 (3,4 GHz). 2.2.11.BXL 64 bit, vi kin trc NETBURST P4 Prescott (nm 2004) Vi kin trc NetBurst 64 bit (Extended Memory 64 Technology - EM64T) u tin c Intel s dng trong BXL P4 Prescott (tn m Prescott 2M). Prescott 2M cng s dng cng ngh 90 nm, b nh m L2 2 MB, bus h thng 800 MHz, socket 775LGA. Ngoi cc tp lnh MX, SSE, SSE2, SSE3, cng ngh HT v kh nng tnh ton 64 bit, Prescott 2M (tr BXL 620) c h tr cng ngh Enhanced SpeedStep ti u tc lm vic nhm tit kim in nng.
Cc BXL 6x2 c thm cng ngh o ha (Virtualization Technology). Prescott 2M c mt s tc nh P4 HT 620 (2,8 GHz), 630 (3,0 GHz), 640 (3,2 GHz), 650 (3,4 GHz), 660, 662 (3,6 GHz) v 670, 672 (3,8 GHz). 2.2.12. Pentium D (nm 2005) Pentium D (tn m Smithfield, 8xx) l BXL li kp (dual core) u tin ca Intel, c ci tin t P4 Prescott nn cng gp mt s hn ch nh hin tng tht c chai do bng thng BXL mc 800 MHz (400 MHz cho mi li), Cng s dng vi kin trc NetBurst, Pentium D (m Presler, 9xx) c Intel thit k mi trn cng ngh 65nm, 376 triu transistor, b nh m L2 4 MB (2x2 MB), hiu nng cao hn, nhiu tnh nng mi v t tn in nng hn Smithfield. Pentium D 915 v 920 tc 2,8 GHz, 925 v 930 (3,0GHz), 935 v 940 (3,2 GHz), 945 v 950 (3,4 GHz), 960 (3,6GHz). Presler dng 9x0 c h tr Virtualization Technology. 2.2.13. Pentium Extreme Edition (nm 2005) BXL li kp dnh cho game th v ngi dng cao cp. Pentium EE s dng nhn Smithfield, Presler ca Pentium D trong Smithfield s dng cng ngh 90nm, b nh m L2 c m rng n 2 MB (2x1 MB), h tr tp lnh MMX, SSE, SSE2, SSE3, cng ngh HT, Enhanced Intel SpeedStep Technology (EIST) v EM64T. Pentium 840 EE (3,20 GHz, bus h thng 800 MHz, socket 775LGA) l mt trong nhng BXL thuc dng ny. 2.2.14. BXL 64bit, kin trc Core Ti din n IDF u nm 2006, Intel gii thiu kin trc Intel Core vi nm ci tin quan trng l kh nng m rng thc thi ng (Wide Dynamic Execution), tnh nng qun l in nng thng minh (Intelligent Power Capability), chia s b nh m linh hot (Advanced Smart Cache), truy xut b nh thng minh (Smart Memory Access) v tng tc phng tin s tin tin (Advanced Digital Media Boost). 2.2.15. Intel Core 2 Duo BXL li kp sn xut trn cng ngh 65 nm, h tr SIMD instructions, cng ngh Virtualization Technology cho php chy cng lc nhiu HH, tng cng bo v h thng trc s tn cng ca virus (Execute Disable Bit), ti u tc BXL nhm tit kim in nng (Enhanced
Intel SpeedStep Technology), qun l my tnh t xa (Intel Active Management Technology). Ngoi ra, cn h tr cc tp lnh MMX, SSE, SSE2, SSE3, SSSE3. Core 2 Duo (tn m Conroe) c 291 triu transistor, b nh m L2 4 MB, bus h thng 1066 MHz, socket 775LGA. Mt s BXL thuc dng ny: E6600 (2,4 GHz), E6700 (2,66 GHz). Core 2 Duo (tn m Allendale) E6300 (1,86 GHz), E6400 (2,13 GHz) c 167 triu transistor, b nh m L2 2MB, bus h thng 1066 MHz, socket 775LGA. E4300 (1,8 GHz) xut hin nm 2007 c b nh m L2 2 MB, bus 800 MHz, khng h tr Virtualization Technology. 2.2.16. Core 2 Extreme BXL li kp dnh cho game th s dng kin trc Core, c nhiu c im ging vi BXL Core 2 nh cng ngh sn xut 65 nm, h tr cc cng ngh mi Enhanced Intel SpeedStep Technology, Intel x86-64, Execute Disable Bit, Intel Active Management, Virtualization Technology, Intel Trusted Execution Technology... cc tp lnh MMX, SSE, SSE2, SSE3, SSSE3. 2.2.17. Core 2 Extreme Core 2 Extreme (tn m Conroe XE) (thng 7 nm 2006) vi i din X6800 2,93 Ghz, b nh m L2 n 4 MB, bus h thng 1066 MHz, socket 775LGA. Cui nm 2006, con ng pha trc ca BXL tip tc rng m khi Intel gii thiu BXL 4 nhn (Quad Core) nh Core 2 Extreme QX6700, Core 2 Quad Q6300, Q6400, Q6600 v BXL 8 nhn trong vi nm ti. Chc chn nhng BXL ny s tha mn nhu cu ngi dng am m cng ngh v tc . Hin c loi CPU Quad-Core (4 nhn). Hng AMD cho ra cng ngh gm 2 b x ly, mi b 2-4 nhn. Tuy nhin loi CPU ny vn cha c mt trn th trng. 2.3 Cht liu v cng ngh ch to CPU 2.3.1.Cht liu Gm v organic (hu c) t dng Thoroughbred tr i u lm bng organic. Hin ti, cng ngh c p dng cho cc CPU Cht liu ch yu ch to cpu AMD l ceramic MOS (Metal Oxide Semi-Conductor bn dn xt kim loi), da vo mt lp xt kim loi nm trn tm
silicon kt ni bi cc ng hp cht dn in. Ngi ta ci tin MOS thnh CMOS (Complimentary MOS - MOS b tr) hot ng in th thp. y l 2 cng ngh c mt trong hu ht cc thit b my tnh. p ng nhu cu lm cho CPU ngy cng nhanh hn, t tiu hao nng lng hn cc cng ngh 0,25 -> 0,18 -> 0,13 micron ln lt ra i. Nhng chnh s thu nh cc cu ni trong CPU ny khin vic p dng MOS v CMOS tr nn ngy cng kh khn hn, do cc cu ni ny nm qu st nhau nn d dn n hin tng ng in cho ln cc cu bn cnh. Mt nhc im quan trng khc ca cng ngh MOS l phn silicon gia cc cu ni (c vai tr nh mt t in) phi np c in dung ti a c th ng - v li phi thot ht in dung c th m. Vic ny tn thi gian x l, v lng ph thi gian x l trn CPU. Cc nh sn xut CPU ci tin MOS hin c nh vic thay oxit nhm bng oxit ng lm tng xung nhp ln ng k. Nhng CPU c th t ti tc 5-10 GHz phi c mt gii php khc phc trit hn na 2 nhc im nu trn. chnh l cng ngh SOI (Silicon On Insulator). IBM pht trin cng ngh ny t nm 1990 cho CPU ca IBM, vi mc ch gim in nng s dng, tng xung nhp v.vnhng cng ngh ny vn cha thc s c ng dng ngay cho n cui th k 20, khi vic tng xung nhp cho cc dng CPU hin i cn thm cc phng php sn xut khc. Ci tin SOI l in dung ca t silicon gia cc cu c cc tiu ho lm gim thi gian cn thit thot/np, m v ng cu ni. iu ny gip tng xung nhp ln rt nhiu. S d SOI lm c iu l nh vic chn vo gia tm silicon mt lp vt liu cch in v li mt phn silicon nh gia cc cu ni. Lp vt liu cch in ny l mt dng ca xt silicon c to ra bng k thut SIMOX (Seperation by Implantation of Oxygen) - kh xi c p ln b mt ca silicon wafer p sut v nhit cao, khi silicon phn ng vi xi to nn 1 lp xt silicon bm vo silicon wafer bn di. SOI s khng thay th hon ton MOS/CMOS m ch ti u ho cho hai cng ngh ny: - CPU dng SOI s nhanh hn n 30% so vi CPU dng MOS/CMOS nu c cng mt xung ng h nh nhau. - Yu cu v in nng thp hn nhiu so vi MOS/CMOS (t hn khong 50%), CPU s chy mt hn - vt qua mt tr ngi ln ca vic nng tc cc b x l. - Cho php thu nh cng ngh sn xut CPU xung 0.09 micron hay thp hn cng vi SOI c ngha rng cc b vi x l s c tng tc rt nhanh v tc 5-10GHz s sm t c. Th nhng SOI cn c silicon t nguyn cht 100% - th m cng ngh hin nay cha sn xut c. Isonics l 1 cng ty ang nghin cu sn xut loi silicon wafer
ny. AMD thc s trng i vo SOI khc phc nhng nhc im ca CPU nh tiu tn nhiu in nng v chy nng hn. b x l K8 ca IBM, hay cn gi l Hammer dng cng ngh SOI ang c mong i. Ni lc cng ngh - HyperTransport, Cool'n'Quiet. AMD c bit u i CPU 64 bit vi cng ngh 'siu chuyn' HyperTransport v t iu chnh hot ng Cool'n'Quiet. HyperTransport gip vic truyn thng tin gia cc chip (cu nam, cu bc, BXL, b nh,...) nhanh hn, kh nng 'ni chuyn' vi mt chip hoc thit b khc nhanh hn vi lng tiu th ln hn. HyperTransport lm cho ng truyn rng hn, do tc truyn nhanh v nhiu hn. Cng ngh ny c th p dng cho tt c bng thng ca bo mch ch, t chipset n BXL, b nh, AGP, PCI,...Cool'n'Quiet l mt ci tin khc dnh cho dng BXL 64 bit, tc v in nng tiu th ca BXL s c iu chnh t ng. Nu c t ng dng c chy (BXL x l t) th Cool'n'Quiet s gim tc v in th BXL, ngc li, khi cn x l nhiu th BXL s c tng tc v in th. 2.4 Nguyn tc hot ng ca CPU CPU (Central Processing Unit) cng c gi l microprocessor hay processor l mt n v x l d liu trung tm. Cch n x l d liu nh th no hon ton ph thuc vo chng trnh c vit t trc. Chng trnh ni chung c th l mt bng tnh, mt b x l t hay mt game no . N ch tun theo cc th t (c gi l cc ch lnh hay cc lnh) c bn trong chng trnh. Khi mt chng trnh no c chy th th t c thc hin nh sau: a. Chng trnh lu bn trong a cng s c a vo b nh RAM. y chng trnh chnh l mt lot cc ch lnh i vi CPU. b. CPU s dng mch phn cng c gi l memory controller ti d liu chng trnh t b nh RAM. c. Lc d liu bn trong CPU s c x l. d. Nhng g din ra tip theo s ph thuc vo chng trnh va c np. CPU c th tip tc ti v thc thi chng trnh hoc c th thc hin mt cng vic no vi d liu c x l, nh vic hin th kt qu thc hin no ln mn hnh.
Hnh 2.4: D liu lu c a vo CPU

S truyn ti d liu gia a cng v b nh RAM c thc hin m khng s dng n CPU, nh vy n s lm cho h thng hot ng nhanh hn. Phng php ny c gi l bus mastering hay DMA (Direct Memory Access). Cc b vi x l ca AMD da trn sockets 754, 939 v 940 (Athlon 64, Athlon 64 X2, Athlon 64 FX, Opteron v mt s m hnh Sempron) c mt memory controller c nhng bn trong. iu c ngha rng vi cc b vi x l ny, CPU truy cp trc tip b nh RAM. 2.4.1.Clock Clock chnh l mt tn hiu c s dng ng b ha mi th bn trong my tnh. Hy xem trong hnh 2.4.1, y chnh l mt xung clock in hnh: n l mt xung hnh vung bin thin mc 0 v 1 vi mt tc c c nh. Trn hnh v ta c th thy 3 chu k ca xung clock ny. Bt u ca mi mt chu k khi tn hiu clock bin thin t 0 ln 1; chng c nh du n bng mt mi tn. Tn hiu clock c o theo n v c tn gi l Hertz (Hz), y l s chu k clock trong mi giy ng h. Mt xung clock 100MHz c ngha l trong mt giy ng h c 100 triu chu k xung nhp.
Hnh 2: Tn hiu xung clock Trong my tnh, tt c cc b nh thi u c o di dng cc chu k clock. V d, mt b nh RAM c tr l 5 th iu c ngha l n s gi chm 5 chu k xung nhp thc hin cng vic cung cp d liu. Trong CPU, tt c cc ch lnh gi chm mt s chu k xung clock no c thc thi. V d, mt ch lnh no c th c gi chm n 7 chu k xung clock c thc thi xong. CPU bit c bao nhiu chu k xung clock m mi ch lnh cn, n bit c iu ny bi CPU gi mt bng lit k cc thng tin ny. Chnh v vy nu CPU c hai ch lnh c thc thi v n bit rng ch lnh u tin s gi chm 7 chu k xung clock thc thi th n s t ng thc thi ch lnh k tip vo chu k clock th 8. R rng y l mt cch l gii chung cho CPU vi mt khi thc thi cc b vi x l hin i c mt s khi thc thi lm vic song song v n c th thc thi ch lnh th hai ti cng thi im vi ch lnh u. iu ny c gi l kin trc superscalar. Nu so snh hai CPU ging nhau, CPU no chy tc clock cao hn s
nhanh hn. Trong trng hp ny, vi mt tc clock cao hn, thi gian gia mi chu k clock s ngn hn, v vy nhng cng vic s c thc thi tn t thi gian hn v hiu xut s cao hn. Tuy nhin khi so snh hai b b vi x l khc nhau th iu ny hon ton khng ng. Nu ta ly hai b vi x l c kin trc khc nhau v d, khc nhau v nh sn xut nh Intel v AMD nhng th bn trong hai CPU ny l hon ton khc nhau. Nh cp, mi ch lnh cn n mt s chu k clock nht nh c thc thi. Chng ta hy ni rng b vi x l A cn n 7 chu k clock thc thi mt ch lnh no v b vi x l B cn 5 chu k clock thc hin mt ch lnh tng t. Nu chng ang chy vi cng mt tc clock th b vi x l B s nhanh hn, v n c th x l ch lnh ny tn t thi gian hn. Vi cc CPU hin i, c nhiu vn cn phi xem xt n hiu xut ny, v cc CPU c s lng khi thc thi khc nhau, kch thc cache khc nhau, cc cch truyn ti d liu bn trong CPU cng khc nhau, cch x l cc ch lnh bn trong cc khi thc thi v tc clock khc nhau vi th gii thc bn ngoi, Khi tn hiu clock ca b vi x l cao th c mt vn m chng ta gp phi. Bo mch ch, ni m b vi x l c ci t khng th lm vic bng cch s dng cng tn hiu clock. Nu xem bo mch ch, ta s thy mt s ng v rnh. Cc ng v rnh ny l nhng mch in ni mt s mch ca my tnh. Vn y l vi tc clock cao, cc dy mch in ny s bt u lm vic nh anten, chnh v vy tnh hiu, thay v n v tr cn n pha cui u dy li bin mt, c truyn i nh cc sng v tuyn. 2.4.2 External Clock V vy cc nh sn xut CPU bt u s dng mt khi nim mi, khi nim c gi l nhn xung clock, ng dng ny bt u c s dng trong b vi x l 486DX2. Vi c ch ny (c s dng trong tt c cc CPU ngy nay), CPU c mt clock ngoi (external clock) c s dng khi truyn ti d liu vo ra b nh RAM (s dng north bridge chip) v mt clock trong cao hn. a ra mt v d thc, trong s 3.4 GHz Pentium 4 th con s 3.4 GHz chnh l clock trong ca CPU, clock ny t c bng cch nhn 17 vi clock ngoi l 200 ca n. M phng v d ny trong hnh 2.4.2
Hnh 2.4.2: Clock trong v ngoi trn Pentium 4 3.4 GHz. S khc nhau ln gia clock trong v clock ngoi trn cc CPU hin i l cch vt qua nhc im t tnh nh ni trn tng hiu sut my tnh. Tip tc vi v d v Pentium 4 3.4 GHz trn, n phi gim tc ca n i 17 ln khi thc hin c d liu t b nh RAM! Trong sut qu trnh ny, n lm vic nh mt CPU vi tc 200MHz. Mt s k thut c s dng ti thiu ha nh hng ca s khc nhau clock ny. Mt trong s chng l s dng cache nh bn trong CPU. Phng php khc l truyn ti nhiu khi d liu trn mi mt chu k clock. Cc b vi x l ca hai hng Intel v AMD u s dng tnh nng ny, tuy nhin trong khi CPU ca AMD truyn ti hai d liu trn mt chu k clock th cc CPU ca Intel truyn ti 4 d liu trn mi chu k.
Hnh 2.4.3: Truyn ti nhiu d liu trn mi chu k clock
Chnh v iu nn cc CPU ca AMD c lit vo loi c tc gp hai clock ngoi thc. V d, mt CPU ca AMD vi external clock l 200MHz c lit vo CPU c clock ngoi l 400MHz. iu tng t cng c p dng i vi cc CPU ca Intel, vi external clock l 200MHz th CPU ca n s c tc clock ngoi l 800Mhz. K thut truyn ti hai d liu trn mi mt chu k clock c gi l DDR (Dual Data Rate), cn k thut truyn ti 4 d liu trn mt chu k clock c gi l QDR (Quad Data Rate). 2.4.3 S khi ca mt CPU Trn hnh 2.4.4 s khi c bn ca mt CPU hin i. C nhiu s khc nhau gia cc kin trc ca AMD v Intel. Vic hiu c cc kin thc c bn ny s l mt bc ta c th hiu c cch cc CPU ca Intel v AMD lm vic nh th no v s khc nhau gia chng. Dng nt chm trn hnh 2.4.4 th hin phn body ca CPU, v b nh RAM c t bn ngoi CPU. ng d liu gia b nh RAM v CPU thng l 64-bit (hoc 128-bit khi s dng cu hnh b nh knh dual), ang s dng clock nh hoc clock ngoi ca CPU (clock thp). S lng bit s dng v tc clock c th c kt hp trong mt khi c tn gi l tc truyn ti, tnh theo MB/s. tnh ton tc truyn ti, cng thc c thc hin tnh tc ny bng s bit x clock/8. Vi h thng s dng cc b nh DDR400 trong cu hnh knh n (64 bit) th tc truyn ti s l 3.200MB/s, cn vi h thng tng t s dng cc b nh knh dual (128 bit) s c tc truyn ti b nh l 6.400 MB/s.
Hnh 2.4.4. S khi c bn ca mt CPU Tt c cc mch bn trong phn nh du chm chy tc clock trong ca CPU. Ph thuc vo CPU m mt s phn bn trong c n c th chy tc clock cao hn. Cng vy, ng d liu gia cc khi CPU c th rng hn, ngha l truyn ti nhiu bit hn trn mi chu k clock 64 v 128. V d, ng d liu gia b nh cache L2 v cache ch lnh L1 trn cc b vi x l hin i thng l 256 bit. S bit c truyn ti trn mi chu k clock cng cao th s truyn ti s c thc hin cng nhanh (hay ni cch
khc, tc truyn ti s cao hn). Trn hnh 2.4.4, mi tn gia b nh RAM v cache nh L2; mi tn gia cc khi khc din t tc clock khc nhau v b rng ca ng d liu s dng. 2.4.4 Memory Cache Memory Cache l mt kiu b nh hiu sut cao, cng c gi l b nh tnh. Kiu b nh s dng trn b nh RAM chnh ca my tnh c gi l b nh ng. B nh tnh tiu tn nhiu nng lng in hn, t hn v c kch thc vt l ln hn so vi b nh ng, tuy nhin n li chy nhanh hn. N c th lm vic vi cng tc clock ca CPU, iu m b nh ng khng th thc hin c. Khi CPU cn np d liu ngoi, n phi lm vic tc clock thp hn do vy m k thut cache nh c s dng y khc phc nhc im ny. Khi CPU np d liu t mt v tr nh no th mch iu khin memory cache controller np vo cache nh mt khi d liu bn di v tr hin hnh m CPU np. V cc chng trnh c thc hin theo th t nn v tr nh tip theo m CPU s yu cu c th l b tr ngay di v tr nh m n np. Do memory cache controller np rt nhiu d liu di v tr nh u tin c c bi CPU nn d liu k tip s bn trong cache nh, chnh v vy CPU khng cn phi thc hin thao tc ly d liu bn ngoi: n c np vo bn trong cache nh nhng trong CPU, chnh v nhng trong CPU m chng c th truy cp bng tc clock trong. Cache controller lun lun quan st cc v tr nh v ang c np d liu t mt vi v tr nh sau khi v tr nh va c c. Mt v d thc t, nu mt CPU np d liu c lu ti a ch 1.000 th cache controller s np d liu t n a ch sau a ch 1.000. S n c gi l trang; nu mt b vi x l ny lm vic vi 4KB trang (gi tr in hnh) th n s np d liu t cc a ch 4.096 di v tr nh hin
Hnh 2.4.5: Memory cache controller lm vic nh th no hnh ang c np (a ch 1.000 trong v d). 1KB bng 1.024 byte, do l 4,096 ch khng phi 4,000. Chng ti th hin v d ny trn hnh 2.4.5. Memory cache cng ln th c hi cho d liu yu cu bi CPU y cng cao, chnh v vy CPU s gim s truy cp trc tip vo b nh RAM, do hiu sut h thng tng (hy nn nh rng khi CPU cn truy cp trc tip vo b nh RAM th n phi thc hin tc clock thp hn nn gim hiu sut ca ton h thng). Chng ta gi l hit khi CPU np mt d liu yu cu t cache v miss nu d liu yu cu khng c v CPU cn phi truy cp vo b nh RAM ca h thng. L1 v L2 tng ng l Level 1 v Level 2, c i din cho khong cch chng cch li CPU (khi thc thi). Mt s ng vc hay c y l ti sao c n 3 b nh Cache (L1 data cache, L1 instruction cache v L2 cache). Hy ch trn hnh 2.4.5 v thy c rng L1 instruction cache lm vic nh mt input cache, trong khi L1 data cache lm vic nh mt output cache. L1 instruction cache thng nh hn L2 cache ch hiu qu khi chng trnh bt u lp li mt phn nh ca n (loop), v cc ch lnh yu cu s gn hn vi khi tm np. Trn trang chi tit k thut ca mt CPU, L1 cache c th c th hin bng mt hnh nh hon ton khc. Mt s nh my sn xut lit k hai L1 cache ring bit (i khi gi cache ch lnh l I v cache d liu l D), mt s hng ghi s lng ca c hai l 128 KB nhng iu c ngha l 64 KB cho
cache ch lnh v 64 KB cho cache d liu. Mc d vy i vi cc CPU Pentium 4 v Celeronn i mi da trn socket 478 v 775 th khng c hin tng ny. Cc b vi x l Pentium 4 (v cc b vi x l Celeron s dng socket 478 v 775) khng c L1 instruction cache m thay vo chng c mt trace execution cache, y l cache c t gia khi gii m v khi thc thi. Chnh v vy y l L1 instruction cache nhng tn c thay i v mt v tr cng khc. Chng ta ang cp n iu ny l v y l mt li rt thng xy ra khi ngh rng cc b vi x l Pentium 4 khng c L1 instruction cache. Vy khi so snh Pentium 4 vi cc CPU khc mi ngi hy ngh rng L1 cache ca n nh hn nhiu. 2.4.6 R nhnh Nhng chng ti cp n mt vi ln t trc, mt trong nhng vn chnh i vi cc CPU l c qu nhiu miss i vi cache, v khi tm np phi truy cp trc tip vo b nh RAM (chm), nn lm chm c h thng. Thng s dng cache nh trnh c rt nhiu vn ny nhng c mt gii php in hnh c th gii quyt vn ny l r nhnh: Nu gia chng trnh c mt ch lnh JMP (jump hoc go to) gi chng trnh n mt v tr nh khc hon ton, v tr mi ny s khng c np trong L2 memory cache, m ch lm cho khi tm np vo v tr mt cch trc tip trong b nh RAM. gii quyt vn ny, cache controller ca cc CPU hin i phn tch khi nh m n np v bt c khi no c tm thy mt ch lnh JMP th n s np khi nh ny vo v tr trong L2 memory cache trc khi CPU x l ch lnh JMP .
Hnh 2.4.6. Gii php nhnh khng iu kin

iu ny qu mang li s thc thi d dng hn nhiu, vn y l khi chng trnh c mt r nhnh iu kin, ngha l a ch m chng trnh s vo phc thuc vo mt iu kin vn cha c bit. V d, nu a =< b vo a ch 1, hoc nu a>b th vo a ch 2. Minh ha v d ny trn hnh 2.4.7. iu ny s to ra mt miss i vi cache, v cc gi tr ca a v b hon ton khng c bit n v cache controller s ch ang xem xt cc ch lnh ging JMP. Gii php thc hin y l: cache controller np c hai iu kin vo cache nh. Sau khi CPU x l ch lnh r nhnh, n s n gin loi b mt trng hp khng c chn. Vic np b nh cache vi d liu khng cn thit s tt hn so vi vic truy cp vo b nh RAM.
Hnh 2.4.7: Gii php r nhnh c iu kin 2.4.7 Vic x l ch lnh Khi tm np chu hon ton trch nhim v vic np cc ch lnh t b nh. u tin, n xem xem ch lnh c yu cu bi CPU c trong L1 instruction cache hay khng. Nu khng c y, n s vo L2 memory cache. Nu ch lnh cng khng c trong L2 memory cache th n s phi np trc tip t b nh RAM. Khi ta bt my tnh, tt c cc cache u trng rng, tuy nhin khi h thng bt u np h iu hnh, CPU bt u x l cc ch lnh u tin t cng v cache controller bt u np cc cache v l nhng g bt u chun b thc hin x l mt ch lnh. Sau khi khi tm np c c ch lnh cn thit cho CPU c x l, n gi ch lnh ny n khi gii m. Khi gii m s ch ra ch lnh ny thc hin nhng nhim v g. N thc hin iu bng cch hi kin b nh ROM
tn ti bn trong CPU, c gi l microcode. Mi ch lnh m CPU hiu u c mt microcode ca n. Microcode s ra lnh cho CPU thc hin nhng g. N ging nh hng dn tng bc trong cc ti liu hng dn. V d, nu ch lnh np b sung a+b th microcode ca n s bo vi khi gii m rng n cn c hai tham s a v b. Khi gii m sau s yu cu khi tm np ly d liu c trong hai v tr nh k tip, ph hp vi cc gi tr ca a v b. Sau khi khi gii m dch xong ch lnh v ly c tt c d liu cn thit thc thi ch lnh, n s gi tt c d liu ny v hng dn tng bc v cch thc thi ch lnh n khi thc thi. Khi thc thi s thc thi ch lnh ny. Trn cc CPU hin i, ta s thy c nhiu khi thc thi lm vic song song. iu ny c thc hin tng hiu sut ca CPU. V d, mt CPU c 6 khi thc thi s c th thc thi n 6 ch lnh song song ng thi, chnh v vy theo l thuyt n hon ton c th thc hin c mt hiu sut bng vi 6 b vi x l m ch c mt khi thc thi. Kiu kin trc ny c gi l kin trc superscalar. Thng thng cc CPU hin i khng c nhiu khi thc thi ging nhau; chng c cc khi thc thi dnh ring cho mi loi ch lnh. Mt v d d hiu nht y l FPU, Float Point Unit, khi chu trch nhim thc thi cc ch lnh ton hc phc tp. Thng gia khi gii m v khi thc thi c mt khi (gi l khi gi i hoc lp biu) chu trch nhim v vic gi ch lnh n ng khi thc thi, c ngha l nu l mt ch lnh ton hc th n s gi ch lnh n FPU ch khng gi n khi thc thi chung. Cng v vy cc khi thc thi chung c gi l ALU (Arithmetic and Logic Unit). Cui cng, khi vic x l c thc hin, cc kt qu s c gi n L1 data cache. Tip tc v d a+b ca chng ta, kt qu s c gi ra L1 data cache. Kt qu ny c th sau c gi li n b nh RAM hoc n mt a im khc nh video card chng hn. Tuy nhin iu ny s ph thuc vo ch lnh k tip s c x l tip theo (ch lnh k tip c th l in kt qu ra mn hnh). Mt tnh nng th v khc m tt c cc b vi x l u c l pipeline trong thit k my tnh y l mt tuyn lp rp thuc phn cng lm tng tc x l cc lnh thng qua qu trnh thc hin, truy tm v ghi tr li. Thit k ny c kh nng c mt s ch lnh khc mt s tng khc ca CPU cng thi im. Sau khi khi tm np gi ch lnh n khi gii m, n s khng lm g (nhn ri)? Vy v vic thay th khng lm g bng cch cho khi ny ly ch lnh k tip th sao? Khi ch lnh u tin vo ti khi thc thi, khi ch lnh c th gi ch lnh th hai n khi gii m v ly ch lnh th ba, v qu trnh c tip tc nh vy. Trong CPU hin i c pipeline 11 tng (mi tng l mt khi ca CPU), n s c th c n 11 ch lnh bn trong ti cng mt thi im. Trong thc t, khi tt c cc CPU hiu i u c kin trc superscalar th s ch lnh ng thi bn trong CPU s cao hn. Cng vy, vi CPU pipeline c 11 tng, mt ch lnh c
thc thi hon ton s phi chuyn qua 11 khi. Nu cng c nhiu s tng hay khi nh vy th lng thi gian m mi ch lnh gi chm c thc thi s nhiu hn. Hay ni cch khc, hy nh rng mt s ch lnh c th chy bn trong CPU cng mt thi im. Ch lnh u tin np bi CPU c th gi chm 11 bc c x l xong, nhng khi n i ra th ch lnh th hai s cng c x l ngay sau (ch mt mt s bc gi chm ch khng phi l ton b 11 tng). C mt s mo khc c s dng bi cc CPU hin i nhm tng hiu sut h thng. Chng s xt hai trong s chng, l thc thi khng tun theo th t (OOO) v thc thi c suy on a. Thc thi khng tun theo th t (OOO) Hy nh rng chng ti ni rng cc CPU hin i c mt s khi thc thi lm vic song song v c mt s kiu khc i vi cc khi thc thi, nh ALU - khi thc thi chung, v FPU khi thc thi ton hc. Hy ly mt v d chung hiu r vn ny, chng ta hy cho CPU v d c 6 c my thc thi, 4 ch lnh chung (generic instruction) cho ALU v 2 ch lnh ton hc (math instruction) cho FPU. Chng ta cng cho rng chng trnh c th t ch lnh di y. 1. ch lnh chung (ALU) 2. ch lnh chung 3. ch lnh chung 4. ch lnh chung 5. ch lnh chung 6. ch lnh chung 7. ch lnh ton hc (FPU) 8. ch lnh chung 9. ch lnh chung 10. ch lnh ton hc
iu g s xy ra? Khi gi i/lp lch s gi 4 ch lnh u tin n cc khi ALU nhng sau ch lnh th 5 CPU s cn phi i cho mt ch lnh ca ALU ca chng c gii phng tip tc x l, v lc ny tt c
4 khi thc thi chung u bn c. iu ny khng tt bi v chng ta vn c 2 ch khi ton hc (FPU) cha dng n, r rng chng ang trong ch nhn ri. Chnh v vy, mt thc thi khng tun theo th t (OOO) (tt c cc CPU hin i u c tnh nng ny) s xem ch lnh k tip xem n c th c gi n mt trong hai khi thc thi ang nhn ri kia khng. Trong v d ca chng ta, n khng th, v ch lnh th 6 cng cn n mt khi thc thi chung (ALU) x l. C my thc thi khng tun theo th t vn tip tc cng vic tm kim ca n v tm ra rng ch lnh th 7 l mt ch lnh ton hc v c th c thc thi ti khi thc thi ton hc ang nhn ri. Do cc khi thc thi ton hc khc vn ang nhn ri nn n s vo chng trnh tm kim ch lnh ton hc khc. Trong v d ca chng ta, n s nhy qua ch lnh th 8 v 9 v np ch lnh th 10. Trong v d ca chng ta, cc khi thc thi s lun x l ti cng mt thi im, cc ch lnh c thc thi lc ny l ch lnh th 1, 2, 3, 4, 7 v 10. Tn OOO n t thc t rng CPU khng cn phi i m n c th ko mt ch lnh cui chng trnh v x l n trc cc ch lnh trn. R rng c my thc thi khng tun theo th t OOO khng th mi tm kim mt ch lnh nu khng c ch lnh no cn (v d nh trong v d trn l khng c ch lnh ton hc chng hn). C my ny ca tt c cc CPU c mt gii hn nht nh v s lng ch lnh m c c th tm (thng l 512). b. Thc thi c suy on Hy cho rng mt trong nhng ch lnh chung l mt ch lnh r nhnh c iu kin. Vy c my thc thi OOO s thc hin nhng g? Nu CPU b sung mt tnh nng gi l thc thi c suy on (tt c cc CPU hin i u c), n s thc thi c hai nhnh. Xem xt v d bn di. 1. ch lnh chung 2. ch lnh chung 3. nu a=<b ti ch lnh 15 4. ch lnh chung 5. ch lnh chung 6. ch lnh chung 7. ch lnh ton hc 8. ch lnh chung 9. ch lnh chung 10. ch lnh ton hc ... 15. ch lnh ton hc 16. ch lnh chung ...
Khi c my thc thi khng theo th t phn tch chng trnh ny, n s ko ch lnh 15 vo FPU, lc ny FPU ang nhn ri. Chnh v vy ti thi im ny, chng ta c c hai nhnh cng c x l ng thi. Nu khi CPU kt thc vic x l ch lnh th ba bit c a>b th CPU s loi b vic x l ca ch lnh 15. Ta c th ngh iu ny gy tn thi gian nhng trong thc t n hon ton khng tn thi gian. N hon ton khng ng bao nhiu CPU thc thi ch lnh ring , v FPU kiu g cng nhn ri. Mt khc nu a=<b th CPU s c c mc li v hiu sut y, v khi ch lnh th ba yu cu ch lnh 15, y l ch lnh c x l ri, tip theo l ch lnh 16, v cc ch lnh sau . Ch lnh 16 cng c x l bi c my thc thi khng theo th t. 2.5.CNG NGH SOI 2.5.1 Cc cng ngh ch to vi mch hin ti Vt liu bn dn l mt loi vt liu khng dn in iu kin thng nhng dn in mt iu kin c bit no . Cng ngh hin ti da vo mt lp xt kim loi nm trn phin silc kt ni bi cc ng hp cht dn in. Lp kim loi xt ng vai tr nh mt transistor, khi c ni vi ngun c in th cao, lp xt ny lm cho phn silc bn di tr nn dn in v cho dng in c truyn t cu ni ny qua cu ni kia, to thnh cc vi mch in t thuc loi bt/tt hay 1/0 - ngun gc ca cng ngh my vi tnh hin i (Hnh 2.5.1).
Hnh 2.5.1. Nguyn l lm vic ca vi mch in t Khi lm vic, dng in s chy t cu ni c in th cao sang cu ni c in th thp mi khi phin silc dn in. Ngi ta iu khin vic ny bng cch cho dng in i qua lp xt bn trn khi no cn dn in v ngt khi khng cn. Cng ngh ny c gi l cng ngh MOS
(Metal Oxide Semi-Conductor - bn dn xt kim loi). Mt cng ngh khc na l CMOS (Complimentary MOS - MOS b tr), CMOS ch yu cu in th thp chy qua lp xt kim loi, ngc vi MOS. Hu ht cc thit b bn dn, c bit l my tnh, u dng mt hoc c hai cng ngh ny. Cc cu ni trn cng ngy cng nh i cng vi s thu nh ca lin kt CPU qua cc cng ngh 0,25 0,18 0,13m... Cng ngh ni trn cng ngy cng kh p dng m khng xy ra hin tng ng in cho qua cc cu khc khng lin quan nm bn cnh do chng nm qu st nhau. Do vy, cng ngh ny cn phi c thay i nu mun c c nhng bc tin mi trong sn xut cc linh kin bn dn ni chung, v sn xut CPU ni ring. Cc ci tin khc cho cng ngh MOS/CMOS c sn cng mang n mt s tin b no , bng chng l c AMD v Intel u sn xut sn phm ca mnh bng cng ngh 0,13m. 2.5.2 Cng ngh SOI Trong cng ngh SOI, mt lp vt liu cch in c chn vo gia phin silc, li mt phn silc nh gia cc cu ni (Hnh 2.5.2). Li th ca SOI l vi s chn thm lp cch in ny, in dung ca t silc gia cc cu c cc tiu ho, do gim thi gian cn thit thot/np, m v ng cu ni. iu ny gip tng s cng vic x l c trong mt n v thi gian.
Hnh 2.5.2. Cng ngh SOI Hnh 2.5.3 l mt v d so snh gia mt mch in MOS v mt mch in SOI. im bt li ca vi x l dng cng ngh MOS l phn silc gia cc cu ni (c vai tr nh mt t in) phi np c in dung ti a c th ng - v li phi thot ht in dung khi m. Vic ny tn thi gian x l, lng ph thi gian x l trn CPU v l iu m c cc nh sn xut ln chng ta u khng mong mun. Cn i vi cng ngh SOI th phn silc gia cc cu nh, thi gian tch in nh, tc nhanh. Lp cch in c dng trong cng ngh SOI ph bin l mt dng ca
xt silc hay thm ch thu tinh, nhng c cu trc khc vi cu trc pha l dn in ca phin silc.
Hnh 2.5.3. So snh cng ngh MOS v SOI V mt ho hc, rt kh c th ghp c 2 lp silc c cu trc pha l v khng phi pha l vi nhau. Hng IBM s dng mt k thut c tn l SIMOX (Seperation by Implantation of Oxygen - ngn cch bi phng php cy kh xi) to mt lp ngn cch bng xt silc (SiO2) trn phin silc. Kh xi c p ln b mt ca b mt phin silc p sut v nhit cao, khi silc phn ng vi xi to nn mt lp xt silc bm vo phin silc bn di. Tc l h khng tm cch hn gn hai phn silc v xt silc vo nhau m to mt lp xt silc ngay trn phn silc c sn (Hnh 2.5.4).
Hnh 2.5.4. Phng php SIMOX a. u im ca SOI SOI c nhiu u im. Th nht, vic gim thi gian ng m cc cu ni c ngha rng cc b vi x l dng cng ngh ny s nhanh hn n
30% so vi cc b vi x l dng cng MOS/CMOS nu c cng mt xung ng h nh nhau. Mt u im na ca SOI l cc vi x l dng cng ngh ny s yu cu cng sut thp hn nhiu so vi MOS/CMOS. Mt xu hng vi nm gn y l khi mi ngi s dng nhiu cng ngh tin tin hn th cng sut ca cc b vi x l cng tng theo. V d, vi x l 486 yu cu cng sut khong 5W, trong khi mt vi x l Pentium tiu tn khong 10W v mt vi x l Pentium II 400MHz c cng sut tiu th khong 28W. Cng sut tng c ngha l hn ch nhng ng dng ca cc b vi x l, c bit l trong cc ng dng di ng. Kh nng ca cng ngh SOI l yu cu mt ngun cng sut thp xut pht t thc t mch in SOI c th hot ng ti in th thp vi cng hiu sut nh cng ngh CMOS ti in th cao. Do , SOI s c mt tc ng rt ln vo cc ng dng yu cu cng sut thp chng hn nh cc ng dng v tuyn v xch tay. Bn cnh , SOI cho php thu nh vi mch li ng k. Vic thu nh tin trnh sn xut xung 90nm (0,09m) hay thp hn cng vi SOI c ngha rng cc b vi x l s c tng tc rt nhanh v tc 5-10GHz s sm t c. b. Tng lai ca cng ngh SOI Tuy SOI c rt nhiu u im so vi MOS/CMOS nhng n s khng thay th hon ton MOS/CMOS m ch ti u ho cho hai cng ngh ny. SOI s c kt hp vi cc cng ngh khc to ra cc loi vi x l mi. AMD, Intel v IBM ang nghin cu cng ngh 90nm, bc tip theo trong qu trnh pht trin cng ngh ch to vi mch. Intel hi vng s a ra b vi x l Pentium 4 da trn cng ngh ny vo na cui nm 2003, trong khi cc sn phm ca AMD s c a vo sn xut trong qu 4 nm 2003 v a ra th trng vo qu 1 nm 2004. V va qua, IBM v AMD k mt tho thun cng nghin cu v pht trin cc loi vi x l mi da trn cng ngh 65nm v 45nm. y thc s l mt bc tin to ln trong cng ngh ch to vi mch v thc y vic ng dng rng ri vi mch vo tt c cc lnh vc nh cng ngh thng tin, vin thng v t ng ho. 2.6 kin trc Pentium M khi tt c cc CPU mi ca Intel s dng kin trc Pentium M, vic nghin cu kin trc ny l mt vic quan trng t ta c th hiu su c kin trc ca cc CPU Core Solo hay Core Duo (Yonah) v cng hiu c
lp nn tng cho vic tin ti kin trc li siu nh (Core microarchitecture), c s dng bi cc CPU Merom, Conroe v Woodcrest. Pentium M c xy dng da trn kin trc th h th 6 ca Intel, cng c s dng trong cc CPU Pentium Pro, Pentium II v Pentium III, tuy nhin li khng trn Pentium 4 nh nhiu ta ngh, mc ch ca n nhm vo cc my tnh di ng. Ta c th ngh Pentium M nh mt Pentium III c nng cao. Nhng cn ch khng nhm ln Pentium M vi Pentium III. i khi Pentium M cn c gi l Centrino. Qu thc n c th c gi nh vy khi ta c mt laptop CPU Pentium M, chipset Intel 855 hay 915 v Intel/PRO wireless LAN. Chnh v vy nu ta c mt laptop c xy dng trn Pentium M m khng c nhng iu kin b sung nh trn th khng th c coi l Centrino. C bn v cch kin trc P6 lm vic nh th no v nhng im g mi khi so snh Pentium M vi Pentium III. Cng v vy m trong ny ta s bit thm c v cch lm vic ca cc CPU Pentium Pro, Pentium II, Pentium III v Celeron (chng cng chnh l cc m hnh da trn P6, ngha l slot 1 v socket 370). Trc khi tip tc, chng ta hy xem xt n s khc nhau gia cc CPU Pentium M v Pentium III: Nhn bn ngoi, Pentium M lm vic ging nh Pentium 4, truyn ti 4 d liu trn mt chu k clock. K thut ny c gi l QDR (Quad Data Rate Gp bn ln tc d liu) v lm cho bus ni b c hiu sut tng gp 4 ln vi tc clock thc ca n, ta c th xem bng di y. Clock thc 100 MHz 133 MHz

Hiu sut 400 MHz 533 MHz
Tc truyn 3.2 GB/s 4.2 GB/s
L1 memory cache: Hai L1 memory cache 32 KB, mt cho d liu v mt cho ch lnh (Pentium III c hai L1 memory cache16 KB). L2 memory cache: 1 MB trn cc m hnh 130 nm (li Banias) hay 2 MB trn cc m hnh 90 nm (li Dothan). Pentium II ch c n 512 KB. Celeron M, phin bn r tin nht ca Pentium M cng c 512 KB L2 memory cache. H tr cho cc ch lnh SSE2. D bo nhnh cao cp: D bo nhnh c thit k li (v c da trn mch ca Pentium 4) ci thin hiu sut. S hp nht nhiu hot ng nh: B gii m ch lnh hp nht c hai hnh ng nh thnh mt c th tit kim c nng lng v
ci thin hiu sut. Chng ta s ni k hn v vn ny phn di.
Cng ngh SpeedStep nng cao, y l cng ngh cho php cc CPU c th gim c clock trong ch nhn ri tit kim thi gian sng ca pin. Mt s tnh nng nhm tit kim cho pin cng c b sung vo kin trc siu nh ca Pentium M, v mc ch ca cc CPU ny ban u c thit k cho my tnh di ng.
By gi chng ta hy i xem xt su hn v kin trc ca Pentium M. 2.6.1 Nguyn l ca Pentium M Nguyn l l mt danh sch tt c cc tng m ch lnh cho phi c thc thi theo ng thut ton. Intel khng tit l cc nguyn l ca Pentium M, chnh v vy chng ta s ni v nguyn l ca Pentium III. Nguyn l ca Pentium M c th s c nhiu tng hn so vi Pentium III nhng vic phn tch n s cho chng ta c c tng v kin trc ca Pentium M lm vic nh th no. Hy nh rng, nguyn l lm vic ca Pentium 4 c n 20 tng v nguyn l lm vic ca cc CPU Pentium 4 mi hn c da trn li Prescott c n 31 tng. Trn hnh 2.6.1 ta c th thy c nguyn l 11 tng ca Pentium III
Hnh 2.6.1: Nguyn l ca Pentium III Di y l gii thch mt cch c bn v mi tng, gii thch s lm sng t cch mi ch lnh c gn c thc hin nh th no bi cc b vi x l lp P6. y ch l tm tt v nhng gii thch c th d hiu IFU1: Np mt dng (32 byte tng ng vi 256 bit) t ch lnh L1 cache v lu n vo trong b m lung ch lnh (Instruction Streaming Buffer). * IFU2: Nhn dng cc ch lnh ng bin (16byte tng ng vi 128bit). V cc ch lnh x86 khng c mt chiu di c nh nn tng ny nh du v tr m mi ch lnh bt u v kt thc bn trong 16byte c np. Nu c bt k nhnh no bn trong 16byte th a ch c n s c lu ti Branch Target Buffer (BTB), chnh v vy CPU c th s dng nhng thng tin ny sau trn mnh tin on nhnh ca n. * IFU3: nh du n v gii m ch lnh ca mi ch lnh phi c gi. C ba khi gii m ch lnh khc nhau m chng ta s cp n chng trong phn di. * DEC1: Gii m ch lnh x86 thnh nhng ch lnh nh RISC (cc hot ng nh). V CPU c n 3 b gii m ch lnh nn n c th gii m c n 3 ch lnh cng lc. * DEC2: Gi cc ch lnh nh va c gii m vo hng i ch lnh gii m (Decoded Instruction Queue), hng i ny c kh nng lu tr
c n 6 ch lnh nh. Nu ch lnh c chuyn i nhiu hn 6 ch lnh nh th tng ny cn phi c lp li khng b st chng. * RAT: V kin trc P6 thc hin vic thi hnh out-of-order (khng tun theo th t, vit tt l OOO), nn gi tr ca thanh ghi cho c th c thay i bi mt ch lnh c thc thi trc v tr chng trnh din ra, sa d liu cn thit cho ch lnh khc. Chnh v vy gii quyt c kiu xung t ny, ti tng ny, thanh ghi gc c s dng bi ch lnh s c thay i thnh 40 thanh ghi bn trong m kin trc siu nh m P6 c. * ROB: Ti tng ny, ba ch lnh nh c gii m s np vo Reorder Buffer (ROB). Nu tt c d liu u cn thit cho vic thc thi ca mt ch lnh nh c cung cp v nu c mt khe m ti hng i ch lnh gii m Reservation Station th ch lnh ny s c chuyn vo hng i ny. * DIS: Nu ch lnh gii m ny li khng c gi n hng i trn th n c th c thc hin ti tng ny. Ch lnh gii m s c gi n khi thc thi thch hp. * EX: Ch lnh c gii m s c thc thi ti khi thc thi ny. Mi mt ch lnh gii m ny ch cn mt chu k xung nhp c thc thi. * RET1: Kim tra ti b m Reorder Buffer xem c bt k ch lnh gii m no c nh du nh thc thi khng. * RET2: Khi tt c cc ch lnh gii m c lin quan n ch lnh x86 thc s c xa ht khi b m Reorder Buffer v tt c cc ch lnh nh ( c gii m) c lin quan vi ch lnh x86 hin hnh c thc thi, th cc ch lnh ny s c xa khi b m Reorder Buffer v cc thanh ghi x86 s c nng cp (tin trnh c quay tr v tng RAT). Tin trnh tr li lm vic phi c thc hin theo th t. Ba ch lnh gii m c th c xa khi b m Reorder Buffer trong mi mt chu k clock. 2.6.2. Memory Cache v Khi tm np Nhng chng ti cp t trc, L2 memory cache ca Pentium M c th l 1 MB trn cc m hnh 130 nm (li Banias) hay 2 MB trn cc m hnh 90 nm (li Dothan). Trong khi n c hai memory cache L1, mt ci l 32KB cho ch lnh v ci kia l 32KB cho d liu. Nh gii thch phn trc, khi tm np c chia thnh 3 tng. Trong hnh 2.6.3, ta c th xem c cch khi tm np lm vic nh th no. Khi tm np np dng th nht (32 bytes = 256 bits) vo b m lung ch lnh ca n (Instruction Streaming Buffer). Sau b gii m chiu di ch lnh s nhn ra cc ranh gii ch lnh bn trong mi 16byte. V ch lnh x86 khng c chiu di c nh nn tng ny s nh du v tr mi ch lnh bt u v kt thc bn trong 128bit c np. Nu c mt ch lnh nhnh
no bn trong 128 bit th a ch s c lu vo Branch Target Buffer (BTB), chnh v vy CPU ca ta c th s dng cc thng tin ny sau trn mnh d bo nhnh ca n. BTB c 512 u vo. Sau khi tng Decoder Alignment Stage nh du khi gii m ch lnh no th mi ch lnh s c gi i. C 3 khi gii m ch lnh khc nhau s gii thiu phn di y.
Hnh 2.6.3: Khi tm np 2.6.4 Gii m ch lnh v thay i tn cho thanh ghi V kin trc P6 s dng cho cc b vi x l Pentium Pro kin trc CISC/RISC lai nn b vi x l phi chp nhn cc ch lnh CISC v cng c bit n vi t cch l cc ch lnh x86, iu ny l do tt c cc phn mm cung cp ngy nay u c vit bng kiu ch lnh ny. CPU ch s dng RISC khng phi l to ra cho my tnh, v n khng chy phn mm hin nay nh Windows v Office. V vy, gii php c s dng bi tt c cc b vi x l hin ang cung cp
trn th trng ngay nay t c Intel v AMD l u s dng gii m CISC/RISC. Bn trong, CPU x l cc ch lnh RISC nhng front-end ca n li ch chp nhn cc ch lnh CISC x86. Cc ch lnh CISC x86 c cp n nh ch lnh thng thng cn cc ch lnh RISC bn trong c cp n nh cc ch lnh c gii m. Mc d vy, cc ch lnh c gii m RISC khng th c truy cp mt cch trc tip, do chng ta khng th to phn mm da trn cc ch lnh ny vng trnh qua b gii m. Cng vy, mi CPU s dng cc ch lnh RISC ca ring n, cc ch lnh ny khng c cng b v khng tng thch vi ch lnh gii m t cc CPU khc. iu c ngha l cc ch lnh gii m ca Pentium M khc hon ton vi ch lnh gii m ca Pentium 4, s khc bit ny chnh l t cc ch lnh gii m Athlon 64. Ph thuc vo phc tp ca ch lnh x86 m n phi c chuyn thnh cc ch lnh gii m RISC. B gii m ch lnh Pentium M lm vic ging nh trn hnh 2.6.3. Nh nhng g ta c th quan st thy, c ba b gii m v mt b xp dy ch lnh gii m (MIS). Hai b gii m c ti u ha cho cc ch lnh n gin, trong cc ch lnh n gin l ch lnh thng ch l mt ch lnh gii m. Kiu ch lnh ny c chuyn i nh mt ch lnh gii m. Mt b gii m c ti u ha cho cc ch lnh x86 phc tp, ch lnh ny c th c chuyn i thnh 4 ch lnh gii m. Nu ch lnh x86 qu phc tp, c ngha l n chuyn i ti hn bn ch lnh gii m th n s c gi n MIS l b nh ROM, gm c mt danh sch cc ch lnh c th c dng thay th cho x86 trn.
Hnh 2.6.3: B gii m v i tn thanh ghi B gii m ch lnh c th chuyn i ln n 3 ch lnh x86 trn mi mt chu k clock, mt b gii m phc tp Decoder 0 v hai b gii m n gin
1 v 2, iu ny lm cho chng ta c cm gic hng i ch lnh c gii m (Decoded Instruction Queue) c th ln n 6 ch lnh gii m trn mi chu k clock, kch bn c th khi Decoder 0 gi 4 ch lnh gii m v hai b gii m kia gi mi b mt ch lnh c gii m hoc khi MIS c s dng. Cc ch lnh x86 phc tp s dng (MIS) Micro Instruction Sequencer c th d chm mt s chu k clock khi gii m, iu ph thuc vo s lng ch lnh c gii m s to ra t s chuyn i. Ta cn nn lu rng Decoded Instruction Queue ch c th gi c n 6 ch lnh gii m, chnh v vy nu c hn 6 ch lnh gii m c sinh ra bi b gii m cng vi MIS th mt chu k khc s c s dng gi cc ch lnh hin hnh trong hng i ti Register Allocation Table (RAT), lm trng hng i v chp nhn cc ch lnh gii m m khng ph hp vi n trc . Pentium M s dng mt khi nim mi i vi kin trc P6, khi nim ny c gi l hp nht ch lnh gii m. Trn Pentium M, mi mt b gii m ni hai ch lnh gii m thnh mt. Chng s ch c tch ra khi c thc thi, ti tng thc thi. Trn kin trc P6, mi ch lnh c chiu di 118 bit. Pentium M thay v lm vic vi cc ch lnh 118bit, n lm vic vi cc ch lnh c chiu di 236bit m chnh l kch thc ni ca hai ch lnh 118bit. Cn phi lu rng cc ch lnh gii m lin tc c chiu di l 118bit, cn nhng g c thay i l chng c truyn ti thnh mt nhm gm hai ch lnh c bn ny. tng ng sau phng php ny l tit kim nng lng v tng hiu sut. Vic gi mt ch lnh c kch thc 236bit di s nhanh hn vic gi hai ch lnh 118bit. Thm vo , CPU s tiu tn t ngun in hn v s c t ch lnh gii m lu thng bn trong n. Cc ch lnh c gn sau s gi n bng Register Allocation Table (RAT). Kin trc CISC x86 ch c 8 thanh ghi 32bit l EAX, EBX, ECX, EDX, EBP, ESI, EDI v ESP. S lng ny l qu thp v cc CPU hin i c th thc thi m out-oforder, v n s ph hng ni dung bn trong thanh ghi c, t gy ra hng cc chng trnh. Chnh v vy, ti tng ny, b vi x l thay i tn v ni dung ca cc thanh ghi c s dng bi chng trnh thnh mt trong 40 thanh ghi bn trong c (mi mt thanh ghi ny c 80 bit rng, nh vy vic chp nhn c d liu nguyn v d liu thay i), cho php ch lnh c th chy ti cng mt thi im vi ch lnh khc m s dng cng cng mt thanh ghi chun, hoc thm ch out-of-order, c ngha l cho php ch lnh th hai c th chy trc ch lnh th nht d l chng cng chung trn mt thanh ghi. 2.6.5 B m Reorder Buffer Khi cc ch lnh x86 v ch lnh c gii m c kt qu truyn ti gi
cc tng CPU theo cng mt th t th chng s xut hin trn chng trnh ang chy. Khi vo ROB, cc ch lnh gii m c th c np v thc thi out-of-order bi cc khi thc thi. Sau khi thc thi, cc ch lnh Hnh 2.6.4: b m Reorder c gi tr li v Reorder Buffer. Sau ti tng cui cng (Retirement), cc ch lnh thc thi c xut ra khi b m Reorder Buffer vi cng th t m chng np vo, c ngha l chng c chuyn theo th t. Trn hnh 2.6.4, ta c th c c tng v cch chng lm vic nh th no. Trn hnh 2.6.4, chng ta n gin ha trm dnh ring (Reservation Station) v cc khi thc thi c th to s d hiu cho b m ny. 2.6.6 Reservation Station v cc khi thc thi Nh chng ta cp t trc, Pentium M s dng cc ch lnh c ni (thng l hai ch lnh c ni vi nhau) t khi gii m n v tr cc cng gi i c t trn Reservation Station. Reservation Station gi i cc ch lnh gii m mt cch ring bit ( tch ghp i). Pentium M c 5 cng nh vy, cc cng ny c nh s t 0 n 4 trn Reservation Station. Mi cng c kt ni n mt hoc nhiu khi thc thi, cc ta c th xem trn hnh 2.6.6.
Hnh 2.6.6: Reservation Station v cc khi thc thi Di y l gii thch vn tt v mi khi thc thi c trn CPU ny:
IEU: Instruction Execution Unit Khi thc thi ch lnh l ni cc ch lnh thng c thc thi. Cng c bit n trong cc sch gii thiu v cu trc my tnh vi tn ALU (Khi logic s hc Arithmetic and Logic Unit). Cc ch lnh thng thng ny cng c hiu l cc ch lnh integer. FPU: Floating Point Unit l ni cc ch lnh ton hc phc tp c thc thi. Trc kia, khi ny cng c tn gi l math co-processor khi ng x l ton hc. SIMD: l ni cc ch lnh SIMD c thc thi, ngha l MMX, SSE v SSE2. WIRE: Cc hm phc tp. JEU: Jump Execution Unit x l cc nhnh v cng c bit n l Branch Unit. Shuffle: Khi ny thc thi mt loi ch lnh ca SSE c tn gi l shuffle. PFADD: Thc thi mt ch lnh SSE c tn gi PFADD (Packed FP Add) v c cc ch lnh COMPARE, SUBTRACT, MIN/MAX v CONVERT. Khi ny c cung cp ring, chnh v vy n c th bt u vic thc thi mt ch lnh gii m mi mi chu k clock d l n
khng hon tt c s thc thi ca ch lnh gii m trc. Khi ny c mt tr ba chu k clock, ngha l n s gi chm 3 chu k clock i vi mi ch lnh c x l. Reciprocal Estimates: Thc thi hai ch lnh SSE, mt c gi l RCP (Reciprocal.Estimate) v mt gi l RSQRT (Reciprocal Square Root Estimate). Load: Khi ny dng x l cc lnh hi d liu c c t b nh RAM. Store Address: Khi x l cc ch lnh hi d liu c ghi ti b nh RAM. Khi ny cng c tn gi l AGU, Address Generator Unit. Kiu ch lnh ny s dng c hai khi Store Address v Store Data ti cng mt thi im. Store Data: X l cc ch lnh hi d liu ghi vo b nh RAM. Loi ch lnh ny s dng c hai khi Store Address v Store Data ti cng mt thi im.
Ch lnh phc tp c th mt n vi chu k clock c x l. Chng ta hy ly mt v d ca cng 0, ni m khi floating point unit (FPU) c mt . Trong khi khi ny ang x l mt ch lnh rt phc tp, mt n vi clock thc thi th cng 0 s khng ngng hot ng: n lun lun gi cc ch lnh n gin n IEU mc d khi FPU li ang rt bn. Chnh v vy, mc d tc gi i ln nht l 5 ch lnh gii m trn mi mt chu k clock, nhng thc t CPU c th tng ln n 12 ch lnh gii m ti cng mt thi im. Cc ch lnh yu cu CPU c th c d liu c lu tr ti a ch RAM cho, Khi lu tr a ch (Store Address Unit) v lu tr d liu (Store Data Unit) c s dng ti cng mt thi im, mt dng cho nh a ch v mt dng cho c d liu. y l l do ti sao cng 0 v cng 1 c nhiu khi thc thi. Nu ch mt cht th s thy c Intel t trn cng mt cng c khi nhanh v t nht cng vi mt khi chm (phc tp). Chnh v vy, trong khi khi phc tp ang bn x l d liu th cc khi khc c th vn nhn cc ch lnh gii m t cng gi i tng ng ca n. tng ny l gi tt c cc khi thc thi lun lm vic. Sau mi mt ch lnh gii m c thc thi, n li tr v b m Reorder Buffer, y chnh l ni c ca n c thit lp ch thc thi. Sau ti tng cui (Retirement Stage), cc ch lnh gii m c c thc thi ca chng s c xa khi b m Reorder Buffer theo th t ban u ca n (ngha l theo th t m chng c gii m) v sau cc thanh ghi x86 c cp nht (ngc li bc ca tng t li tn ca thanh ghi). C th c n 3 ch lnh gii m c xa b t b m Reorder Buffer trn mi mt chu k clock. Sau , mi ch lnh ny c
thc thi hon ton. 2.6.7 Cng ngh SpeedStep nng cao Cng ngh SpeedStep c to ra tng thi gian sng ca pin v n c gii thiu u tin trong cc b vi x l ca Pentium III, M. Phin bn u tin ca cng ngh ny cho php cc CPU c th chuyn gia hai tn s clock mt cch ng. Ch tn s thp (LFM), ch cho php thi lng sng ca pin ln nht, v ch tn s cao (HFM), ch cho php chy CPU ti tc ln nht. CPU c hai t l nhn clock. T lnh LFM l t lnh factory-lock v ta khng th thay i c t l ny. Pentium M gii thiu cng ngh SpeedStep nng cao (Enhanced SpeedStep Technology), cng ngh ny l cng ngh c mt vi cu hnh clock v in p khc gia LFM (c nh l 600 MHz) v HFM. Mt v d cc ta c th d hiu hn trong trng hp ny, bng cu hnh clock v in p cho 1.6 GHz Pentium M da trn cng ngh 130nm: in p 1.484 V 1.42 V 1.276 V 1.164 V 1.036 V 0.956 V Clock 1.6 GHz 1.4 GHz 1.2 GHz 1 GHz 800 MHz 600 MHz
Mi mt m hnh ca Pentium M li c mt bng in p/clock ca ring n. Cn phi ch mt iu rng khi khng cn tn nhiu nng lng i vi laptop th khng nhng ch gim tc clock m cn gim c in p, vic gim in p s gip gim tiu tn rt nhiu pin my. Cng ngh Enhanced SpeedStep lm vic bng cch kim tra cc thanh ghi model c th MSR (Model Specific Registers) ca CPU, thnh phn ny c gi l Performance Counter. Vi thng tin thu nhn t b phn ny, CPU c th gim hoc tng clock/in p ca n ph thuc vo kh nng s dng ca CPU. n gin nu ta tng yu cu s dng CPU th n s tng clock/in p cn nu ta gim hiu sut s dng CPU th n s gim clock/in p.
Enhanced SpeedStep ch l mt trong nhng nng cao c thc hin vi kin trc siu nh Pentium M nhm mc ch tng thi lng s dng ca pin.
2.7 kin trc Core ca Intel Kin trc Core ca Intel xut hin vo nm 2006, y l kin trc c s dng trn tt c cc CPU mi vo thi im ny ca Intel nh Merom, Conroe v Woodcrest. Kin trc mi ny c xy dng trn kin trc ca Pentium M v c thm mt s tnh nng mi. Th u tin m ta cn phi lu l phn tn, kin trc Core khng c lin quan g vi cc CPU Core Solo v Core Duo ca Intel. Core Single l mt CPU Pentium M c sn xut cng ngh 65 nm, cn cc CPU Core Duo trc y c gi l Yonah l loi CPU dual-core cng ngh 65 nm da trn kin trc ca Pentium M. Pentium M c xy dng trn kin trc th h th 6 ca Intel, kin trc ny cng c s dng trong cc CPU Pentium Pro, Pentium II, Pentium III v cc CPU trc y ca Celeron ch khng phi trn Pentium 4 nh ta vn ngh, tng ban u c nhm n cc my tnh di ng. Nu ta c th ngh Pentium M l mt Pentium III nng cao th cng c th ngh kin trc Core l mt Pentium M nng cao. Kin trc Core s dng cu trc 14 tng. Cu trc ny l mt danh sch tt c cc tng m mt ch lnh c cho phi tri qua khi thc thi hon tt. Intel khng tit l cu trc ca Pentium M v chnh v vy cho ti nay h vn cha cng b nhng ch dn ca mi tng trong kin trc Core. Pentium III s dng cu trc 11 tng, Pentium 4 ban u c 20 tng v cc CPU Pentium 4 mi hn da trn li Prescott c bit c n 31 tng. 2.7.1 Cache nh v khi tm np Hy nh rng Cache nh l b nh tc cao (SRAM) c nhng vo bn trong CPU, s dng lu d liu m CPU c th cn n. Nu d liu c yu cu bi CPU khng c trong Cache nh th n s phi truy cp vo b nh RAM chnh, iu ny s lm gim tc ca CPU v b nh RAM c truy vp bng s dng tc clock ngoi ca CPU. V d, trn mt CPU 3,2GHz, Cache nh c truy cp tc 3,2GHz nhng b nh RAM chnh ch c truy cp tc clock 800MHz. Kin trc Core c to bng vic c khi nim multi-core, ngha l c nhiu chip trn mt ng gi. Trn Pentium D, phin bn dual-core ca Pentium 4, mi core u c Cache nh L2 ca ring n. Vn vi hai Cache ring y l ti mt thi im no khi mt li ny s dng ht Cache nh trong khi li kia li khng s dng ht hiu sut trn Cache nh L2 ca ring n. Khi xy ra iu ny th li u tin phi truy cp v ly d liu t b nh RAM chnh, thm ch Cache nh L2 ca li th hai l hon ton trng rng m l ra c th
c s dng lu d liu, trnh tnh trng li phi truy cp trc tip vo b nh RAM chnh. i vi kin trc Core, vn ny c gii quyt. Cache nh L2 c chia s, c ngha l c hai li u c th s dng Cache nh L2 mt cch chung nhau, cu hnh ng s c thc hin cho mi Cache. V d vi mt CPU c 2 MB L2 cache, mt li c th ang s dng 1,5MB cn li kia s dng 512 KB (0.5 MB), ngc li vi t l chia c nh 50-50 nh c s dng trc y trong cc CPU dual-core. Khi tin tm np c chia s gia cc li, ngha l nu h thng Cache nh np mt khi d liu c s dng bi li u tin th li th hai cng c th s dng d liu c np trn Cache ny ri. Trong cc kin trc trc, nu li th hai cn d liu ging nh d liu c np vo Cache ca li u tin th n vn phi truy cp thng qua bus ngoi (iu khin CPU lm vic tc clock ngoi, c tc clock thp hn tc clock trong) hoc thm ch ly d liu cn thit trc tip t b nh RAM ca h thng. Intel cng ci thin khi tin tm np ca CPU, a ra cc mu theo cch m CPU hin ang ly d liu t b nh on th d liu m CPU s tm np tip theo l g v np n vo Cache nh trc khi CPU yu cu. V d, nu CPU np d liu t a ch 1, sau yu cu d liu trn a ch 3 v sau yu cu tip d liu trn a ch 5 th khi tin tm np s on rng chng trnh s np d liu t a ch 7 v n s np t a ch ny ra Cache nh trc khi CPU yu cu n n. Qu thc tng ny khng c g mi m v tt c cc CPU t Pentium Pro s dng mt s kiu d on cung cp Cache nh L2. Trn kin trc Core, Intel c mt cht nng cao v tnh nng ny bng cch to ra mt khi tin tm np tm kim cc mu trong d liu tm np thay v cc b ch th tnh ca d liu m CPU s yu cu tip theo. 2.7.2 B gii m ch lnh: Macro-Fusion Mt khi nim mi c gii thiu trong kin trc Core l macro-fusion. Macro-fusion l kh nng gn (joining) hai ch lnh x86 vo thnh mt ch lnh micro-op. Cch lm ny c th ci thin c hiu sut ca CPU v tiu tn t nng lng ca CPU hn v n s ch thc thi mt ch lnh micro-op thay v hai. Mc d vy c ch ny li b hn ch i vi cc ch lnh so snh v cc ch lnh r nhnh c iu kin (c ngha l cc ch lnh CMP v TEST v Jcc). V d, chng ta hy xem on chng trnh di y: load eax, [mem1] cmp eax, [mem2]
jne target on chng trnh ny s thc hin np thanh ghi 32 bit EAX bng d liu c cha trong v tr nh 1, so sch gi tr ca n vi d liu c trong v tr nh 2 v nu chng khc nhau th (jne = jump if not equal), th chng trnh s truy cp vo a ch target, cn nu bng nhau th chng trnh s tip tc trn v tr hin hnh. Vi macro-fusion, cc ch lnh so snh (cmp) v r nhnh (jne) s c hp nht vo mt ch lnh micro-op. Chnh v vy sau khi chuyn qua b gii m ch lnh, phn chng trnh ny s ging nh di y: load eax, [mem1] cmp eax, [mem2] + jne target Nh nhng g thy trn, chng ta lu mt ch lnh. Cng t ch lnh c thc thi th my tnh ca ta s thc hin vic thc thi nhim v nhanh hn v tn t cng sut tiu th hn. B gii m ch lnh c trn kin trc Core c th gii m 4 ch lnh trn mt chu k clock, trong khi cc CPU trc nh Pentium M v Pentium 4 th ch c th gii m c n 3. y b gii m ch lnh ca kin trc Core ko n 5 ch lnh mi ln vo hng i ch lnh, thm ch n cn c th gii m n 4 ch lnh trn mt chu k clock. Chnh v vy nu hai trong s 5 ch lnh c ni thnh mt th b gii m vn c th gii m bn ch lnh trn mt chu k clock. V n s ch nhn ri cc b bt c khi no macro-fusion xy ra, ngha l b gii m s ch cung cp ba ch lnh ni micro-op u ra ca n trong khi c kh nng cung cp n bn. Trong hnh 2.7.1 bn di ta c th thy nhng thng tin tm tt gii thch trn.
Hnh 2.7.2: Khi tm np v b gii m ch lnh trong kin trc Core
2.7.3 Khi thc thi Pentium M c 5 cng gi i c t trn trm dnh ring Reservation Station ca n, nhng ch c hai cng c s dng gi i cc ch lnh micro-ops n cc khi thc thi. Ba ch lnh cn li c s dng bi cc khi c lin quan n b nh (Load, Store Address v Store Data). Kin trc Core cng c 5 cng gi i nh vy nhng ba trong s chng c s dng cho vic gi cc ch lnh ni micro-ops n cc khi thc thi. iu c ngha rng cc CPU ang s dng kin trc Core c th gi ba ch lnh micro-ops n khi thc thi trn mt chu k clock. Kin trc Core cung cp mt FPU m rng v mt IEU m rng (ALU) khi chng ta mang ra so vi kin trc Pentium M. iu ny c ngha rng kin trc Core c th x l n ba ch lnh s nguyn trn mt chu k clock, trong khi Pentium M ch c
hai. Tuy nhin khng phi tt c cc ch lnh ton hc u c th c thc thi trn tt c cc FPU. Nh nhng g ta c th quan st c trong hnh 2.7.3, cc ton t nhn floating-point ch c th c thc thi trong FPU th ba v phn thm vo floating-point ch c th c thc thi trn FPU th hai. Cc ch lnh Fpmov c th c thc thi trn FPU th nht hoc trn hai FPU khc nu khng c ch lnh phc tp hn (FPadd or FPmul) sn sng c gi n chng. Cc ch lnh MMX/SSE u c x l bi FPU. Trong hnh 2.7.3 ta s thy s khi chnh ca cc khi thc thi trong kin trc Core.
Hnh 2.7.3: Cc khi thc thi trong kin trc Core Mt s khc nhau ln gia hai kin trc Pentium M v Pentium 4 vi kin trc Core l trn kin trc Core, cc khi Load v Store c khi to a ch ca ring n nhng trong. Pentium 4 v Pentium M c cc khi to a ch ring v trn Pentium 4 ALU u tin c s dng lu d liu trn b nh. Di y l nhng gii thch nh v nhng khi c trong CPU ny:
IEU: Instruction Execution Unit l ni cc ch lnh c thc thi. Khi ny cng c bit n l khi ALU (Arithmetic and Logic Unit). Cc ch lnh thng thng cng c bit l cc ch lnh s nguyn. JEU: Jump Execution Unit x l r nhnh v cng c bit n vi tn Branch Unit. FPU: Floating-Point Unit. Khi ny chu trch nhim cho vic thc thi cc biu thc ton hc floating-point v cng c cc ch lnh MMX v
SSE. Trong CPU ny, cc FPU khng hon thin v mt s kiu ch lnh (FPmov, FPadd v FPmul) ch c thc thi trn cc FPU no : o FPadd: Ch c FPU ny mi c th x l cc ch lnh cng floating-point nh ADDPS. o FPmul: Ch c FPU ny mi c th x l cc ch lnh nhn floating-point nh MULPS o FPmov: Cc ch lnh cho vic np hoc copy mt thanh ghi FPU, nh MOVAPS (c dng truyn ti d liu n thanh ghi SSE 128-bit XMM). Kiu ch lnh ny c th c thc thi trn cc FPU, nhng ch trn cc FPU th hai v th ba nu cc ch lnh Fpadd hay Fpmul khng c trong Reservation Station. Load: khi ny dng x l cc ch lnh yu cu d liu c c t b nh RAM. Store Data: Khi ny x l cc ch lnh yu cu d liu c ghi vo b nh RAM.
Lu : rng cc ch lnh phc tp c th mt n mt s chu k clock trong khi x l. Chng ta hy ly mt v d v cng 2, ni khi FPmul nm . Khi khi ny ang x l mt ch lnh rt phc tp phi mt n vi chu k clock c thc thi th cng 2 s khng cht: n s lun gi cc ch lnh n gin n IEU trong khi FPU ang bn. 2.7.4 ng dn 128-bit bn trong v kin trc nh mi Mt tnh nng khc c trong kin trc Core l ng dn d liu 128 bit bn trong. Trong cc CPU trc, ng dn d liu bn trong ch c 64bit. y l mt vn i vi cc ch lnh SSE, ch lnh c gi l XMM c di 128 bit. Chnh v vy khi thc thi mt ch lnh bin i thnh 128 bit d liu th ton t ny c chia thnh hai ton t 64bit. ng d liu 128 bit mi lm cho kin trc Core tr nn nhanh hn trong vic x l cc ch lnh SSE c 128 bit d liu. Kin trc nh mi l k thut tng tc thc thi cc ch lnh c lin quan n b nh. Tt c cc CPU ca Intel t Pentium Pro u c c ch khng tun theo trnh t (out-of-order), c ch ny cho php CPU c th thc thi cc ch lnh khng ph thuc theo bt c mt th t no. Nhng g xy ra vi cc ch lnh lin quan n b nh c thc thi theo kiu truyn thng din ra theo mt th t ging ht vi th t chng xut hin trong chng trnh. V d, nu chng trnh gc c mt ch lnh nh store 10 at address 5555 v sau l mt ch lnh load data stored at 5555, th chng s khng th c o ngc (ngha l c thc thi khng tun theo th t) hoc ch lnh th hai s ly sai d liu, v d liu a ch
5555 b thay i bi ch lnh th nht. Nhng g m c ch kin trc nh mi thc hin l nh v v thc thi cc ch lnh c lin quan n b nh c th thc thi khng theo th t, tng tc thc thi ca chng trnh (chng ti s gii thch thm v iu ny c thc hin nh th no). Trong hnh 2.7.4, ta c mt v d v mt CPU khng c c ch nh ny (ngha l tt c cc CPU khng c xy dng trn kin trc Core). Nh nhng g ta c th nhn thy, CPU phi thc thi cc ch lnh khi chng xut hin trong chng trnh gc. V d, ch lnh Load4 khng lin quan ti bt k n b nh no v c th c thc thi trc, mc d vy n vn phi i tt c cc ch lnh khc.
Hnh 2.7.4: CPU khng c kin trc nh mi Trong hnh 2.7.5, ta s thy cch chng trnh trong hnh 2.7.4 lm vic nh th no trn CPU c kin trc Core. N bit rng ch lnh Load4 khng c lin quan n cc ch lnh khc v c th c thc thi trc.
Hnh 2.7.5: CPU vi c ch nh mi. iu ny ci thin c hiu sut ca CPU v lc ny ch lnh Load4 s c thc thi ngay t u, CPU c d liu cn thit cho vic thc thi cc ch
lnh khc cn n gi tr X c thc thi. Trong cc CPU thng thng, nu sau khi ch lnh Load4 ny c ch lnh Add 50, th ch lnh Add 50 (v tt c cc ch lnh khc ph thuc vo kt qu ) s phi i cc ch lnh khc nh th hin trong hnh 2.7.4 c thc thi. Vi kin trc nh mi ny, cc ch lnh c th c thc thi sm, v CPU lc ny s c c gi tr X t sm. 2.7.5 iu chnh tit lu cng sut Vi vic iu chnh tit lu cng sut tin tin, kin trc Core lm tit kim c nhiu nng lng tiu th hn so vi cc CPU trc . Tnh nng ny cho php CPU c th tt cc khi ang khng c s dng thi im . tng ny thm ch cn cho php nhiu u vit hn v khi CPU c th tt cc phn c th bn trong mi khi CPU tit kim nng lng, tn t cng sut v ci thin c thi gian s dng ca pin (trong trng hp xt n cc CPU di ng). Mt kh nng tit kim nng lng khc ca kin trc Core l ch bt cc bit cn thit trong cc bus bn trong CPU. Nhiu bus bn trong ca CPU c kch thc mt cch cng knh v lng ph. Chnh v vy thay cho vic bt tt c v d 480 ln d liu ca mt bus no th CPU c th ch cn bt 32 ln d liu ca n, tt c cc d liu trong ln u cn thit cho vic truyn ti ch lnh 32bit. * C th hi kh hiu tuyn b ny, v ta vn thng nghe thy rng kin trc ca Intel s dng cc ch lnh 32bit, v vy chng ti cn a ra gii thch ny lm sng t vn . Bn trong CPU, nhng g c xem xt mt ch lnh l m thao tc (opcode) ca ch lnh (ngn ng my tng ng vi ngn ng ch lnh assembly) cng vi tt c cc d liu c yu cu. iu ny l v c thc thi, ch lnh phi nhp vo c ch thc thi hon tt, ngha l cng vi tt c cc d liu c yu cu. Cng theo cch , kch thc ca mi m thao tc ch lnh x86 l mt bin v khng c inh l 32bit nh nhng g ta vn ngh. V d, mt ch lnh mov eax, (32bit data), dng lu (32-bit data) v thanh ghi EAX ca CPU c xem xt bn trong nh mt ch lnh 40bit (mov eax dch vo 8-bit opcode cng vi 32bit d liu). Vic cc ch lnh c s chiu di khc nhau l nhng g t trng cho tp ch lnh CISC (Complex Instruction Set Computing). 2.8 Cc m hnh Core 2 Duo cc model ca Core 2 Duo, Core 2 Quad v Core 2 Extreme cho ti thi im ny v s gii thiu thm v mt s tnh nng chnh ca chng.
Di y l nhng tm tt v cc tnh nng chnh ca h Core 2:

Kin trc li Cache nh ch lnh L1 32KB v Cache nh d liu L1 32KB cho mi li. Cng ngh Dual-core hoc cng ngh quad-core. Qu trnh sn xut 65 nm Socket 775. 800 MHz (200 MHz x 4), tc clock ngoi 1.066 MHz (266 MHz x 4) hoc 1.333 MHz (333 MHz x 4). Cache nh hp nht L2 2 MB, 4 MB hoc 8 MAILBOX. Cng ngh o ca Intel (ngoi tr Core 2 Duo E4300) Cng ngh Intel EM64T. Tp ch lnh SSE3. Execute Disable Bit Kh nng x l cng sut tiu th thng minh Cng ngh Enhanced SpeedStep.
Trn hnh 2.7.1 ta c th thy c mt bc tranh v chn ca Core 2 Duo CPU.
Hnh 2.7.1: Chn ca b vi x l Core 2

Cc model Trong bng di y chng ti s lit k tt c cc model ca Core 2 Duo c pht hnh cho ti gn thi im ny. Nhi Cloc Cloc Kch Chi L2 t k k S lng th tit k Model Cach TDP ti tron ngo transistor c thut e a ( g i chn C) 3 GH SLA9U E6850 z 2.66 SLA9V E6750 GHz 2.66 SL9ZF E6700 GHz 2.66 SL9S7 E6700 GHz 2.40 SL9ZL E6600 GHz 2.40 SL9S8 E6600 GHz 2.33 SLA9X E6550 GHz SLAA X E654 2.33 0 GHz 1,33 3 4 MB MHz 1,33 3 4 MB MHz 1,06 6 4 MB MHz 1,06 6 4 MB MHz 1,06 6 4 MB MHz 1,06 6 4 MB MHz 1,33 3 4 MB MHz 1,33 4 3 MB MHz 1,06 6 4 MB MHz 291 million 291 million 291 million 291 million 291 million 291 million 291 million 291 million 291 million 143 65 W mm2 143 65 W mm2 72
in p
0.962V -1.35V 0.962V -1.35V -
72
143 65 W 60.1 mm2
143 0.85V65 W 60.1 mm2 1.35V 143 1.18V65 W 60.1 mm2 1.32V 143 0.85V65 W 60.1 mm2 1.35V 143 65 W mm2 143 mm2 65 W 72 0.962 V1.35V 0.962 V1.35V -
72
2.13 SL94T E6420 GHz
143 65 W 60.1 mm2
2.13 SL9T9 E6400 GHz 2.13 SL9S9 E6400 GHz 1.86 SLA4U E6320 GHz 1.86 SL9TA E6300 GHz 1.86 SL9SA E6300 GHz SLA95
1,06 6 2 MB MHz 1,06 6 2 MB MHz 1,06 6 4 MB MHz 1,06 6 2 MB MHz 1,06 6 2 MB MHz
167 million 167 million 291 million 167 million 167 million 167 million 167 million
111 1.22V65 W 61.4 mm2 1.32V 111 0.85V65 W 61.4 mm2 1.35V 143 65 W 60.1 mm2 -
111 1.22V65 W 61.4 mm2 1.32V 111 0.85V65 W 61.4 mm2 1.35V 111 mm2 65 W 73.3 0.962 V1.35V
E450 2.20 800 2 0 GHz MHz MB 2 GH 800 2 MB z MHz
SL93F E4400 SLA98
111 1.16V65 W 61.4 mm2 1.31V 65 W 73.3 1.16V1.31V
800 E440 2 2 MHz 0 GHz MB 1.8 800 2 MB GHz MHz
111 167 millio mm2 n 167 million
SL9TB E4300
111 0.85V65 W 61.4 mm2 1.35V
Trong bng di y l lit k ca cc model Core 2 Quad. Chi tit k Model thut Nhit Clock L2 in S TDP ti ngoi Cache p nhn a ( C) 1,066 8 MB MHz 1,066 8 MHz MB 95 71 1.10V1.37V 4 4
Clock trong
SLACQ Q6700 2.66 GHz SL9UM Q6600 2.4 GHz
105 1.10V62,2 W 1.37V
SL9UM Q6600 2.4 GHz
1,066 105 1.10V8 MB 62,2 MHz W 1.37V
Trong bng di y l cc model Core 2 Extreme c pht hnh. Chi tit k thut Nhit L2 S TDP ti in p Cache nhn a ( C) 8 MB 8 MB 4 MB 8 MB 130 W 130 W 75 W 130 W 44 W 44 W 130 W 64.5 64.5 60.4 64.5 100 100 65 1.10V1.37V 1.10V1.37V 0.85V1.35V 1.10V1.37V 1.125V1.325V 1.10V1.37V 4 4 2 4 2 2 4 2
Model
Clock trong
Clock ngoi 1,333 MHz 1,066 MHz 1,066 MHz 1,066 MHz
SLAFN QX6850 3 GHz SL9UK QX6800 SL9S5 X6800 SLACP QX6800 SLA33 X7900 SLAF4 X7900 SL9UL QX6700 SLA6Z X7800 2.93 GHz 2.93 GHz 2.93 GHz
2.80 800 MHz 4 MB GHz 2.80 800 MHz 4 MB GHz 2.66 GHz 1,066 MHz 8 MB
2.60 800 MHz 4 MB 44 W 100 GHz
Bng di y l nhng g chng ti tng hp t cc chi tit k thut ca cc th h Centrino: Nn tng Tn m B vi x l Centrino Centrino Centrino Centrin Centrino Centrino Pro Duo Duo o Santa Rosa Core 2 Duo Santa Rosa Core 2 Duo Napa Napa Sonoma Carmel Pentium M
Pentium Core Duo Core Solo M (Yonah)
(Dothan) (Banias) Core 2 Duo (Meron) Chipset Intel 965 Intel 965 Express Express Intel 945 Intel 945 Intel 915 Intel 855 Express Express Express
Network Intel PRO Wireles / Wireless s 4965AG N
Intel PRO / Wireless Intel PRO Intel PRO Intel PRO Intel 2200BG / Wireless / Wireless / Wireless PRO / Intel PRO 4965AG 3945AB 3945AB Wireless / Wireless N G G 2100 2915AB G
CHNG 2:
BUS V TRUYN THNG TIN TRONG MY TNH
2.1.1. nh ngha BUS: Bus l ng truyn tn hiu in ni cc thit b khc nhau trong mt h thng my tnh. Bus c nhi u dy dn c gn trn mainboard, trn cc dy ny c cc u ni a ra, cc u ny c sp xp v cch nhau nhng khong quy nh c th cm vo nhng I/O board hay board b nh (bus h thng system bus). 2.1.2. Phn loi cc Bus trong h thng:
Cc Bus trong h thng my tnh Cng c nhng bus dng cho mc ch chuyn bit, th d ni 1 vi x l vi 1 hay nhiu vi x l khc hoc ni vi b nh cc b (local bus). Trong vi x l cng c mt s bus ni cc thnh phn bn trong ca b vi x l vi nhau. Ngi thit k chip vi x l c th tu la chn loi bus bn trong n, cn vi cc bus lin h bn ngoi cn phi xc nh r cc quy tc lm vic cng nh cc c im k thut v in v c kh ca bus ngi thit k mainboard c th ghp ni chip vi x l vi cc thit b khc. Mt s bus c s dng ph bin: Tn Bus Lnh vc p dng Camac Vt l ht nhn EISA Mt s h thng c chip 80386 IBM PC, My IBM/PC, IBM/PC/AT PC/AT Massbus My PDP 11, v VAX Microchannel My PS/2 Multibus I Mt s h thng 8086
Mt s h thng c chip 80386 Mt s h thng c chip x l ca Motorola Mt s h thng c chip x l h 68x0 ca Motorola Ni cch khc, cc bus ny phi tun theo 1 chun no . Tp cc quy tc ca chun cn c gi l giao thc bus (bus protocol) Ngoi ra, c rt nhiu loi bus khc nhau c s dng, cc bus ny ni chung l khng tng thch vi nhau. Bus thng phn loi theo 3 cch sau: Theo t chc phn cng (nh trn) Theo giao thc truyn thng ( bus ng b v khng ng b) Theo loi tn hiu truyn trn bus ( bus a ch, bus d liu,) 2.1.3. Bus h thng: Thng c nhiu thit b ni vi bus, mt s thit b l tch cc (active) c th i hi truyn thng trn bus, trong khi c cc thit b th ng ch yu cu t cc thit b khc. Cc thit b tch cc c gi l ch (master) cn thit b th ng l t (slave). V d: Khi CPU ra lnh cho b iu khin a c/ghi mt khi d liu th CPU l master cn b iu khin a l slave. Tuy nhin, b iu khin a ra lnh cho b nh nhn d liu th n li gi vai tr master. 2.1.3 Bus Driver v Bus Receiver: Tn hiu in trong my tnh pht ra thng khng iu khin bus, nht l khi bus kh di v c nhiu thit b ni vi n. Chnh v th m hu ht cc bus master c ni vi bus thng qua 1 chip gi l bus driver, v c bn n l mt b khuch i tn hiu s. Tng t nh vy, hu ht cc slave c ni vi bus thng qua bus receiver. i vi cc thit b khi th ng vai tr master, khi th ng vai tr slave, ngi ta s dng 1 chip kt hp gi l transceiver. Cc chip ny ng vai tr ghp ni v l cc thit b 3 trng thi, cho php n c th trng thi th 3 h mch (th ni). Ging nh vi x l, bus c cc ng a ch, ng s liu v ng iu khin. Tuy nhin, khng nht thit c nh x 1 1 gia cc tn hiu cc chn ra ca vi x l v cc ng dy ca bus. Th d: mt s chp vi x l c 3 chn ra, truyn ra cc tn hiu bo chp vi x l ang thc hin cc thao tc MEMR, MEMW, IOR, IOW hay thao tc khc, mt s Bus in hnh c cc ng trn. Cc vn quan trng nht lin quan n thit k bus l: xung clock bus (s phn chia thi gian, hay cn gi l bus blocking), c ch phn x bus (bus arbitration), x l ngt v x l li.
Multibus II Versabus VME
Cc bus c th c chia theo giao thc truyn thng thnh hai loi ring bit l bus ng b v bus khng ng b ph thuc vo vic s dng clock bus. 2.1.4 Bus ng b (Synchronous bus): Bus ng b c mt ng iu khin bi mt b dao ng thch anh, tn hiu trn ng dy ny c dng sng vung, vi tn s thng nm trong khong 5MHz 50MHz. Mi hot ng bus xy ra trong mt s nguyn ln chu k ny v c gi l chu k bus.
Chu k c trong Bus ng b Hnh trn l gin thi gian ca mt bus ng b vi tn s xung clock l 4MHz, nh vy chu k bus l 250ns. Gi s c 1 byte t b nh chim 3 chu k bus (750ns), tng ng vi T1, T2, T3 nh hnh v. V tt c cc tn hiu in thay i mc khng phi l tc thi, nn trn hnh v c cc sn xung, ta gi s cc sn xung ko di 10ns. T1 bt u bng cnh dng ca xung clock, trong mt phn thi gian ca T1, vi x l t a ch byte cn c ln bus a ch. Sau khi tn hiu a ch c xc lp, vi x l t cc tn hiu MREQ v RD tch cc mc thp, tn hiu MREQ (Memory Request) - xc nh truy xut b nh ch khng phi thit b I/O, cn tn hiu RD - chn c ch khng phi ghi d liu. T2: thi gian cn thit b nh gii m a ch v a d liu ln bus d liu. T3: ti cnh m ca T3, vi x l nhn d liu trn bus d liu, cha vo thanh ghi bn trong vi x l v cht d liu. Sau vi x l o cc tn hiu MREQ v R D .
Nh vy thao tc c hon thnh, ti chu k my tip theo vi x l c th thc hin thao tc khc. Cc gi tr c th v thi gian ca hnh v trn c th c gii thch chi tit nh sau: TAD: TAD <110ns, ngha l nh sn xut vi x l m bo rng trong mi chu k c ton hng t b nh, vi x l s a ra tn hiu a ch khng nhiu hn 110 ns tnh t thi im cnh dng ca T1. TDS: gi tr nh nht l 50ns, c ngha l nh sn xut b nh phi m bo rng d liu n nh trn bus d liu t nht l 50ns trc im gia cnh m ca T3. Yu cu ny m bo cho vi x l c d liu tin cy. Khong thi gian bt buc i vi TAD v TDS xc nh rng trong trng hp xu nht, b nh ch c 250 + 250 + 125 110 50 = 465 ns tnh t thi im c tn hiu a ch cho ti khi to ra d liu trn bus d liu. Nu b nh khng c kh nng p ng nhanh, n pht tn hiu WAIT trc cnh m ca T2. Thao tc ny a thm cc trng thi ch wait state (tc l a thm vo 1 chu k bus), khi b nh a ra tn hiu n nh, n s o WAIT thnh WAIT TML: m bo tn hiu a ch s c xc lp trc tn hiu MREQ t nht 60ns. Khong thi gian ny s quan trng nu tn hiu MREQ iu khin qu trnh to tn hiu chon chip CS hay CE do mt s chip nh i hi phi nhn c tn hiu a ch trc tn hiu chn chip. Nh vy, khng th chn chip nh vi thi gian thit lp 75ns. TM, TRL cho php hai tn hiu MREQ v RD tch cc trong khong thi gian 85ns tnh t thi im xung ca xung clock T1. Trong trng hp xu nht, chp nh ch c 250 + 250 85 50 = 365ns sau khi 2 tn hiu trn tch cc a d liu ra bus d liu. S bt buc v thi gian ny b sung thm s bt buc thi gian vi tn hiu clock. TMH, TRH : thi gian cc tn hiu MREQ v RD c o sau khi d liu c vi x l nhn vo. TDH: Thi gian b nh cn gi data trn bus sau khi tn hiu RD o. Gin thi gian mt chu k c trn bus ng b c n gin ho so vi thc t, trong cc tn hiu cn s dng ln hn nhiu. Gi tr ti hn ca cc thng s cho trong bng sau: K hiu Tham s Min (ns) Max (ns) TAD Thi gian tr ca a ch 100 TML Thi gian a ch n nh trc MREQ 60 b
TM TRL TDS TMH TRH TDH
Thi gian tr ca MREQ so vi cnh m ca T1 Thi gian tr ca RD b so sn xung ca tn hiu ng b T1 Thi gian thit lp d liu trc sn xung ca tn hiu xung clock( tn hiu ng h) Thi gian tr ca MREQ b so vi sn xung ca tn hiu ng h T3 Thi gian tr ca RD b so vi sn xung ca tn hiu ng h T3 Thi gian lu tr d liu t lc o tn hiu RD b
85 85 50 85 85 0
Truyn theo khi: Ngoi cc chu k c/ghi, mt s bus truyn d liu ng b cn h tr truyn d liu theo khi. Khi bt u thao tc c khi, bus master bo cho slave bit s byte cn c truyn i, th d truyn con s ny i trong chu k T1, sau ng l truyn i 1 byte, slave a ra trong mi chu k 1 byte cho ti khi s byte c thng bo. Nh vy, khi c d liu theo khi, n byte d liu cn n+2 chu k clock ch khng phi 3n chu k. Mt cch khc cho truyn d liu nhanh hn l gim chu k. v d trn: 1 byte c truyn i trong 750ns, vy bus c tc truyn 1.33MBps. Nu xung clock c tn s 8MHz, thi gian 1 chu k ch cn mt na, tc s l 2.67MBps. Tuy nhin, gim chu k bus dn n kh khn v mt k thut, cc tn hiu truyn trn cc ng khc nhau khng phi lun c cng tc , dn n hiu ng bus skew. iu quan trng l thi gian chu k phi di hn so vi skew trnh vic nhng khong thi gian c s ho li tr thnh cc i lng bin thin lin tc. 2.1.5 Bus bt ng b( Asynchronous bus) Bus bt ng b khng s dng xung clock ng b, chu k ca n c th ko di tu v c th khc nhau i vi cc cp thit b khc nhau. Lm vic vi cc bus ng b d dng hn do n c nh thi mt cch gin on , tuy vy chnh c im ny cng dn n nhc im. Mi cng vic c tin hnh trong khong thi gian l bi s ca xung clock, nu 1 thao tc no ca vi x l hay b nh hon thnh trong 3.1 chu k th n cng s phi ko di trong 4 chu k. Khi chn chu k bus v xy dng b nh, I/O card cho bus ny th kh c th tn dng nhng tin b ca cng ngh. Chng hn sau khi xy bus vi s nh thi nh trn,
cng ngh mi a ra cc vi x l v b nh c thi gian chu k l 100ns ch khng cn l 750ns nh c, th chng vn chy vi tc thp nh cc vi x l, b nh loi c, bi v giao thc bus i hi b nh phi a c d liu ra v n nh trc thi im cnh m ca T3. Nu c nhiu thit b khc nhau cng ni vi 1 bus, trong c th c mt s thit b hot ng nhanh hn hn cc thit b khc th cn phi t bus hot ng ph hp vi thit b c tc thp nht. Bus bt ng b ra i nhm khc phc nhng nhc im ca bus ng b. Trc ht master pht ra a ch nh m n mun truy cp, sau pht tn hiu MREQ b tch cc xc nh cn truy xut b nh. Tn hiu ny cn thit khi b nh v cc cng I/O s dng chung min a ch. Sau khi pht a ch, bn master cng phi pht tn hiu RD tch cc bn slave bit rng master s thc hin thao tc c ch khng phi ghi. Cc tnh hiu MREQ b v RD b c a ra sau tn hiu a ch mt khong thi gian ph thuc tc hot ng ca master. Sau khi 2 tn hiu ny n nh, master s pht ra tnh hiu MSYN (master synchrization) mc tch cc bo cho slave bit rng cc tn hiu cn thit sn sng trn bus, slave c th nhn ly. Khi slave nhn c tn hiu ny, n s thc hin cng vic vi tc nhanh nht c th c, a d liu ca nh c yu cu ln bus d liu. Khi hon thnh slave s pht tn hiu SSYN (slave synchronization) tch cc.
Chu k c ca Bus bt ng b Master nhn c tn hiu SSYN tch cc th xc nh c d liu ca slave sn sng nn thc hin vic cht d liu, sau o cc ng a ch cng nh cc tn hiu MREQ, RD, v SSYN. Khi slave nhn c tn hiu MSYN khng tch cc, n xc nh kt thc chu k v o tn hiu SSYN lm bus tr li trng thi ban u, mi tn hiu u khng tch cc, ch bus master mi. Trn gin thi gian ca bus bt ng b, ta s dng mi tn th hin nguyn nhn v kt qu MSYN tch cc dn n vic
truyn d liu ra bus d liu v ng thi cng dn n vic slave pht ra tn hiu SSYN tch cc, n lt mnh tn hiu SSYN li gy ra s o mc ca cc ng a ch, MREQ b, RD b, v SSYN. Cui cng s o mc ca MSYN li gy ra s o mc tn hiu SSYN v kt thc chu k. Tp cc tn hiu phi hp vi nhau nh vy c gi l bt tay ton phn (full handshake), ch yu gm 4 tn hiu sau: MSYN tch cc. SSYN b tch cc p li tn hiu MSYN. MSYN c o p li tn hiu SSYN b (tch cc). SSYN b c o p li tnh hiu MSYN khng tch cc. Ta c th nhn thy bt tay ton phn l c lp thi gian, mi s kin c gy ra bi 1 s kin trc ch khng phi bi xung clock. Nu 1 cp master-slave no hot ng chm th cp master-slave k tip khng h b nh hng. Tuy u im ca bus bt ng b rt r rng, nhng trong thc t phn ln cc bus ang s dng l loi ng b. Nguyn nhn l cc h thng s dng bus ng b d thit k hn. Vi x l ch cn chuyn cc mc tn hiu cn thit sang trng thi tch cc l b nh p ng ngay, khng cn tn hiu phn hi. Ch cn cc chn ph hp th mi hot ng u tri chy, khng cn phi bt tay. 2.1.6 Phn x bus (bus arbitration) Trong h thng my tnh khng phi ch c CPU lm bus master, cc chip I/O cng c lc lm bus master c th c hay ghi b nh v gi ngt. Cc b ng x l cng c th lm bus master. Nh vy ny sinh ra vn : iu g s xy ra khi 2 thit b tr ln ng thi cn lm bus master? T cn c mt c ch phn x trnh s hn lon ca h thng. C ch phn x c th l tp trung hay khng tp trung. 2.1.7 Phn x bus tp trung Nhiu vi x l c n v phn x c ch to nm ngay trong chip CPU, trong mt s my tnh mini, n v ny nm ngoi chp CPU. Theo c ch ny th b phn x (arbiter) ch c th bit c yu cu chim dng bus hay khng m khng bit c bao nhiu n v mun chim dng bus. Khi arbiter nhn c yu cu, n s pht ra 1 tn hiu cho php trn ng dy (bus grant: cho php s dng bus). ng dy ny ni qua tt c cc thit b I/O theo kiu ni tip. Khi thit b nm gn arbiter nht nhn c tn hiu cho php, n kim tra xem c phi chnh n pht ra yu cu hay khng. Nu c th n s chim ly bus v khng truyn tip tn hiu cho php trn ng dy. Nu khng th n s truyn tn hiu cho php ti thit b k tip trn ng dy, vi thit b ny s vic xy ra ging thit b trc n, qu trnh
c tip din cho n khi c mt thit b chim ly bus. S x l nh vy c tn gi l daisy chaining (chui cnh hoa). im ni bt ca s ny l cc thit b c gn th t u tin tu thuc vo v tr ca n so vi arbiter, thit b gn hn th mc u tin cao hn.
Phn s Bus tp trung mt mc ni tip Mt s loi bus c nhiu mc u tin, vi mi mc u tin c ng yu cu bus (bus request) v ng dy cho php bus (bus grant). V d: gi s 1 bus c 2 mc u tin 1 v 2 (cc bus thc t c 4, 8 hay 16 mc). Mi thit b trong h thng my tnh ni vi 1 trong cc mc yu cu bus, cc ng thng c s dng nhiu hn c gn vi ng dy c mc u tin cao hn. v du, cc thit b 1, 2 s dng mc u tin 1, cn cc thit b 3, 4 s dng mc u tin 2.
Phn s Bus tp trung 2 mc Nu c mt s thit b cc mc u tin khc nhau cng yu cu, arbiter ch pht ra tn hiu grant i vi yu cu c mc u tin cao nht. Trong s cc thit b c cng mc u tin, thit b no gn arbiter hn s u tin hn. V mt k thut, khng cn ni ng grant level 2 gia cc thit b v chng khng bao gi i hi bus mc 2. Tuy nhin, trong thc t thun tin cho vic lp t ngi ta hay lm nh sau: ni tt c cc ng grant thng qua tt c cc thit b, nh vy s d dng hn l ni cc ng
grant mt cch ring bit, v t cn c vo thit b no c quyn u tin cao hn. Mt arbiter(phn x) c ng dy th 3 ni ti cc thit b cc thit b xc nhn nhn c tn hiu grant v chim dng bus ng ACK (acknowledgement). Ngay sau 1 thit b pht tn hiu tch cc trn ng dy ACK, c th o tn hiu trn cc ng dy request v grant xung mc khng tch cc. Cc thit b khc c th yu cu bus khi thit b u tin ang dng bus. Khi s truyn thng kt thc, bus master k tip s c la chn. Cch lm vic nh vy lm tng hiu qu s dng bus, nhng cn thm 1 ng truyn tn hiu v cu trc thit b cng phc tp hn. Cc chip trong my tnh PDP-11 v cc chip Motorola lm vic vi cc bus nh vy. 2.1.7 Phn x bus khng tp trung: Trong Multibus, ngi ta cho php c th la chn s dng phn x bus tp trung hay khng tp trung, c ch phn x bus khng tp trung c thc hin nh sau:
Phn x Bus khng tp trung trong multibus C ch s dng 3 ng dy, khng ph thuc vo s lng thit b ni vi bus: Bus request: yu cu chim dng bus. Bus busy: ng bo bn, c bus master t mc tch cc khi c thit b ang chim dng bus Bus arbitration: c mc ni tip thnh 1 chui xch qua tt c cc thit b ngoi vi. u ca chui ny c gn vi mc in p 5V ca ngun nui. Khi khng c n v no yu cu chim dng bus, ng dy phn x bus truyn mc tch cc ti tt c cc thit b trong chui xch. Khi 1 n v no mun chim dng bus, u tin n kim tra xem bus c rnh khng v u vo In ca ng trng ti bus c mc tch cc hay khng. Nu khng (not active) th n khng tr thnh bus master. Ngc li, n s o u Out thnh khng tch cc, lm cho cc thit b ng sau n trong chui xch c u In khng tch cc. Khi trng thi c th hiu lm (khong thi gian tn hiu trn u In v Out ang thay i) qua i, ch cn
li duy nht 1 thit b c u In tch cc v Out khng tch cc. Thit b ny tr thnh bus master, n s t bus busy tch cc v bt u truyn thng tin trn bus. 2.1.8 X l ngt: trn, ta ch kho st cc chu k bus thng thng, trong master nhn hay gi thng tin t / n slave. Mt ng dng quan trng na ca bus l dng x l ngt. Khi CPU ra lnh cho thit b I/O lm mt vic g , n thng ch i tn hiu ngt do thit b I/O pht ra khi hon thnh cng vic c CPU yu cu. Khi nhn c tn hiu ngt, CPU s p ng ngay, c th nhn d liu do thit b I/O truyn v, hay gi tip d liu ra thit b I/O, hay CPU s s dng bus cho mt thao tc khc. Nh vy chnh ngt pht ra tn hiu yu cu s dng bus. V c th nhiu thit b ngoi vi cng pht ra ngt, cho nn cn c 1 c ch phn x ging nh i vi cc bus thng thng. Gii php thng dng l gn cc mc u tin cho cc thit b v s dng 1 arbiter tp trung trao quyn u tin cho cc thit b quan trng thng xuyn c s dng.
2.2 Bus m rng (Expansion bus)

Bus m rng cho php PC lin lc c vi cc thit b ngoi vi, cc thit b ny c ci t qua cc khe cm m rng (expansion slot). Cc thng s chnh ca bus m rng: tc truyn ti a gia cc thit b vi nhau v gia cc thit b vi b nh chnh, s ng a ch (s lng nh c th c truy xut bi 1 thit b), s ng ngt cng, . 2.2.1 Bus ISA (Industry Standard Architecture) Bus ISA dng cho h thng ch c iu khin bi 1 CPU trn bng mch chnh, tc l tt c cc chng trnh v thit b u ch c iu khin bi CPU . Tn s lm vic cc i l 8.33 MHz ( tc chuyn ti cc i l 16.66 MBps vi s liu 2 bytes). B rng d liu l 8 hay 16 bits. ISA c 24 ng a ch nn qun l c 16 MB b nh. Bus ISA tng thch 90% vi bus AT. 2.2.2 Bus EISA v MCA: S dng cho cc CPU 32 bits ( s liu v ng a ch) t 80386 tr i. 2.2.3 Bus EISA (Extended ISA): y l chun m rng ca ISA b tr cc d liu 32 bits nhng vn gi c s tng thch vi mch ni ghp c. Bus EISA c 2 nc, cc tn hiu ISA c gi qua nc trn v cc tn hiu ph tr EISA qua nc di. Cc c trng ca EISA nh sau: V mt c kh: c nhiu chn cm hn nhng vn tng thch vi ISA
rng d liu: c th truy xut 2 ng 8 bits (tng thch vi ISA), hay 2 ng 16 bits Do. , n v qun l bus 32 bits c th chuyn ti 4 byte vi b nh hoc thit b ngoi vi. iu ny gp phn tng tc truyn ti ln khong 33 MBps so vi 16.66 MBps ca ISA. rng a ch: ngoi 24 ng nh ISA cn thm 8 ng b sung na, do c th nh a ch trong 4 GB b nh. Phn cng c thit k theo h thng EISA phc tp hn ISA v n cng phi thc hin cc chu k bus tng thch vi ISA. EISA c th thc hin phn x bus, n cho php vi x l nm ngoi bng mch chnh c th iu khin ton b bus. iu ny rt hiu qu trong cc h thng a x l (multiprocessor). Hng Intel pht trin 4 chip in t phc v cho bus EISA nh sau: o ISP (Intergrated system peripheral) o BMIC (Bus master interface controller) o EBC (EISA bus controller) o EBB (EISA bus buffer) 2.2.3 Bus MCA (Micro Channel Architecture) Phc v cho h thng IBM PS/2 khng tng thch vi bus ISA, c th hot ng vi 16 hay 32 bits d liu. N c nhiu ng dn hn ISA, thit k phc tp cho php gim bt cc nhiu cao tn ca PC ti cc thit b xung quanh. Tc truyn d liu c th ln ti 160 MBps. 2.2.4 Bus cc b (Local Bus) Nhc im ca cc bus chun trn l mc d xung clock ca CPU rt cao nhng cng ch lm vic vi cc ngoi vi vi tc truyn ti khng qu 33MBps. iu ny khng th p ng c tc ca cc card ho cm vo khe cm ca bus m rng trong ch ha. Chun cc bus cc b to thm cc khe c m m rng ni trc tip vo bus cc b (bus ni gia CPU v cc b m). Do vy, bus m rng loi ny cho php truy xut ln trn 32 bit cng nh tn dng c tc xung clock ca chnh CPU, trnh c ro cn 8.33MHz ca bus h thng. Theo hng gii quyt ny, Intel pht trin bus PCI v U ban VESA (Video Electronics Standards Association) pht trin bus VL. 2.2.5 Bus PCI (Peripheral Component Interconnect)
S Bus PCI Bus PCI l bus ca i486 trong d liu v a ch c gi i theo cch thc dn knh (multiplexing), cc ng a ch v d liu c dn chung trn cc ng ca PCI. Cch ny tit kim c s chn PCI nhng li hn ch tc v phi cn 2 xung clock cho mt qu trnh truyn d liu (1 cho a ch v 1 cho d liu). Vic ni gia CPU, b nh chnh, v bus PCI c thc hin bng c u PCI (PCI bridge), qua bus PC s phc v cho tt c cc n v ca bus PCI. Ti a l 10 thit b c th c ni ti bus PCI, trong cu PCI c coi l mt. Chu k bus ca PCI t gn bng tc chu k bus ca i486. N c th hot ng vi rng 32 bits d liu v tc 33MHz (c th t 64 bits vi tc 66 MHz). Mt im mnh ca PCI l d liu c truyn ti theo kiu cm (burst), trong a ch ch truyn i 1 ln, sau n s c hiu ngm bng cch cho cc n v pht hoc thu m ln trong mi xung clock. Do , bus PCI hu nh c lp y bi d liu. Tc truyn ti a trong kiu burst c th ln n 120MBps. 2.4.6 Bus VL ( VESA local bus) Ging nh PCI, bus VL cng phn cch gia h CPU, b nh chnh, v bus m rng chun. Thng qua bus cc b trn board mch chnh, n c th iu khin ti a 3 thit b ngoi vi. Khe cm VL c 116 tip im. Bus VL chy vi xung clock bn ngoi CPU, nh vy trong cc my DX2 th
tn s ny ch bng mt na clock CPU. V mt logic, mi mt thit b c th mt trong hai v tr: LMB (Local bus master) hoc LBT (Local bus target). B phn iu khin bus cc b LBC (local bus controller) trn main board s quyt nh thit b no s tr thnh LMB , tc l c nm quyn iu khin bus v cho php nhng quyn cho thit b c quyn u tin cao hn. Thng c 3 cp u tin c sp xp theo th t gim dn nh sau: DMA/lm ti, CPU/n v lm ch bus (bus master) v cc n v lm ch bus khc. Thit b no v tr LBT th khng c kh nng lm cc vic lin quan n chuyn ti d liu. Bus VL ch lm vic vi 32 bits, trong tng lai s c m rng n 64 bits.
CHNG 3: B NH
3.1. Cc c trng ca b nh.

Memory: Memory n gin l mt thit b nh n c th ghi v cha thng tin. ROM, RAM, Cache, Hard disk, Floppy disk, CD.... u c th gi l memory c (v n vn lu thng tin). D l loi memory no ta cng c cc thng s sau y: 3.1.1. TN GI Khi nim RAM (Random Access Memory) l b nh truy xut ngu nhin, mt d liu trong RAM khi mt in. DRAM hay SDRAM l khi nim m rng hn (Synchronous Dynamic Random Access Memory - RAM ng b). SDRAM l tn gi chung ca mt dng b nh my tnh, n c phn ra SDR (Single Data Rate) v DDR (Double Data Rate). Do nu gi mt cch chnh xc, chng ta s c hai loi RAM chnh l SDR SDRAM v DDR SDRAM. Cu trc ca hai loi RAM ny tng i ging nhau, nhng DDR c kh nng truyn d liu c hai im ln v xung ca tn hiu nn tc nhanh gp i. 3.1.2. TC (SPEED) y c l l khi nim c ngi dng quan tm nht, tuy nhin c ngi thc mc v cch gi tn, i vi DDR th c hai cch gi theo tc MHz hoc theo bng thng. V d, khi ni DDR333 tc l thanh RAM mc nh hot ng tc 333MHz nhng cch gi PC2700 th li ni v bng thng RAM, tc l khi chy tc 333MHz th n s t bng thng l 2700MB/s (trn l thuyt). 3.1.3. TR (LATENCY) L khong thi gian t khi ra lnh n khi nhn c s phn hi. CAS l vit tt ca 'Column Address Strobe' (a ch ct). RAS (Row Adress Strobe) l a ch hng. khi chipset s truy cp vo hng ngang (ROW) ca ma trn b nh thng qua vic a a ch vo chn nh (chn RAM) ri kch hot tn hiu RAS. Chng ta s phi ch khong vi xung nhp h thng (RAS to CAS Delay) trc khi a ch ct c t vo chn nh v tn hiu CAS pht ra. Sau khi tn hiu CAS pht i, chng ta tip tc phi ch mt khong thi gian na (y chnh l CAS Latency) th d liu s c tm thy. 3.1.4. TN S LM TI Module DRAM c to nn bi nhiu t bo in t, mi t bo ny phi
c np li in hng nghn ln mi giy v nu khng d liu cha trong chng s b mt. Mt s loi DRAM c kh nng t lm ti d liu c lp vi b x l thng c s dng trong nhng thit b di ng tit kim in nng. 3.1.5. SDRAM ACCESS TIME Vic cho ra i cch c d liu theo tng chui (Burst Mode) gip khc phc nhiu nhc im v tng hiu nng cho RAM, chu k ca chui ngn hn rt nhiu chu k trang ca RAM loi c. Chu k ca chui cng c coi nh l chu k xung nhp ca SDRAM v chnh v th n c coi nh thang xc nh cho tc ca RAM bi l khong thi gian cn thit gia cc ln truy xut d liu theo chui ca RAM. Nhng con s -12, -10, -8... ghi trn cc chip RAM cho bit khong thi gian ti thiu gia mi ln truy xut d liu: nhn 12 xc nh chu k truy cp d liu ca RAM l 12ns (nano-giy). 3.1.6 Cc loi b nh + ROM (Read Only Memory) C c tnh l thng tin lu tr trong ROM khng th xo c v khng sa c, thng tin s c lu tr mi mi. Nhng ngc li ROM c bt li l mt khi ci t thng tin vo ri th ROM s khng cn tnh a dng + PROM (Programmable ROM) Mc d ROM nguyn thy l khng xo/ghi c, nhng do s tin b trong khoa hc, Thng tin c th c "ci" vo chip v n s lu li mi trong chip. Mt c im ln nht ca loi PROM l thng tin ch ci t mt ln m thi. + EPROM (Erasable Programmable ROM) Mt dng cao hn PROM l EPROM, tc l ROM nhng chng ta c th xo v vit li c. Dng "CD-Erasable" l mt in hnh. EPROM khc PROM ch l thng tin c th c vit v xo nhiu ln theo ngi x dng, v phng php xo l hardware (dng tia cc tm xo) cho nn kh l tn km v khng phi ai cng trang b c. + EEPROM (Electronic Erasable Programmable ROM) y l mt dng cao hn EPROM, t im khc bit duy nht so vi EPROM l c th ghi v xo thng tin li nhiu ln bng software thay v hardware. ng dng ca EEPROM c th nht l "flash BIOS". BIOS vn l ROM v flash BIOS tc l ti ci t thng tin (upgrade) cho BIOS. +RAM (Random Access Memory) thng tin c th c truy cp khng cn theo th t. + SRAM (Static RAM) v DRAM (Dynamic RAM) SRAM l loi RAM lu gi data m khng cn cp nht thng xuyn (static).
Trn thc t, ch to SRAM tn km hn hn DRAM v SRAM thng c kch c ln hn DRAM, nhng tc nhanh hn DRAM v khng phi tn thi gian refresh nhiu ln. + BDEO-DRAM (Burst Extended Data Out DRAM) L th h sau ca EDO DRAM, dng k thut "pineline technology" rt ngn thi gian d a ch ca data. Nu cc ta nhng mu RAM ti gii thiu trn theo trnh t k thut th thy l hu ht cc nh ch to tm cch nng cao tc truy cp thng tin ca RAM bng cch ci tin cch d a ch hot cch ch to hardware. + SDRAM (Synchronous DRAM) y l mt loi RAM c nguyn l ch to khc hn vi cc loi RAM trc. Nh tn gi ca n l "synchronous" DRAM, synchronous c ngha l ng b, tc xung ng h ca RAM ng b vi d liu. + DDR SDRAM (Double Data Rate SDRAM) y l loi memory ci tin t SDRAM. N nhn i tc truy cp ca SDRAM bng cch dng c hai qu trnh ng b khi clock chuyn t 0 sang 1 v t 1 sang 0. Ngay khi clock ca memory chuyn t 0 sang 1 hoc t 1 sang 0 th thng tin trong memory c truy cp. + DRDRAM (Direct Rambus DRAM) y li l mt bc ngoc mi trong lnh vc ch to memory, h thng Rambus (cng l tn ca mt hng ch to n) c nguyn l v cu trc ch to hon ton khc loi SDRAM truyn thng. Memory s c vn hnh bi mt h thng ph gi l Direct Rambus Channel c rng 16 bit v mt clock 400MHz iu khin. (c th ln 800MHz) + SLDRAM (Synchronous-Link DRAM) L th h sau ca DRDRAM, thay v dng Direct Rambus Channel vi chiu rng 16bit v tc 400MHz, SLDRAM dng bus 64bit chy vi tc 200MHz. Theo l thuyt th h thng mi c th t c tc 400Mhz x 64 bits = 400Mhz x 8 bytes = 3.2Gb/giy, tc l gp i DRDRAM. iu thun tin l l SLDRAM c pht trin bi mt nhm 20 cng ty hng u v vi tnh cho nn n rt da dng v ph hp nhiu h thng khc nhau. + PC66, PC100, PC133, PC1600, PC2100, PC2400.... PC xxx *2*8 = bng thng . Chiu rng ca DDR SDRAM: PC200 * 8 = PC1600. Tng t PC133 s l PC133 * 2 * 8bytes = PC2100 v PC150 s l PC150 * 2 * 8 = PC2400. + Cache memory L loi memory c dung lng rt nh v chy rt nhanh (gn nh tc ca CPU). Thng thng th Cache memory nm gn CPU v c nhim v cung cp nhng data thng (ang) dng cho CPU. S hnh thnh ca Cache l mt cch nng cao hiu qu truy cp thng tin ca my tnh m thi. Nhng thng
tin ta thng dng (hoc ang dng) thng c cha trong Cache, mi khi x l hay thay i thng tin, CPU s d trong Cache memory trc xem c tn ti hay khng, nu c n s ly ra dng li cn khng th s tm tip vo RAM hoc cc b phn khc. L do Cache memory nh l v n rt t tin v ch to rt kh khn bi n gn nh l CPU (v cu thnh v tc ). Thng thng Cache memory nm gn CPU, trong nhiu trng hp Cache memory nm trong con CPU lun. Ngi ta gi Cache Level 1 (L1), Cache level 2 (L2)...l do v tr ca n gn hay xa CPU. Cache L1 gn CPU nht, sau l Cache L2... + Interleave L mt k thut lm tng tc truy cp thng tin bng gim bt thi gian nhn ri ca CPU. V d, CPU cn c thng tin thng t hai ni A v B khc nhau, v CPU chy qu l cho nn A cha kp ly ra CPU phi ch ri! A thy CPU ch th phin qu mi bo CPU sang B i lun sau tr li A ly cng cha mun! Bi th CPU c th rt bt thi gian m ly c c A v B. Ton b ngha interleave l vy. + Bursting Cng l mt k thut khc gim thi gian truyn ti thng tin trong my tnh. Thay v CPU ly thng tin tng byte mt, bursting s gip CPU ly thng tin mi ln l mt block. 3.1.7. Cch Tnh Dung Lng Ca Memory (RAM) Thng thng RAM c hai ch s, v d, 32Mx4. Thng s u biu th s hng (chiu su) ca RAM trong n v Mega Bit, thng s th nh biu th s ct (chiu ngang) ca RAM. 32x4 = 32MegaBit x 4 ct = 128 Mega Bit = 128/8 Mega Bytes = 16MB. - S Pin ca RAM Khi chn RAM, ngoi vic ch tc , sc cha, ta phi coi s Pin ca n. Thng thng sPin ca RAM l (tu vo loi RAM): 30, 72, 144, 160, 168, 184 pins. - SIMM (Single In-Line Memory Module)y l loi ra i sm v c hai loi hoc l 30 pins hoc l 72 pins. Ngi ta hay gi r l 30-pin SIMM hoc 72-pin SIMM. Loi RAM (c cu hnh SIMM) ny thng ti thng tin mi ln 8bits, sau pht trin ln 32bits. Ta cng khng cn quan tm lm n cch vn hnh ca n, nu ra ngoi th trng ta ch cn nhn dng SIMM khi n c 30 hoc 72 pins. Loi 72-pin SIMM c chiu rng 41/2" trong khi loi 30-pin SIMM c chiu rng 31/2" (xem hnh)
- DIMM (Dual In-line Memory Modules) Cng gn ging nh loi SIMM m thi nhng c s pins l 72 hoc 168. Mt c im khc phn bit DIMM vi SIMM l ci chn (pins) ca SIMM dnh li vi nhau to thnh mt mng tip xc vi memory slot trong khi DIMM c cc chn hon ton cch ri c lp vi nhau. Mt c im ph na l DIMM c ci t thng ng (n ming RAM thng ng vo memory slot) trong khi SIMM th n vo nghing khong 45 . Thng thng loi 30 pins ti data 16bits, loi 72 pins ti data 32bits, loi 144 (cho notebook) hay 168 pins ti data 64bits. - SO DIMM (Small Outline DIMM) y l loi memory dng cho notebook, c hai loi pin l 72 hoc 144. Nu ta mt t th thy chng c kh hnh nh ph hp cho notebook. Loi 72pins vn hnh vi 32bits, loi 144pins vn hnh vi 64bits. - RIMM (Rambus In-line Memory Modules) v SO RIMM (RIMM dng cho notebook) L technology ca hng Rambus, c 184 pins (RIMM) v 160 pins (SO RIMM) v truyn data mi ln 16bit (th h c ch c 8bits m thi) cho nn chy nhanh hn cc loi c. Tuy nhin do chy vi tc cao, RIMM memory t nhit rt cao thnh ra li ch to n cng phi khc so vi cc loi RAM truyn thng. 3.1.8 in th lm vic C mt ch s v in th cung cp cho RAM (DRAM Voltage). Thng th DDR s dng mc in th 2,5v v DDR-II l 1,8v. Mt s loi RAM DDR tc cao c th yu cu ti 2,8v hoc 2,85v, i vi nhng loi ny ta phi tham kho ti liu hng dn i km c c thng tin. Tuy nhin cn tun theo mt nguyn tc an ton l: Khng nn ko in th ln qu 2,9v nu khng c gii php tn nhit hu hiu v RAM c th s b chy hoc phng IC sau mt thi gian s dng.
3.2. S phn cp b nh
3.2.1 Xc nh loi b nh Hin c 3 cng ngh b nh ph bin l SDRAM, DDR-SDRAM v RDRAM nn ta cn xc nh loi b nh da theo ti liu hng dn ca bo mch ch. SDRAM: Ph bin trong cc h thng Pentium, Pentium II, v Pentium III,
SDRAM c 3 loi: PC66, PC100 v PC133; tng ng vi tn s lm vic 66MHz, 100MHz v 133 MHz. DDR SDRAM: Ph bin trong h thng Pentium IV hay AMD. Cng ging nh SDRAM, DDR SDRAM cng c nhiu loi tc khc nhau nh PC2100, PC2700, PC3200, PC3500 v PC3700 (xung lm vic tng ng l 266MHz, 333MHz, 400MHz, 433MHz, v 466MHz) RDRAM: L cng ngh b nh tt nht, RDRAM s dng cho cc h thng Xeon v Pentium IV cao cp. 3.2.2 Video Ram (Vram) VRAM c pht trin da trn cng ngh FPM (fast page mode), c hai cng giao tip thay v mt cng nh thng thng: mt cng dnh cho chc nng lm ti mn hnh) cng cn li xut nh ra mn hnh. Nh thit k ny, VRAM hot ng hiu qu hn DRAM trong nhng ng dng video. Tuy nhin, do sn lng tiu th chip video t hn chip nh chnh nn gi cn cao. V th, trong mt s h thng card video t tin, ngi ta c th dng DRAM thng thng gim gi thnh. 3.2.3 Graphic ddr (gddr) GDDR (DDR ha) c pht trin da trn cng ngh DDR SDRAM dnh ring cho ha. Sau phin bn GDDR-2 thit k da trn DDR-II, ATI v NVIDIA kt hp cht ch vi cc nh sn xut b nh a ra phin bn GDDR-3 c in p lm vic thp hn GDDR-2, lm vic t tn s 500MHz n 800MHz vi mc tiu gim in nng tiu th, tng mt chip nh v n gin ha gii php tn nhit. 3.2.4 Window ram (wram) WRAM l mt dng b nh hai cng khc, c dng trong nhng h thng chuyn x l ha. Hi khc VRAM, WRAM c cng hin th nh hn v h tr tnh nng EDO (Extended Data Out). 3.2.5 Synchronous Graphic Ram (SGRAM) SGRAM l loi SDRAM thit k ring cho video vi chc nng c/ghi c bit. SGRAM cho php truy xut v chnh sa d liu theo khi thay v tng n v nn gim bt s lt c/ghi b nh v tng hiu nng ca b iu khin ha. 3.2.6 Base Rambus V Concurrent Rambus Trc khi tr thnh cng ngh b nh chnh, cng ngh Rambus c dng lm b nh video. Cng ngh b nh Rambus dng lm b nh chnh hin ti c gi l Direct Rambus. Cn hai dng Rambus s khai l Base Rambus v Concurrent Rambus c dng cho ng dng video trong my trm v h thng game video nh Nintendo 64
3.2.7 B nh ci tin + Enhanced Sdram (Esdram) tng tc v hiu nng, thanh nh chun c th c tch hp thm b m SRAM (Static RAM) trc tip trn chip. ESDRAM l SDRAM c thm b m SRAM c kh nng lm vic vi tn s 200MHz. Cng tng t nguyn l b nh m ngoi, DRAM cng dng mt b m SRAM lu d liu thng dng, nhm rt ngn thi gian truy xut DRAM. u im ca SRAM trn chip l to lp tuyn bus rng hn gia SRAM v DRAM, tng cng bng thng v tc DRAM mt cch hiu qu. + Fast Cycle Ram (Fcram) FCRAM c Toshiba v Fujitsu ng pht trin nhm phc v my ch, my in cao cp v h thng chuyn mch vin thng. B nh c phn thnh nhiu mng v c thit k hng i nn tng c tc truy xut ngu nhin v gim in nng tiu th. + Synclink Dram (Sldram) Hin ti tuy li thi nhng SLDRAM tng c cng ng ch to DRAM pht trin nhm cnh tranh vi Rambus vo cui thp nin 1990.
+ Virtual Channel Memory (Vcm)
Do NEC pht trin, VCM cho php cc khi b nh khc nhau giao tip c lp vi b iu khin nh v c m ring. Cch ny cho php mi tc v h thng thnh mt khi ring, khng chia s hay dng chung vi cc tc v cng chy khc 3.3. Xy dng b nh t cc chip nh.
3.3.1 Lu tr t tnh
kiu lu tr t tnh dng lu d liu trn mt trc cc a mng. Cc a ny c ch to t aluminum, thy tinh hoc ceramic v c bc bn ngoi vi mt lp vt liu st t, thng l hp kim coban. Lp vt liu st t ny bao ph s cho php u c/ghi c th t ha cc vng nh ca a th hin d liu s trn . C nhiu a mng bn trong mt cng, chng c cch ly vi nhau bi cc ming m trn mt trc n. Trc ny c iu khin bi mt m t c th quay trn cc a. Tc ca m t ny l khng i v l tc
ca cng. Cc u c ghi trn tng mt a c gn vi mt cnh tay chuyn ng ring. Cnh tay chuyn ng ny c iu khin bng mt m t servo c th chuyn u c vo gn hoc ra xa vi trc. C hai cch ghi d liu ln a: theo chiu ngang v chiu vung gc. Chiu ngang l cch truyn thng ghi d liu ln a. Cng ngh ghi vung gc c th cho php cc thit k ng gi c nhiu d liu hn trn cng mt vng ca a m khng phi bun phin v hiu qu ca siu thun t cho cc vng c kch thc ging nhau. N hi kh hiu trong vn ti sao chng ta khng phi lo lng v hiu qu ca siu thun t. V bn cht vn ny l hng ca trng t tnh thay i, v v vy chng tng tc vi cc thnh phn bn cnh ca chng khc nhau. S tng tc ny rt quan trng trong vic xc nh xem siu thun t c nh hng hay khng. Tng t vi cng, cc bit c lu trn mt di bng bng cch o cc mt vng t tnh nh. C hai kiu c bn ca di bng l: tuyn tnh v xon c. Cc bng tuyn tnh c cc rnh tuyn tnh. Trn bng c mt s rnh m rng t bng ny n bng khc. Mi rnh gm c nhiu vng t tnh nh, cc vng ny c th c s dng th hin bt d liu 1 hoc 0. Cc bng xon c c cc rnh c th chy theo ng cho ln xung theo bng. iu c ngha rng cc rnh s chng ln nhau. Bnh thng iu l khng tt, tuy nhin kiu bng ny s dng hai u ghi, mi u ghi li s dng mt trng thi phn cc i nhau, iu cho php u c c th phn bit c cc rnh. Do vy n c th cho dung lng cao hn khi s dng bng. 3.3.2 B nh bn dn Mt trong nhng loi b nh bn dn thng thng l RAM, bn c th xem hnh 3.3.2. C hai loi RAM chung l ng v tnh. Ram tnh (SRAM) lu d liu trong mt b gm c 6 transistor (6 transistor ny to thnh mt khi c bit n l mt flip-flop (FF)). Ram ng (DRAM) lu d liu bng cc t in, cn phi lm ti lin tc, y l l do ti sao DRAM khng lu c d liu khi mt in. u im ca DRAM l ch cn n mt trasistor v mi t in cho mi bit. iu ny lm cho n c dung lng nh cao hn SRAM. Cn u im ca SRAM l cc transistor khng cn n vic lm ti v tng tc nhanh hn cc t in.
Hnh 3.3.2: RAM Mt kiu b nh bn dn khc ang c s dng nhiu hin nay l b nh Flash. Trong loi b nh ny cng c chia thnh hai kiu: NOR v NAND. NOR (Not OR) thng s dng cc cng logic NOR trong khi NAND (Not AND) li s dng cc cng logic NAND. C hai cng lgic NAND v NOR u c cu to t cc transistor v khng cha t in trong . iu ny ngha l khi mt in d liu c lu bn trong chng s khng b mt. Mc d c NAND v NOR Flash u tng t nhau nhng chng cng c mt s im khc nhau. NAND flash s dng cng ngh truy cp tun t ph hp hn cho vic lu tr d liu. NOR flash l mt cng ngh truy cp ngu nhin, iu ny lm cho n tt hn trong vic lu tr cc chng trnh s dng tn t b nh. NOR flash thng c s dng trong cc ng dng nh chy mt h iu hnh ca in thoi di ng. NAND flash c s dng in hnh trong cc ng dng nh cc th nh USB. 3.3.3 B nh quang Mt kiu lu tr quang hc thng c s dng nht l CD. Cc CD c sn xut t polycarbonat plastic c cc l nh, cc l nh ny c sp xp theo hnh xon c xung quanh a, l cc l dng biu th d liu. Trn polycarbonat ny l mt lp vt liu phn chiu mng, thng l aluminum hay vng v trn l mt lp acrylic bo v a. Khi mt CD ang c, tia laser s p vo lp polycarbonat v c phn chiu vo lp vt liu phn chiu. Tia laser phn chiu quay tr li c pht hin bng mt cm bin quang, dng chuyn i tn hiu tia laser nhn c thnh tn hiu in. Ph thuc vo tia laser tp trung vo cc l hng khc nhau th tn hiu in thu c cng s khc nhau v tia phn chiu khc nhau. S khc nhau trong cc tn hiu in l cch mt my tnh c th c d liu trn a CD nh th no. l trng hp i vi cc CD thng thng, nhng vic ghi d liu ln cc a CD nh th no? Mt CDR cng tng t nh mt CD trong cu trc chung ca n ngoi tr c hai kha cnh chnh. u tin l n khng c cc l.Th hai, gia polycarbonat v aluminum phn chiu c mt lp thuc nhum trong sut.
lu d liu vo CD-R, tia laser dng ghi c tp trung vo phn xon c mun ghi (ng xon c ny khng tn ti cho ti khi bn to n bng vic ghi d liu ln) v nung nng lp thuc nhum. Cc thuc tnh ha hc ca lp thuc nhum thay i tng ng m ca n vi nhit t nng. V vy tia laser dng ghi c th chuyn ng dc theo ng xon c v thay i m ca cc vng nh, s khc bit trong m th hin ra d liu l cc con s 1 v 0. D liu sau c c t CD-R theo cch nh mt CD. CD-R ch c th c ghi mt ln. iu ny l bi v khi lm lp thuc nhum thay i th bn khng th lm cho n trong sut li c ln na. Vy sau CD-R l g? CD-RW s dng lp thuc nhum khc, lc u c mu c, sau khi c t nng c mu trong sut. Thuc nhum ny cng c thuc tnh kh th v l c th tr li trng thi ban u nu c t nng n mt nhit cao hn. iu ny cho php bn d dng xa cc d liu c lu trn a trc .
Hnh 3.3.3. nh ca cc l trn mt a DVD Cc a DVD lm vic cng ging nh a CD. Cc a ny c th lu nhiu d liu hn a CD v v bn cht chng gm nhiu a CD mng c ct tr trn mt DVD. iu c to t mt s lp polycarbonat v vt liu phn chiu. Cc tia laser v cm bin quang cng c nhiu ci tin hn, trong tia laser c kh nng xuyn qua cc lp khc nhau v cm bin quang cng c th pht hin c tt c cc lp khc nhau .
3.3.4. B nh phn t ng c cho vic pht trin cng ngh lu tr mi l chng ta mun nhanh chng vn n c gii hn nh v nhanh trong cc thit b, trong khi ngi dng lun yu cu dung lng v hiu sut tt hn. Chnh v vy cc cng ngh mi cng cn phi c nghin cu v sm a ra hn. Trong phn ny chng ti c gii thiu n cng ngh nh phn t. Vy cng ngh nh phn t l g? iu g lm cho b nh phn t hp dn n vy, cu tr li l cc phn t rt nh v c th cung cp mt mt nh ln hn gp nhiu ln so vi cc cng ngh hin ti. gi mt bit trong mt phn t, theo l thuyt iu ny kh n gin. Ta ch cn thm hoc bt cc electron trong mi phn t . iu kh khn y l vic c v ghi cc bit d liu nh th no. truy cp vo cc phn t c v ghi, mt s nh nghin cu sp xp mt mng phn t xung quanh cc ng nano nh c kh nng tch in. Phng php ny c th hin nh trong hnh 3.3.4. Mt s chuyn gia nghin cu khc li mun gia cng cc bt d liu thng qua sng v tuyn. H thc hin iu bng cch to mt xung in t mt tn s no , xung ny sau c th thay i np cho phn t. c cc bt d liu, mt xung tn s khc s c to ra sau . Kt qu phn t c xung th hai ny c th cho bn bit rng xung u tin tng tc vi phn t, do vy cho php bn lu v sau c bit d liu .
Hnh 3.3.4. S thit b nh phn t Nh nhng g bn c th nhn thy trn l cng ngh b nh phn t, cng ngh ny c th ha hn s cung cp cho ngi dng mt mt nh ln. Tuy nhin, hin nay b nh phn t vn nm trong cc phng th nghim, v vy c l chng ta s phi i n vi nm tip theo c th thy c cng ngh mi ny s mang n nhng thun li trong ng dng cho chng ta nh th no. 3.3.5. B nh thay i pha Khng ging nh b nh phn t, b nh thay i pha hin c a vo
ng dng. Trong thc t, cng ngh b nh thay i pha c a ra cch y khong vi thp k. Vo nm nhng nm 60, Stanford Ovshinsky pht minh ra cch kt tinh cc vt liu v nh hnh, cc vt liu khng c cu trc c th. Cc CD-R v CD-RW lm vic bi tia laser thay i m ca mt vng nh trn mi a. S thay i tnh m ca vt liu t v nh sang kt tinh, v ngc li. y cng l cng ngh c pht minh bi Ovshinsky. Ovshinsky l ngi u tin ch to CD-RW vo nm 1970. S khc nhau gia cng ngh CD-R v cng ngh thay i pha l vi b nh ca cng ngh thay i pha, trng thi kt tinh ca mt vng nh c thay i bng mt dng in ch khng phi tia laser. Khi khng s dng tia laser c v ghi d liu th chng ta s khng lm m vng nhng li xut hin in tr sut vng . Khi vng thay i sang kt tinh hoc v nh hnh th in tr sut ca vng c th o c v da vo s in tr sut ngi ta c th phn bit c l 1 hay 0. By gi ta c th thy c in tr xut kh ging vi tnh m c. Mt vt liu c in tr khng cho php nhiu in tch lu thng qua n v vt liu m khng cho php nhiu nh sng xuyn qua n. Cng nn bit rng cc vt liu m trong thc t c s phn chiu nh sng. Ta c th khng nhn ra rng cc vt liu c in tr cng phn chiu. ng hn, n l tr khng (impedance) ca vt liu s phn chiu in. in tr l mt kha cnh ca nhng g to nn tr khng; cc thnh phn khc l in dung v in cm. Trong nhiu ng dng, vic hn ch s phn chiu bi tr khng ph hp l mt vn ln trong thit k. B nh thay i pha c tim nng thay th c b nh flash trong mt vi nm ti. Vy lm th no c th so snh c vi flash? Ging nh flash, b nh thay i pha l b nh truy cp ngu nhin n nh lm cho n ph hp vi c chy m v lu tr d liu. Nm 2006, IBM cng vi Macronix v Qimonda tuyn b cc kt qu nghin cu rng h thit k, xy dng v minh chng c thit b nh thay i pha u tin. Thit b ny nhanh hn gp 500 ln so vi flash trong khi s dng t hn mt na cng sut tiu th. Thit b u tin ny cng nh gn hn cc b nh flash. 3.3.6. B nh Holographic Nhiu ngi ngh rng cng ngh holographic ch l mang tnh l thuyt, nhng ngy nay n ang dn tr thnh mt cng ngh hin thc. R rng n cha c s dng rng ri v kh t . Tuy nhin tnh trng ny s sm c thay i bi v c rt nhiu u im lu tr d liu ca bn trn b nh cng ngh holographic ny.
Hnh 3.3.6. Thit b nh cng ngh holographic B nh holographic lm vic bng cch chiu hai chng sng dnh lin vo mt mi trng nhy cm vi nh sng, mt chm d liu v mt chm tham chiu. Mu giao thoa kch thc ba chiu c to bi hai chm sng ny c lu nh mt k thut to nh ba chiu. Mu giao thoa ny c th c c bng cch ch chiu sng chm tham chiu vo mu giao thoa; chm thu c s ging vi chm d liu gc. Kiu b nh ba chiu ny ngha l chng ta c th lu v truy cp cc trang b nh cng mt thi im. N cng c ngha l cc thit b nh holographic s c mt kh nng nh vi s lng ln khng tng. Vi cc u im ca n, holographic s sm tr thnh mt cng ngh lu tr c s dng trong th trng lu tr th ba. Mc d vy cc thit b holographic s t ph bin nh cc a CD v DVD ngy nay.
3.3.7 MRAM_ Hiu ng T in Tr Ca Ram B nh truy nhp ngu nhin (RAM) l phn t nh khng th thiu trong cc my tnh hin nay. im km ca b nh RAM hin nay l d liu b xa mt sau khi ngt ngun in v tc truy nhp cn hn ch. B nh RAM t in tr (MRAM) ang c nghin cu mnh m v s l mt thay th hu hiu cho RAM truyn thng. a. S lc v hiu ng t in tr v MRAM B nh MRAM c m u t nm 1984 bi 2 tin s Arthur Pohm v Jim Daughton lc ang lm vic cho Honeywell, a tng v mt loi b nh s dng hiu ng t in tr (Magnetoresistance Effect) cho php to ra cc b nh vi mt lu tr thng tin cao, truy nhp ngu nhin, v khng t xa. Nm 1989, Daughton ri Honeywell v tng ny bt u c pht trin thnh thng phm, ng thi vi s nhy vt ca hiu ng t tr l s pht hin ra hiu ng t in tr khng l (Giant Magnetoresistance - GMR) v t in tr chui hm (Tunelling Magnetoresistance - TMR). Thc cht hiu ng t in tr c nghin cu v s dng trc kh lu, hiu n gin l s thay i in tr sut trong cht rn di s tc dng ca t trng. Trc , ngi ta thng ng dng hiu ng t in tr d hng (Anisotropic Magnetoresistance - AMR) trong cc mng hp kim Permalloy NiFe cho u c b nh v sensor t. nh ngha hiu ng t tr, ngi ta a ra t s t tr: Hiu ng GMR ln u tin c pht hin bi nhm ca Fert nm 1988 trn cc mng a lp siu mng Fe/Cr. Vi cc mng ny, c th cho t s MR ti vi chc % v cn c th ln hn, v c gi l hiu ng t in tr khng l (xem hnh 1). Cc nghin cu sau ny ch ra rng tn gi "khng l" khng xut pht t gi tr ln ca MR m xut pht t c ch to ra hiu ng GMR, l c ch tn x ph thuc spin ca in t qua cc lp st t. Nh ta bit rng, in t c spin, in tr ca mt cht ph thuc vo s tn x ca in t trn: trn nt mng tinh th, trn cc moment t, v trn sai hng. T trng ngoi gy ra s nh hng ca cc moment t v
do lm thay i s tn x ca in t trn cc spin v l cc hiu n gin v hiu ng GMR.
Hnh 1. Hiu ng GMR: ng cong thay i in tr theo t trng ngoai trong cu trc siu mng Fe/Cr. Hiu ng t in tr chui hm (Tunneling Magnetoresistance - TMR) ln u tin c pht hin bi nhm ca J.S. Moodera ca MIT nm 1995 trn mng a lp. Lp cch in ng vai tr l lp cho in t chui hm t cc lp st t sang nhau v tn x trn cc lp st t. C th ni hai pht hin ny l ng gp quan trng cho s nhy vt ca MRAM bin tng ca Pohm v Daughton thnh hin thc v MRAM bt u c nghin cu ch to thnh thng phm quy m ln ti hu ht cc phng th nghim ln trn th gii.
Hnh 2. ng cong MR trong cc mng CoFe/Al2O3/Co - Hiu ng t in tr chui h m a. Cu Trc Ca MRAM - nh c bn ca RAM: Tip xc chui hm t tnh (Magnetic Tunnel Junction MTJ)
Hnh 3. nh ca MRAM v cc bit (0), (1) tng ng vi trng thi in tr thp v cao (J.P. Nozieres, Spintech, CNRS). Trong MRAM, thng tin khng c lu tr bi in tch ca in t nh b nh bn dn m c lu tr bi spin ca in t, m c th l theo s nh hng ca moment t theo 2 chiu. Mt nh c bn ca MRAM c gi l MTJ gm 2 lp t tnh kp gia l mt lp cch in mng (c di nm) nh hnh 3. Moment t ca mt lp ng vai tr lp chun, b gi c nh theo mt chiu, cn moment t ca lp cn li nh l lp lu tr c th o di tc dng ca t trng t song song n phn song song vi lp chun do dn n s thay i v in tr ca cu hnh (do s tn x khc nhau ca in t trong cc trng thi song song v phn song song). Cc bit (0) v (1) c quy c tng ng vi trng thi in tr thp v cao. Trn thc t, cu trc thc ca mt MTJ phc tp hn nhiu, m hnh trn ch l n gin ha. S lu tr thng tin sau khi ngt ngun in c xc lp nh s gi li trng thi ca cc moment t (bn cht c hu ca t tnh). - Th h u tin: o t trng cm ng (Field-Induced Magnetic Switching - FIMS) Mt MRAM hon chnh gm cc dy 2 chiu cc nh ring bit c a ch ring. Trong cu trc ngy nay, mi nh l s kt hp ca mt transitor CMOS vi mt tip xc chui hm t v 3 mc thng (line levels) nh hnh 4.
Hnh 4. Phng php c v ghi MRAM trong cc cy trc ph bin (a): Nguyn tc c, (b) cch ghi trong cu trc FIMS, (c) cch ghi trong cu trc TAS, (d) cch ghi trong cu trc CIS. + Khi c d liu, mt dng xung cng sut thp s i vo qua cng Control v m transistor dn ti a ch nh c chn, in tr ca c xc nh bng cch iu khin dng qua "word line" qua tip xc chui hm t v so snh vi ly mu trong dy (hnh 4a). + D liu c ghi theo nguyn l t tr. Cc "word line" v "bit line" sp xp qua 2 cc ca tip xc chui hm t v c hot ng nh mt dng xung ng b to ra mt t trng ti a ch nh. Cng dng c chn sao cho ch lp nh ca tip xc t c th b o t cn cc lp ly mu vn gi nguyn trng thi. iu ny c th to c l do c tnh ca cc cu trc nano. Cu trc FIMS c s dng rt hiu qu trong th h MRAM u tin. Tuy nhin, n c nhng hn ch khi kch thc nh gim xung di 1 m: + Cng sut ghi s tng ln do trng o t t l nghch vi kch thc ht. + Cc li la chn ch ghi cng tng ln khi phn b trng o t SFD (Switching Field Distribution) c xu hng tng vt ln.
+ S bn vng ca d liu trong thi gian di c nguy c b tc ng do s tng cc tc ng ca kch thch nhit. - Th h s dng ch o t nh nhit (Thermally Assisted Switching TAS) Nh vy, gim kch thc nh xung di 1 m l mt thch thc cho MRAM. Mt k thut ghi khc pht trin bi SPINTECH (CNRS, France) c th loi b iu ny l o t nh nhit (TAS). iu ny thc hin nh c tnh ph thuc nhit ca trng o t trong cc ht nano. Trong ch TAS, cc transistor CMOS s m ch ghi, v s c mt dng xung ngn chy qua ln tip xc t ng thi vi dng xung to ra t trng ghi v sinh ra nhit ti lp ro th chui hm (nh mt in tr) v nhanh trng t nng lp kim loi ca tip xc t. Kt qu l trng o t b gim xung ti lp lu tr v cho php ghi d dng hn Cch ny c nhiu u th hn so vi phng php c: + Li a ch b gim xung do qu trnh la chn ghi lc ny hu nh b iu khin bi nhit . + D dng t b sung, nhng cng sut ghi ton th c th gim gim rt nhiu so vi ch FIMS v hu nh khng ph thuc vo kch thc nh. + Tc ghi c tng ln do kh nng a ch ng thi (song song) vi xc sut li thp. + S bn nhit c th ci tin bng cch thay th cc vt liu c trng o t ln hn ti nhit hot ng. - Th h s dng dng phn cc spin cm ng (Spin Polarized Current Induced Switching - CIS) y l phng php mi c pht hin gn y s dng nguyn tc kiu b nh RAM truyn thng nh cc flash RAM. Bc tranh n gin ca CIS l khi dng chy qua vy liu t, cc spin b phn cc, v d nh s mt cn bng gia spin up v down. Khi dng in i vo cc lp t tnh khc, s mt cn bng spin ny sinh ra cc mmen xon ti cc t a phng v c th gy ra mt s o t. Cch thc ny c rt nhiu u th: + Khng h c li a ch + C th nng gp i mt b nh + Loi tr s nh hng ca hiu ng kch thc nh + Gim cng sut c ghi Tuy nhin, phng php ny mi ang c pht trin gn y. C th ni, MRAM s l mt tin b thay th cho cc b nh RAM truyn thng (SRAM, DRAM) vi cc u im: - Mt cao (tng dung lng) - D liu khng b xa mt - Tc truy xut cao hn
- Cng sut tiu tn gim MRAM chnh l mt sn phm ca cng ngh spintronics, iu khin cc spin ca in t trong cc linh kin mi m nhng thnh tu ca n c pht trin t cc kt qu nghin cu v vt liu t nano (hiu ng t in tr, t tr...). Trong mt tng lai khng xa, b nh MRAM s tr thnh thng phm ph bin thay th cho cc b nh c. Bng di y so snh MRAM vi cc loi RAM truyn thng.
Di y l mt hnh chp MRAM pht trin bi SPINTEC
Hnh 5. nh chp mt MRAM pht trin bi SPINTEC.
CHNG 4: CC PHNG PHP VO-RA D LIU 4.1. Cu trc phn cng ca cc h thng vo-ra d liu 4.1.1. Song song (Parallel) Cc my tnh PC c trang b t nht l 1 cng song song v 1 cng ni tip. Khc vi ghp ni ni tip c nhiu ng dng, ghp ni song song thng ch phc v cho my in. S ghp ni song song nh hnh sau:
Hnh 4.1.1 s kt ni cng song song
C ba thanh ghi c th truyn s liu v iu khin my in cng nh khi ghp ni. a ch c s ca cc thanh ghi cho tt c cng LPT (line printer) t LPT1 n LPT4 c lu tr trong vng s liu BIOS. Thanh ghi s liu c nh v offset 00h, thanh ghi trang thi 01h, v thanh ghi iu khin 02h. Thng thng, a ch c s ca LPT1 l 378h, LPT2 l 278h, do a ch ca thanh ghi trng thi l 379h hoc 279h v a ch thanh ghi iu khin l 37Ah hoc 27Ah. nh dng cc thanh ghi nh sau:a ch thanh ghi iu khin l 37Ah hoc 27Ah. nh dng cc thanh ghi nh sau: Thanh ghi d liu (hai chiu):
Thanh ghi trng thi my in (ch c):
Thanh ghi iu khin my in:
x: khng s dng IRQ: yu cu ngt cng; 1 = cho php; 0 = khng cho php Bn mch ghp ni ch c bus d liu 8 bit do d liu lun i qua my in thnh tng khi 8 bit. Cc chn tn hiu ca u cm 25 chn ca cng song song LPT nh sau:
Thng tc x l d liu ca cc thit b ngoi vi nh my in chm hn PC nhiu nn cc ng ACK, BSY v STR c s dng cho k thut bt tay. Khi u, PC t d liu ln bus sau kch hot ng STR xung mc thp thng tin cho my in bit rng s liu n nh trn bus. Khi my in x l xong d liu, n s tr li tn hiu ACK xung mc thp ghi nhn. PC i cho n khi ng BSY t my in xung thp (my in khng bn) th s a tip d liu ln bus. D liu c th trao i trc tip gia 2 PC qua cc cng song song vi nhau. Mun vy, cc ng iu khin bn ny phi c kt ni vi cc ng trng thi bn kia.
My in c th c truy xut bng chng trnh qua DOS, BIOS hay trc tip qua cc cng. Cc lnh nh copy tn_file << PRN trong DOS cho php in 1 file ra my in. Ngt 17h vi hm 01h khi ng my in, 00h in 1 k t ra my in, 02h tr v trng thi ca my in, c sn trong BIOS. 4.1.2. Cng Ni tip (Serial port) a. Truyn ni tip ng b v bt ng b Ghp ni tip cho php trao i gia cc thit b tng bit mt. D liu thng c gi theo cc nhm bit SDU (serial data unit) m mi nhm to thnh 1 byte hay 1 word. Cc thit b ngai vi nh: my v, modem, chut c th c ni vi PC qua cng ni tip COM. S khc nhau gia truyn ni tip ng b v bt ng b l: trong k thut truyn ng b, ngoi ng dy d liu phi a thm vo mt hoc vi ng tn hiu ng b cho bit rng khi no bit tip theo n nh trn ng truyn. Ngc li
trong truyn bt ng b, cc bit d liu t n cha cc thng tin ng b; phn pht v phnthu phi hat ng vi cng 1 tn s xung clock. Thng tin ng b (trong truyn bt ng b) gm c cc bit start (cho bit bt u ca khi d liu c truyn) v mt bit stop (cho bit kt thc khi d liu). b. Kim tra chn l v tc truyn Bit chn l (parity bit) c a vo khung SDU dng pht hin li trn ng truyn. Vic truyn bit chn l ch kim sot c cc li trn ng truyn ngn v cc li bit n nn trong mt s ng dng c bit ngi ta phi dng m CRC mc d phc tp hn. Tuy nhin, gn nh tt c cc chip h tr cho ghp ni ni tip ngy nay u c thit k phn cng kim tra chn l. Mt thng s khc lin quan ti truyn d liu ni tip l tc truyn d liu c gi l tc baud. Trong vic truyn m nh phn, l s bit c truyn trong mt giy (bps - bit per second). c. Nhm d liu ni tip SDU v ni tip ha Trc khi truyn chui s liu ni tip, my pht v my thu phi c khi to hat ng vi cng mt nh dng d liu, cng mt tc truyn. Mt SDU vi 1 bit start, 7 bits s liu, 1 bit chn l v 1 bit stop m t nh hnh v. Lu rng: bit start lun bng 0 (space) v bit stop lun bng 1 (mark).
Bus interface: ghp ni bus; Serial data: d liu ni tip; Transmitter holder register: thanh ghi m gi d liu pht; Transmitter shift register: thanh ghi dch d liu pht;
Receiver buffer register: thanh ghi m d liu thu; Receiver shift register: thanh ghi dch d liu thu; SDU logic: mch logic SDU; Interface control baud generator: my pht iu khin tc truyn d liu baud; Clock: xung clock; 4.1.3 Chun ghp ni RS-232 Cc ghp ni ca PC cho trao i ni tip u theo tiu chun RS-232 ca EIA (Electronic Industries Association) hoc ca CCITT Chu u. Chun ny quy nh ghp ni v c kh, in, v logic gia mt thit b u cui s liu DTE (Data Terminal Equipment) v thit b thng tin s liu DCE (Data Communication Equipment). Th d, DTE l PC v DCE l MODEM. C 25 ng vi u cm 25 chn D25 gia DTE v DCE. Hu ht vic truyn s liu l bt ng b. C 11 tn hiu trong chun RS232C dng cho PC, IBM cn quy nh thm u cm 9 chn D9. Cc chn tn hiu v mi quan h gia cc u cm 25 chn v 9 chn:
Chun RS-232C cho php truyn tn hiu vi tc n 20.000 bps nhng nu cp truyn ngn c th ln n 115.200 bps. Chiu di cp cc i l 17-20m. Cc phng thc ni gia DTE v DCE: - n cng (simplex connection): d liu ch c truyn theo 1 hng. - Bn song cng ( half-duplex): d liu truyn theo 2 hng, nhng mi thi i m ch c truyn theo 1 hng. - Song cng (full-duplex): s liu c truyn ng thi theo 2 hng. 4.2. Cc phng php vo-ra d liu 4.2.1. Truy xut cng ni tip dng DOS v BIOS
Lnh ngai tr MODE ca DOS c th t cc thng s cho cng ni tip RS232. Th d: MODE COM2:2400, E,8 ,1 chn cng COM2, tc 2400 baud, parity chn, 8 bit d liu v 1 bit stop. Cng c th dng ngt 21h ca DOS pht hoc thu d liu qua cng ni tip bng 4 hm sau: - Hm 03h: c 1 k t - Hm 04h: pht 1 k t - Hm 3Fh: c 1 file - Hm 40h: ghi 1 file BIOS cho php truy xut khi ghp ni ni tip qua ngt 14h. - Hm 00h: khi ng khi ghp ni, nh dng d liu, tc truyn,. - Hm 01h, 02h: pht v thu 1 k t - Hm 03h: trng thi ca cng ni tip - Hm 04h,05h: m rng cc iu kin khi ng khi ghp ni, cho php truy xut cc thanh ghi iu khin MODEM.
D7: li qu thi gian (time-out); 1 = c li; 0 = khng li; D6: thanh ghi dch pht; 1 = rng ; 0 = khng rng D5: thanh ghi m pht; 1 = rng; 0 = khng rng D4: ngt ng truyn; 1= c ; 0 = khng D3: li khung truyn SDU; 1 = c ; 0 = khng D2: li chn l; 1 = c ; 0 = khng D1: li trn; 1 = c ; 0 = khng D0: s liu thu; 1 = c ; 0 = khng
D7: pht hin sng mang; 1= pht hin, 0 = khng D6: ch bo tn hiu chung; 1= c ; 0= khng D5: tn hiu DTR; 1 = c , 0 = khng D4: tn hiu CTS; 1 = c , 0 = khng D3: tn hiu DDC, 1 = c , 0 = khng D2: tn hiu delta RI; 1 = c, 0 = khng D1: tn hiu delta DTR; 1 = c , 0 = khng D0: tn hiu delta CTS; 1 = c , 0 = khng Thanh ghi DX cha gi tr tng ng vi cc cng cn truy xut (00h cho COM1,
01h cho COM2, 10h cho COM3, 11h cho COM4). Cc thng s nh dng khung truyn SDU c np vo thanh ghi AL theo ni dung nh sau: D7, D6, D5: tc baud 000 = 110 baud 001 = 150 baud 010 = 300 baud 011 = 600 baud 100 =1200 baud 101 = 2400 baud 110 = 4800 baud 111 = 9600 baud D4-D3: bit parity 00= khng c 01= l 10 = khng c 11= chn D2: s bit stop 0 = 1 bit 1 = 2 bits D1-D0: s bit s liu 10 = 7 bits 11= 8 bits 4.4.2. Giao tip PC Game Cu trc v chc nng ca board ghp ni tr chi (PC game) nh hnh bn di. Bng lnh IN v OUT c th truy xut qua a ch 201h.
Board mch c ni vi bus h thng ca PC ch qua 8 bits thp ca bus d liu, 10 bits thp ca bus a ch v cc ng iu khin IOR v IOW. Mt u ni 15 chn c ni vi board mch cho php ni cc i hai thit b cho PC game gi l joystick. Mi joystick c 2 bin tr c gi tr bin i t 0 n 100k c t vung gc vi nhau i din cho v tr x v y ca joystick. Thm na chng c 2 phm bm, thng l cc cng tc thng h ph hp vi cc mc logic cao ca cc dy trn mch. C th xc nh c trng thi nhn hoc nh phm mt cch d dng bng lnh IN ti a ch 201h. Nibble cao ch th trng thi ca phm. V board khng dng ng IRQ do khng c kh nng pht ra 1 ngt, do vy board ch hot ng trong ch hi vng (polling). Byte trng thi ca board game nh sau:
BB2, BB1, BA2, BA1: Trng thi ca cc phm B2, B1, A2, A1; 1 = nh; 0 = nhn BY, BX, AY, AX: Trng thi ca mch a hi tu thuc vo bin tr tng ng.
4.4.3. Giao tip vi bn phm

4.4.3.1. Bn phm _ Cu trc v chc nng:
Chip x l bn phm lin tc kim tra trng thi ca ma trn qut (scan matrix) xc nh cng tc ti cc ta X,Y ang c ng hay m v ghi mt m tng ng vo b m bn trong bn phm. Sau m ny s c truyn ni tip ti mch ghp ni bn phm trong PC. Cu trc ca SDU cho vic truyn s liu ny v cc chn cm ca u ni bn phm.
STRT: bit start (lun bng 0) DB0 - DB7: bit s liu t 0 n 7. PAR: bit parity (lun l) STOP: bit stop (lun bng 1). Tn hiu xung nhp dng cho vic trao i d liu thng tin ni tip ng b vi mch ghp ni bn phm (keyboard interface) trn main board c truyn qua chn s 1. Mt b iu khin bn phm c lp t trn c s cc chp 8042, hoc 8742,8741. N c th c chng trnh ha (th d kha bn phm) hn na s liu c
th truyn theo 2 hng t bn phm v mch ghp ni, do vy vi m ca chp bn phm c th gip cho vic nhn lnh iu khin t PC, th d nh t tc lp li ca nhn bn phm,. 4.4.3.2. M qut bn phm: Mi phm nhn s c gn cho 1 m qut (scan code) gm 1 byte. Nu 1 phm c nhn th bn phm pht ra 1 m make code tng ng vi m qut truyn ti mch ghp ni bn phm ca PC. Ngt cng INT 09h c pht ra qua IRQ1.Chng trnh x l ngt s x l m ny tu theo phm SHIFT c c nhn hay khng. V d: nhn phm SHIFT trc, khng ri tay v sau nhn C:make code c truyn - 42(SHIFT) - 46 (C). Nu ri tay nhn phm SHIFT th bn phm s pht ra break code v m ny c truyn nh make code. M ny ging nh m qut nhng bit 7 c t ln 1, do vy n tng ng vi make code cng vi 128. Tu theo break code, chng trnh con x l ngt s xc nh trng thi nhn hay ri ca cc phm. Th d, phm SHIFT v C c ri theo th t ngc li vi th d trn: break code c truyn 174 ( bng 46 cng 128 tng ng vi C) v 170 (bng 42 cng 128 tng ng vi SHIFT). Phn cng v phn mm x l bn phm cn gii quyt cc vn vt l sau: - Nhn v nh phm nhng khng c pht hin. - Kh nhiu rung c kh v phn bit 1 phm c nhn nhiu ln hay c nhn ch 1 ln nhng c gi trong mt khong thi gian di. 4.4.3.3. Truy xut bn phm qua BIOS BIOS ghi cc k t do vic nhn cc phm vo b m tm thi c gi l b m bn phm (keyboard buffer), c a ch 40:1E, gm 32 byte v do vy kt thc a ch 40:3D. Mi k t c lu tr bng 2 bytes, byte cao l m qut, v byte thp l m ASCII. Nh vy, b m c th lu tr tm thi 16 k t. Chng trnh x l ngt s xc nh m ASCII t m qut bng bng bin i v ghi c 2 m vo b m bn phm. B m bn phm c t chc nh b m vng (ring buffer) v c qun l bi 2 con tr.Cc gi tr con tr c lu tr trong vng s liu ca BIOS a ch 40:1A v 40:1C. Ngt INT 16h trong BIOS cung cp 8 hm cho bn phm. Thng cc hm BIOS tr v mt gi tr 0 ca ASCII nu phm iu khin hoc chc nng c nhn.. Cc th d: - Gi s phm a c nhn. MOV AH,00h ; chy hm 00h, c k t INT 16h ; pht mt interrupt Kt qu: AH = 30 (m qut cho phm a); AL = 97 (ASSCII cho a) - Gi s phm .HOME c nhn.
MOV AH,00h ; chy hm 00h, c k t INT 16h ; pht mt interrupt Kt qu: AH = 71 ( m qut cho phm HOME) AL = 00 (cc phm chc nng v iu khin khng c m ASCII) - Gi s phm HOME c nhn. MOV AH,10h ; chy hm 10h, c k t INT 16h ; pht mt interrupt Kt qu: AH = 71 (m qut cho phm HOME) AL = E0h 4.4.3.4. Chng trnh vi bn phm qua cc cng: Bn phm cng l mt thit b ngoi vi nn v nguyn tc c th truy xut n qua cc cng vo ra. Cc thanh ghi v cc port: S dng 2 a ch port 60h v 64h c th truy xut b m vo, b m ra v thanh ghi iu khin ca bn phm.
Thanh ghi trng thi xc nh trng thi hin ti ca b iu khin bn phm. Thanh ghi ny ch c (read only). C th c n bng lnh IN ti port 64h.
PARE: Li chn l ca byte cui cng c vo t bn phm; 1 = c li chn l, 0 = khng c. TIM: Li qu thi gian (time-out); 1 = c li, 0 = khng c. AUXB: m ra cho thit b ph (ch c my PS/2); 1 = gi s liu cho thit b, 0 = gi s liu cho bn phm. KEYL: Trng thi kha bn phm; 1 = khng kha, 0 = kha. C/D: Lnh/s liu; 1 = Ghi qua port 64h, 0 = Ghi qua port 60h. INPB: Trng thi m vo; 1 = s liu CPU trong b m vo, 0 = m vo rng. OUTB: Trng thi m ra; 1 = s liu b iu khin bn phm trong b m ra, 0 = m ra rng.
Thanh ghi iu khin (64h)
Cc lnh cho b iu khin bn phm: M Lnh A7h Cm thit b ph, A8h Cho php thit b ph, A9h Kim tra ghp ni ti thit b ph AAh T kim tra, ABh Kim tra ghp ni bn phm, ADh Cm bn phm, AEh Cho php bn phm C0h c cng vo C1h c cng vo ra (byte thp) C2h c cng vo ra (byte cao) D0h c cng ra D1h Ghi cng ra D2h Ghi m ra bn phm D3h Ghi m ra thit b ph D4h Ghi thit b ph E0h Kim tra c cng vo
F0h Gi 1 xung ti li ra FFh Cng Kha bn phm: Start: IN AL, 64h ; c byte trng thi TEST AL, 02h ; kim tra b m c y hay khng JNZ start ; mt vi byte vn cn trong b m vo OUT 64h, 0ADh ; kha bn phm Cc lnh cho bn phm: Tm tt cc lnh bn phm:
Th d: lnh bt n led cho phm NUMCLOCK, tt tt c cc n khc. OUT 60H, EDH ; ra lnh cho bt tt cc n led WAIT: IN AL, 64H ; c thanh ghi trng thi JNZ WAIT ; b m vo y OUT 60H, 02H ; bt n cho numclock Cu trc ca byte ch th nh sau:
4.4.4 AGP - Accelerated Graphics Port 4.4.4.1 Nguyn l chung Cc hnh nh m chng ta thy c trn mn hnh my tnh c to bi rt
nhiu im nh gi l pixel. Trong hu ht cc thit lp cho phn gii th mn hnh thng hin th khong hn 1 triu im nh. My tnh s quyt nh cn phi lm g theo th t i vi tng im nh to ra mt hnh nh. c th lm c vic ny, n s dng mt b chuyn i, ly cc d liu nh phn t CPU v chuyn chng thnh hnh nh hin th trn mn hnh.Khi CPU nhn c yu cu xem mt hnh nh t pha ngi s dng, n s chuyn yu cu ny ti card ha quyt nh s dng nhng pixel no hin th hnh nh. Sau n s gi nhng thng tin mn hnh hin th thng qua dy cp. Qu trnh to ra nhng hnh nh khng phi l d liu nh phn thng i hi qu trnh x l phc tp hn rt nhiu. c th v ra mt hnh nh 3D, card ha phi to ra mt khung in t, sau qut hnh nh v thm vo nh sng, mu. i vi tr chi c nhiu hnh nh 3D, my tnh phi lp li qu trnh ny khong 60 ln mi giy. Nh cc thnh phn khc ca my tnh, Graphic Card AGP c u tin kt ni vi CPU qua Bus. V c bn, Bus c hiu nh knh truyn hay ng ni gia cc thnh phn trong my tnh. Do AGP c xy dng da trn cc chun PCI Bus v c coi nh mt AGP Bus nn n l mt dng kt ni im (Point to Point ). Ni cch khc ch c mt thit b kt ni gia AGP vi CPU v b nh, l Graphic Card v do vy n thc s n khng phi l mt Bus. AGP c hai ci tin so vi PCI l tc nhanh hn v truy xut trc tip ti b nh h thng. AGP s dng cc cng ngh sau t c tc nhanh hn:
AGP l mt Bus 32 bit vi xung nhp 66 MHz. iu c ngha l trong mt giy n c th truyn ti mt lng thng tin c ln 32 Bit (4 Byte) n 66 triu ln. Tc truyn ti s tng ln khi n hot ng ch 2X v 4X. Khng c thit b no khc trn my tnh s dng AGP Bus, do vy Graphic Card s khng phi chia s Bus vi cc thit b khc v lun hot ng vi kh nng kt ni ti a. AGP s dng Pipelining tng tc. Pipelining t chc vic thu hi d liu theo trnh t v Graphic Card nhn c cc on d liu hon tr li cc yu cu n l.
AGP s dng Sideband Addressing cho php Graphic Card a ra cc yu cu v phn b cc thng tin a ch s dng 8 Bit trong s 32 Bit dng truyn d liu.
Bn cnh ci tin v tc , mt ci tin na ca AGP-based Graphic Card so vi PCI l kh nng truy xut trc tip ti b nh h thng qua AGP Bus vi tc ti a. y l mt thnh phn rt quan trng ca AGP. Bng lu kt cu (Texture Map) l cha kho quan trng trong ho my tnh, n chim mt lng tng i ln b nh cc Graphic Card thng thng. Do Video RAM thng i hi tng i ln trong khi li b hn ch bi dung lng Graphic Card nn s lng v ln ca Texture Map cng b gii hn gn bng dung lng Graphic Card. H thng AGP-based thun li hn ch c th s dng b nh h thng lu tr cc Texture Map v cc d liu khc m vn thng phi lu Video RAM trn Card.
Trong cc h thng khng h tr AGP chng hn nh PCI-based Graphic Card, mi Texture Map u c lu hai ln. Ln th nht n c np t a cng ln b nh h thng. Sau n c c t b nh h thng ra CPU x l ri c gi tr li qua PCI Bus v lu trn Framebuffer ca Graphic Card. Kt qu l mi Texture Map u c x l v lu hai ln, mt ln bi h thng v mt ln bi Graphic Card. AGP ch lu cc Texture Map mt ln vi Chip GART (Graphic Address Remapping Table). GART s phn b cc phn b nh h thng lu gi cc Texture Map nhng lun lm CPU v Graphic Card lm tng rng cc Texture Map c lu trn Framebufer ca Card. GART c th lu kim sot cc Bit ca Texture Map cho d
chng c lu nhng vng khc nhau trn b nh h thng nhng li c th hin nh mt on b nh lin tc trn Graphic Card. Trong trng hp s dng non-AGP Card, mi Texture Map u b lu thnh hai ln dn n CPU phi lm vic nhiu hn. y chnh l nhng hn ch ca nonAGP Card so vi cc AGP-based Card. AGP ch lu cc Texture Map mt ln vi Chip GART (Graphic Address Remapping Table). GART s phn b cc phn b nh h thng lu gi cc Texture Map nhng lun lm CPU v Graphic Card lm tng rng cc Texture Map c lu trn Framebufer
ca Card. GART c th lu kim sot cc Bit ca Texture Map cho d chng c lu nhng vng khc nhau trn b nh h thng nhng li c th hin nh mt on b nh lin tc trn Graphic Card. Trong trng hp s dng non-AGP Card, mi Texture Map u b lu thnh hai ln dn n CPU phi lm vic nhiu hn. y chnh l nhng hn ch ca nonAGP Card so vi cc AGP-based Card. Hin ti c 3 th h AGP 1.0, AGP 2.0 v AGP Pro. AGP 2.0 c xy dng trn phin bn AGP 1.0 cung cp 3 ch hot ng. Cc ch ny u chy vi tc 66 MHz qua AGP Bus. i vi 2X AGP, Graphic Card gi d liu 2 ln sau mi xung nhp cn ch 4X AGP n s gi d liu 4 ln sau mi xung nhp.
Ch 1x 2x 4x Xung nhp 66 MHz 133 MHz 266 MHz Tc truyn 266 MBps 533 MBps 1,066 MBps
4.4.5. PCI EXPRESS
PCI Express, vit tt l PCIe l mt dng giao din bus h thng/card m rng ca my tnh. N l mt giao din nhanh hn nhiu v c thit k thay th giao din PCI, PCI-X ( PCI Extended ) , v AGP cho cc card m rng v card ha. Khe cm PCI Express (PCIe) hon ton khc so vi cc chun trc nh PCI hay PCI Extended (PCI-X). -Nhng PCI c mt vi hn ch . Nhng CPU , Card mn hnh , Card m thanh v nhng Card mng ngy cng nhanh hn v mnh hn trong khi PCI c nh rng d liu 32-bit v ch c th iu khin 05 thit b trong cng mt lc . -Mt giao thc mi gi l PCI Express (PCIe ) gii quyt c nhng hn ch trn , cung cp bng thng ln hn , tng thch vi nhng h iu hnh ang c . 4.4.5.1. Kt ni ni tip tc cao : Ngay t khi ra i ca my tnh , vic cn thit trao i d liu v cng ln . Trong kt ni ni tip my
tnh tch d liu thnh nhng nhm v chuyn tng gi d liu i mt , ht gi ny ri n gi kia . Kt ni nh th trong thi im ban u ca k nguyn my tnh c tc chm , do nhiu nh sn xut bt u chuyn sang dng kt ni song song gi nhiu mu d liu i cng mt lc . Mt vn xy ra khi nhng kt ni song song t ti tc cao no th nhng dy dn cnh nhau gy nh hng qua li vi nhau, do dng in i qua dy dn to nn mi trng xung quanh n mt t trng . Vi cng t trng mt mc no s nh hng ln dy dn bn cnh lm sai lch tn hiu bn trong mt dy dn khc v ngc li . iu ny xy ra i vi Cable ATA 133. Do vi tn hiu truyn song song ch c th t c mt tc cao nht nh . truyn tn hiu song song vi tc cao khng nh hng ti tn hiu sang nhau i hi thit k li h thng Bus c mc lc nhiu cao lc li nh hng ti gi thnh ca thit b . PCIe l kt ni ni tip m hot ng nh l mng hn l Bus. Thay v mt Bus m iu khin d liu t nhiu ngun. PCIe c Switch iu khin vi kt ni Point-to-Point. Nhng kt ni ny do Switch mang n, hng d liu trc tip ti thit b cn n. Mi thit b c kt ni ring ca n , do nhng thit b khng mt thi gian chia x bng thng nh Bus bnh thng khc . Khi my tnh khi ng ln , PCIe xc nh nhng thit b no c cm bn trong Mainboard . Sau n nhn dng
nhng lin kt gia cc thit b v to mt bn cho bit d liu chuyn ng u s i v phn chia rng ca mi lin kt . S nhn dng ca nhng thit b ny v nhng kt ni l dng cng mt giao thc PCI , do PCIe khng cn thay i phn mm hoc nhng h iu hnh. 4.4.5.2. Vn bng thng : Hin thi, PCI Express c chia lm nhiu loi ng vi tng tc truyn ti d liu khc nhau l: 1x, 2x, 4x, 8x, 12x, 16x (v c 32x), tt c u c bng thng ln hn nhiu so vi chun PCI c. Trong loi 4x, 8x v 12x s dng trong th trng my ch, cn 1x, 2x v 16x th s dng cho ngi dng thng thng. Bng bn cnh so snh cc loi ny vi nhau v vi cc chun truyn ti d liu khc: Lu : v PCI Express l cng ngh da trn nn tng tng t (serial) nn d liu c th truyn ti qua bus theo hai hng, do con s trong bng sau l bng thng tng cng theo c hai hng. -Mi ng ( lane ) ca kt ni PCIe gm hai cp dy, mt truyn d liu v mt gi d liu. Nhng gi d liu di chuyn trong Lane vi tc 1bit/chu k. V kt ni x1 l kt ni nh nht trong kt ni PCIe, nh vy mt Lane c 04 dy dn, mang 1bit/chu k theo mi hng. Kt ni x2 gm 08 dy dn v truyn 2 bit mt lc, kt ni x4 truyn 4 bit v c nh th. Nhng cu hnh khc l x12 , x16 v x32 .
4.4.5.3. Tc nhanh hn
Bus PCI c rng 32-bit , tc xung nhp ng h cao nht l 33MHz , cho php d liu cao nht truyn 133MB/s . Bus PCI-X c rng 64-bit , rng gp i so vi Bus PCI . Nhng tnh nng khc nhau ca PCI-X cho
php tc truyn d liu ln ti t 512MB ti 1GB/s
Mt Lane trong kt ni PCIe c th truyn d liu ln ti 200MB/s cho mi hng . PCIe 16x c th gy kinh ngc khi ln ti 64.GB/s cho mi hng . Vi tc kt ni x1 c th d dng iu khin kt ni Gigabit Ethernet , m thanh v nhng ng dng lu tr . Kt ni x16 c th d dng iu khin sc mnh ca Card mn hnh . Nhng iu kin thun li khi chuyn tc kt ni ni tip :
u tin d liu , iu ny cho php h thng di chuyn hu ht nhng d liu quan trng u tin v ngn chn hin tng kiu nghn mch c chai . D liu c truyn theo thi gian thc . S dng t chn cm hn do rng d liu nh hn Bus thng thng . D dng kt ni v d tm li . n gin hn ngt d liu thnh nhng gi nh v t nhng gi nh cng vi nhau . Mi mt thit b c nhng ng d liu ring do kt ni Point-to-Point t Switch , tn hiu t nhiu ngun khng mt thi gian lm vic trn cng mt Bus .
CHNG 5: CC THIT B NGOI VI

5.1. Cc thit b nhp, xut d liu 5.1.1.Cch hot ng ca mt my in laser: Cc my in laser hot ng bng cch t mc toner (toner: cht mc dng bt c kh nng tch in) trn mt trng quay (drum) c tch in, ri sau chuyn mc toner ln giy in khi t giy ny dch chuyn qua h thng cng mt tc vi trng quay. Hnh 5.1.1 cho ta thy su bc tun t ca tin trnh in trong my in laser. Bn bc u tin s s dng cc thng phn my in vn chu dng s hao mn nhiu nht, tc cc thnh phn c cha bn trong hp tho ra c (cartridge). Vic cha ng cc thnh phn ny bn trong mt hp cartridge s khin my in bn hn. Hai bc sau cng c thc hin bn ngoi hp cartridge. Cc th tc in laser trong hnh 5.1.1 nh sau:
Hnh 5.1.1 Su bc lin tc ca vic in n trn my in laser 1.Lm sch : Mc toner cn st li v in tch s c ly ra khi trng. 2.Chun b : Trng c np mt in tch cao.
3.Ghi : Mt tia laser c s dng gim in tch cao xung mt in tch thp hn, ch nhng ni m mc toner s bm vo. 4.Trin khai : Mc toner c t vo trng ti nhng ni in tch c gim thp xung. 5.Chuyn giao: Mt in tch mnh s ht mc toner t trng ln giy. y l bc u tin din ra bn ngoi hp cartridge. 6.Nung chy: Sc nng v p sut c s dng nung chy mc toner trn giy. Lu rng hnh 5.1.1 ch cho ta thy mt ct ca trng, cc c cu v giy in. Khi hnh dung tin trnh ny, cn nh rng trng quay c chiu rng bng vi chiu rng ca giy in. Gng phn chiu (mirror), thanh gt mc v cc trc ln trong hnh ny cng c chiu rng bng vi chiu rng ca t giy in. Trc ht bn hy v tr ca hp cartrige trong hnh v, trng cm quang quay theo chiu kim ng h nm bn trong cartridge v ng i ca t giy in, vn di chuyn qua hnh v t phi sang tri
Bc 1: Lm sch.
Trc ht cc thang gt (blade) s chi sch mc toner cn st li trn trng. K , cc n xa (erase lamp, c t bn ngoi hp cartridge) s kh in tch cho trng bng cch chiu nh sng ln b mt ca trng trung ha (neutralize) bt k in tch no cn st li trn trng.
Bc lm sch s sch mc toner v kh in tch cn st li trn trng.
Bc 2: Chun b.
Bc chun b s t mt in tch ng nht-600v ln trng. in tch ny c t ln trng bi mt dy dn thit b in hoa chnh (primary corona wire) vn c np in bi mt b ngun cung cp in th cao. (Mt thit b in hoa (corona) l mt thit b c kh nng to in tch). Trong hnh 5.1.1, ta c th thy thit b in ha chnh (primary corona) nm gia dy dn thit b in ha chnh v trng quay, n s iu ha in tch trn trng quay m bo rng in tch ny ng nht mc -600v.
Bc 3: Ghi.
Trong bc ghi, in tch ng nht vn c t trn trng quay trong bc 2 s c gim bt i ch nhng ni cn in. iu ny c thc hin bng cch iu khin cc gng chng phn chiu cc tia laser vo mt trng theo mt mu hnh (pattern) ging ht nh nh cn in. y chnh l bc u tin m cc d liu t my tnh cn phi c truyn ti ti my in. Hnh 5.1.2 cho ta thy tin trnh ny: Cc d liu t my PC c b nh dng (formatter)(1) tip nhn v c chuyn ti b kim sot DC (DC controller)(2), vn l thit b kim sot n v laser (laser unit)(3). Tia laser c khi xng v c dn hng ti mt gng hnh bt gic c gi l gng qut (scanning mirror). Gng qut (4) c quay theo chiu kim ng h bi m m-t qut. Khi gng qut quay, tia laser c diu khin theo mt chuyn ng qut qut sut ton b chiu di ca trng quay. Tia laser c phn chiu ra khi gng qut v c tp trung bi mt thu knh tp trung (,focusing lens) ri c gi ti gng phn chiu. Gng phn chiu s li tia laser i qua mt khe h trong cartridge v chiu vo trng quay.
Bc ghi-c thc hin bi mt tia laser khng thy c,cc gng v cc m-t s gim bt in tch trn trng quay ti nhng ni cn in. Tc ca m-t quay trng v tc ca m-t qut quay gng qut c ng b ha sao cho tia laser hon tt mt ng qut (scanline) dc theo trng ri quay tr li phn u ca trng ny bt u mt ng qut mi, nhm t c qut thch hp cho mi inch ca chu vi trng. V d i vi mt my in 300 dpi (dots per inch: s lng im nh trn mi inch), tia lasre s qut 300 lt cho mi inch ca chu vi trng. Tia laser c bt v tt lin tc khi n thc hin mt qut n theo s chiu di ca trng, cc im (dot) c ghi dc theo trng trn mi lt qut. i vi mt my in 300 dpi, 300 im s c ghi dc theo trng cho mi inch ca chiu di trng. 300 im trn mi inch chiu di, cng vi 300 lt qut cho mi inch ca chu vi trng, hp thnh phn gii 300*300 im trn mi inch vung ca chiu my in laser bn. Ging ht nh vic tia laser qut c ng b ha vi trng quay, kt xut d liu cng c ng b ha vi tia qut ny. Trc khi tia laser bt
u qut dc theo trng, gng pht hin tia (beam detect mirror, xem hnh 5.1.1) s pht hin s hin din ban u ca tia laser bng cch phn x tia ny vo mt si quang (optical fiber). Tia sng ny s i dc theo si quang ti b kim sot DC (DC controller) v ti n s c chuyn i thnh mt tn hiu in c dng ng b ha kt xut d liu. Tn hiu ny c dng chn on cc s c vi tia laser hoc m-t qut. Tia laser ghi mt hnh nh ln b mt trng dng cc vng mang in tch 100v. in tch 100v trn vng hnh nh ny s c s dng trong giai on trin khai chuyn mc toner sang b mt trng.
Bc 4:Trin khai.
Hnh 5.1.3 cho ta thy r hn v bc trin khai,trong mc toner c trc ln trin khai (developing cylinder) p vo cc vng mang in tch 100v trn b mt trng. Mc toner s di chuyn t trc ln sang trng khi c hai quay rt gn nhau. Trc ln c bao ph bi mt lp mc toner, vn c ch to t nha thng en lin kt vi st, tng t nh loi mc toner c s dng trong cc my photocopy. Mc toner c gi trn b mt ca trc ln bi lc hp dn ca chnh n i vi mt nam chm nm bn trong trc ln. Mt thanh gt kim sot (control blade) s ngn cn khng cho mc toner bm vo b mt trc ln. Mc toner ny s nhn mt in tch m (gia 200v v 500v ) v b mt ny c ni ti mt b ngun DC c gi l b th dch DC (DC bias).
Hnh 5.1.3 bc trin khai, mc toner tch in s c t ln b mt ca trng. Mc toner mang in tch m nhiu hn cc vng mang in tch 100v trn b mt trng, nhng t hn cc vng mang in tch 600v trn b mt trng. Do , mc toner b ht vo cc vng 100v trn b mt trng. ng thi, mc toner b y ra khi cc vng in tch 600v ca b mt trng, v chng mang in tch m tng i i vi in tch ca mc toner. Kt qu l mc toner s bm dnh ln trng ti nhng ni m tia laser chiu vo v b y ra khi nhng ni m tia laser cha chiu vo. Hu ht cc my in u cung cp mt cch bn iu chnh mt in (print density). Vi cc my in laser, khi bn iu chnh mt in, bn ang iu
chnh in tch b th hiu dch DC (DC bias) trn trc ln trin khai; in tch ny kim sot mc toner c ht vo trc ln v do , khi in tch ny thay i, mt in cng thay i, mt in cng thay i theo.
Bc 5: Chuyn giao.
Trong bc chuyn giao, thit b in hoa chuyn giao s sinh ra mt in th dng trn t giy in khin mc toner b ht t trng quay sang t giy in khi n qua gia thit ny v trng quay. B kh tnh in(static charge eliminator) s lm yu in tch dng trn t giy in v in tch m trn trng quay t giy ny khng bm cht vo trng quay do s chnh lch in tch. Tnh cht rt ca t giy in v bn knh nh ca trng quay khin t giy ny tch ri khi trng in v i ti trc nung chy (fusing roller). Nu s dng loi giy mng tring mt my in laser,t giy in co th qun trn quanh trng quau v y l l do gii thch ti saocc ti liu hng dn s dng my in laser u ch dn bn s dng ch nhng loi giy c thit k dnh cho my in laser.
Bc 6: Nung chy.
Bc nung chy s lm cho mc toner lin kt vi giy in. Cho ti thi im ny, mc toner ch n thun nm trn giy in. Cc trc ln nung chy (fusing roller) s p dng va p sut ln nhit trn t giy ny. Mc toner s lan chy v cc trc ln s p mc toner vo t giy in. Nhit ca cc trc ln ny c my in gim st. Nu nhit ny vt qu gi tr ti a cho php (410F i vi mt s my in), my in s t ng tt.
5.2. Cc thit b lu tr d liu

a cng, hay cn gi l cng Hard Disk Drive, vit tt: HDD l thit b dng lu tr d liu trn b mt cc tm a hnh trn ph vt liu t tnh. a cng l loi b nh "khng thay i" (non-volatile), c ngha l chng khng b mt d liu khi ngng cung cp ngun in cho chng.. 5.2.1. Cu to a cng gm cc thnh phn, b phn c th lit k v gii thch nh sau: B phn a: Bao gm ton b cc a, trc quay v ng c. a t. Trc quay: truyn chuyn ng ca a t. ng c: c gn ng trc vi trc quay v cc a. B phn u c u c (head): u c/ghi d liu Cn di chuyn u c (head arm hoc actuator arm).
B phn mch in
Mch iu khin: c nhim v iu khin ng c ng trc, iu khin s di chuyn ca cn di chuyn u c m bo n ng v tr trn b mt a. Mch x l d liu: dng x l nhng d liu c/ghi ca a cng. B nh m (cache hoc buffer): l ni tm lu d liu trong qu trnh c/ghi d liu. D liu trn b nh m s mt i khi a cng ngng c cp in. u cm ngun cung cp in cho a cng. u kt ni giao tip vi my tnh. Cc cu u thit t ( jumper) thit t ch lm vic ca a cng: La chn ch lm vic ca a cng (SATA 150 hoc SATA 300) hay th t trn cc knh trn giao tip IDE (master hay slave hoc t la chn), la chn cc thng s lm vic khc... * V a cng: V a cng gm cc phn: Phn cha cc linh kin gn trn n, phn np y li bo v cc linh kin bn trong. V a cng c chc nng chnh nhm nh v cc linh kin v m bo kn kht khng cho php bi c lt vo bn trong ca a cng.
Ngoi ra, v a cng cn c tc dng chu ng s va chm ( mc thp) bo v a cng. Do u t chuyn ng rt st mt a nn nu c bi lt vo trong a cng cng c th lm xc b mt, mt lp t v h hng tng phn (xut hin cc khi h hng (bad block))... Thnh phn bn trong ca a cng l khng kh c sch cao, m bo p sut cn bng gia mi trng bn trong v bn ngoi, trn v bo v c cc h l thong m bo cn bi v cn bng p sut.
* a t (platter): a thng cu to bng nhm hoc thu tinh, trn b mt c ph mt lp vt liu t tnh l ni cha d liu. Tu theo hng sn xut m cc a ny c s dng mt hoc c hai mt trn v di. S lng a c th nhiu hn mt, ph thuc vo dung lng v cng ngh ca mi hng sn xut khc nhau. Mi a t c th s dng hai mt, a cng c th c nhiu a t, chng gn song song, quay ng trc, cng tc vi nhau khi hot ng.
* Track
Trn mt mt lm vic ca a t chia ra nhiu vng trn ng tm thnh cc track. Track c th c hiu n gin ging cc rnh ghi d liu ging nh cc a nha (ghi m nhc trc y) nhng s cch bit ca cc rnh ghi ny khng c cc g phn bit v chng l cc vng trn ng tm ch khng ni tip nhau thnh dng xon trn c nh a nha. Track trn a cng khng c nh t khi sn xut, chng c th thay i v tr khi nh dng cp thp a (low format ).
Khi mt a cng hot ng qu nhiu nm lin tc, khi kt qu kim tra bng cc phn mm cho thy xut hin nhiu khi h hng (bad block) th c ngha l phn c ca n r ro v lm vic khng chnh xc nh khi mi sn xut, lc ny thch hp nht l format cp thp cho n tng thch hn vi ch lm vic ca phn c * Sector Khu S vc sector/track S byte/track Tc truyn d liu (MBps) 28,02 26,54 25,56 23,59 22,12
1 2 3 4 5
456 432 416 384 360
233.472 221.184 212.992 196.608 184.320
Trn track chia thnh nhng phn nh bng cc on hng tm thnh cc sector. Cc sector l phn nh cui cng c chia ra cha d liu. Theo chun thng thng th mt sector cha dung lng 512 byte. S sector trn cc track l khc nhau t phn ra a vo n vng tm a, cc a cng u chia ra hn 10 vng m trong mi vng c s sector/track bng nhau. * Cylinder Tp hp cc track cng bn knh (cng s hiu trn) cc mt a khc nhau thnh cc cylinder. Ni mt cch chnh xc hn th: khi u c/ghi u tin lm vic ti mt track no th tp hp ton b cc track trn cc b mt a cn li m cc u c cn li ang lm vic ti gi l cylinder (cch gii thch ny chnh xc hn bi c th xy ra thng hp cc u c khc nhau c khong cch n tm quay ca a khc nhau do qu trnh ch to). Trn mt a cng c nhiu cylinder bi c nhiu track trn mi mt a t. * Trc quay Trc quay l trc gn cc a t ln n, chng c ni trc tip vi ng c quay a cng. Trc quay c nhim v truyn chuyn ng quay t ng c n cc a t. Trc quay thng ch to bng cc vt liu nh (nh hp kim nhm) v c ch to tuyt i chnh xc m bo trng tm ca chng khng c sai lch - bi ch mt s sai lch nh c th gy ln s rung lc ca ton b a cng khi lm vic tc cao, dn n qu trnh c/ghi khng chnh xc. * u c/ghi u c n gin c cu to gm li ferit (trc y l li st) v cun dy (ging nh nam chm in). Gn y cc cng ngh mi hn gip cho a cng hot ng vi mt xt cht hn nh: chuyn cc ht t sp xp theo phng vung gc vi b mt a nn cc u c c thit k nh gn v pht trin theo cc ng dng cng ngh mi. u c trong a cng c cng dng c d liu di dng t ho trn b mt a t hoc t ho ln cc mt a khi ghi d liu. S u c ghi lun bng s mt hot ng c ca cc a cng, c ngha chng nh hn hoc bng hai ln s a (nh hn trong trng hp v d hai a nhng ch s dng 3 mt).
* Cn di chuyn u c/ghi Cn di chuyn u c/ghi l cc thit b m u c/ghi gn vo n. Cn c nhim v di chuyn theo phng song song vi cc a t mt khong cch nht nh, dch chuyn v nh v chnh xc u c ti cc v tr t mp a n vng pha trong ca a (pha trc quay). Cc cn di chuyn u c c di chuyn ng thi vi nhau do chng c gn chung trn mt trc quay (ng trc), c ngha rng khi vic c/ghi d liu trn b mt (trn v di nu l loi hai mt) mt v tr no th chng cng hot ng cng v tr tng ng cc b mt a cn li. S di chuyn cn c th thc hin theo hai phng thc:

S dng ng c bc truyn chuyn ng. S dng cun cm di chuyn cn bng lc t.
* Hot ng Giao tip vi my tnh C ch c v ghi d liu a cng khng n thun thc hin t theo tun t m chng c th truy cp v ghi d liu ngu nhin ti bt k im no trn b mt a t, l c im khc bit ni bt ca a cng so vi cc hnh thc lu tr truy cp tun t (nh bng t). Thng qua giao tip vi my tnh, khi gii quyt mt tc v, CPU s i hi d liu (n s hi tun t cc b nh khc trc khi n a cng m th t thng l cache L1-> cache L2 ->RAM) v a cng cn truy cp n cc d liu cha trn n. Khng n thun nh vy CPU c th i hi nhiu hn mt tp tin d liu ti mt thi im, khi s xy ra cc trng hp: 1. a cng ch p ng mt yu cu truy cp d liu trong mt thi im, cc yu cu c p ng tun t. 2. a cng ng thi p ng cc yu cu cung cp d liu theo phng thc ring ca n. Trc y a s cc a cng u thc hin theo phng thc 1, c ngha l chng ch truy cp tng tp tin cho CPU. Ngy nay cc a cng c tch hp cc b nh m (cache) cng cc cng ngh ring ca chng (TCQ, NCQ) gip ti u cho hnh ng truy cp d liu trn b mt a nn a cng s thc hin theo phng thc th 2 nhm tng tc chung cho ton h thng. * c v ghi d liu trn b mt a S hot ng ca a cng cn thc hin ng thi hai chuyn ng: Chuyn ng quay ca cc a v chuyn ng ca cc u c. S quay ca cc a t c thc hin nh cc ng c gn cng trc (vi tc rt
ln: t 3600 rpm cho n 15.000 rpm) chng thng c quay n nh ti mt tc nht nh theo mi loi a cng. Khi a cng quay u, cn di chuyn u c s di chuyn n cc v tr trn cc b mt cha ph vt liu t theo phng bn knh ca a. Chuyn ng ny kt hp vi chuyn ng quay ca a c th lm u c/ghi ti bt k v tr no trn b mt a.Ti cc v tr cn c ghi, u c/ghi c cc b cm bin vi in trng c d liu (v tng ng: pht ra mt in trng xoay hng cc ht t khi ghi d liu). D liu c ghi/c ng thi trn mi a. Vic thc hin phn b d liu trn cc a c thc hin nh cc mch iu khin trn bo mch ca a cng. 5.2.2 Cc cng ngh ch to a cng 5.2.2.1 S.M.A.R.T S.M.A.R.T (Self-Monitoring, Analysis, and Reporting Technology) l cng ngh t ng gim st, chun on v bo co cc h hng c th xut hin ca a cng thng qua BIOS, cc phn mm thng bo cho ngi s dng bit trc s h hng c cc hnh ng chun b i ph (nh sao chp d liu d phng hoc c cc k hoch thay th a cng mi). Trong thi gian gn y S.M.AR.T c coi l mt tiu chun quan trng trong a cng. S.M.A.R.T ch thc s gim st nhng s thay i, nh hng ca phn cng n qu trnh li xy ra ca a cng (m theo hng Seagate th s h hng trong a cng chim ti 60% xut pht t cc vn lin quan n c kh): Chng c th bao gm nhng s h hng theo thi gian ca phn cng: u c/ghi (mt kt ni, khong cch lm vic vi b mt a thay i), ng c (xung cp, r ro), bo mch ca a (h hng linh kin hoc lm vic sai). S.M.A.R.T khng nn c hiu l t "smart" bi chng khng lm ci thin n tc lm vic v truyn d liu ca a cng. Ngi s dng c th bt (enable) hoc tt (disable) chc nng ny trong BIOS (tuy nhin khng phi BIOS ca hng no cng h tr vic can thip ny). cng lai (hybrid hard disk drive) cng lai (hybrid hard disk drive) l cc a cng thng thng c gn thm cc phn b nh flash trn bo mch ca a cng. Cm b nh ny hot ng khc vi c ch lm vic ca b nh m (cache) ca a cng: D liu cha trn chng khng b mt i khi mt in.
Trong qu trnh lm vic ca cng lai, vai tr ca phn b nh flash nh sau:
Lu tr trung gian d liu trc khi ghi vo a cng, ch khi my tnh a cc d liu n mt mc nht nh (tu tng loi cng lai) th a cng mi tin hnh ghi d liu vo cc a t, iu ny gip s vn hnh ca a cng ti hiu qu v tit kim in nng hn nh vic khng phi thng xuyn hot ng. Gip tng tc giao tip vi my tnh: Vic c d liu t b nh flash nhanh hn so vi vic c d liu ti cc a t. Gip h iu hnh khi ng nhanh hn nh vic lu cc tp tin khi ng ca h thng ln vng b nh flash. Kt hp vi b nh m ca a cng to thnh mt h thng hot ng hiu qu.
Nhng cng lai c sn xut hin nay thng s dng b nh flash vi dung lng khim tn 256 MB bi chu p lc ca vn gi thnh sn xut. Do s dng dung lng nh nh vy nn cha ci thin nhiu n vic gim thi gian khi ng h iu hnh, dn n nhiu ngi s dng cha cm thy hi lng vi chng. Tuy nhin ngi s dng thng kh nhn ra s hiu qu ca chng khi thc hin cc tc v thng thng hoc vic tit kim nng lng ca chng. Hin cng lai c gi thnh kh t (khong vi trm USD cho dung lng vi chc GB) nn chng mi c s dng trong mt s loi my tnh xch tay cao cp. 5.2.3 Thng s v c tnh ca HDD * Dung lng Dung lng a cng c tnh bng: (s byte/sector) (s sector/track) (s cylinder) (s u c/ghi). Dung lng ca a cng tnh theo cc n v dung lng c bn thng thng: byte, kB MB, GB, TB. a s cc hng sn xut u tnh dung lng theo cch c li (theo cch tnh 1 GB = 1000 MB m thc ra phi l 1 GB = 1024 MB) nn dung lng m h iu hnh (hoc cc phn mm kim tra) nhn ra ca a cng thng thp hn so vi dung lng ghi trn nhn a (v d a cng 40 GB thng ch t khong 37-38 GB).
* Tc quay ca a cng Tc quay ca a cng thng c k hiu bng rpm (vit tt ca t ting Anh: revolutions per minute) s vng quay trong mt pht. Tc quay cng cao th cng lm vic nhanh do chng thc hin c/ghi nhanh hn, thi giam tm kim thp. Cc tc quay thng dng thng l:
5.400 rpm: Thng dng vi cc a cng 3,5 sn xut cch y 2-3 nm; vi cc a cng 2,5 cho cc my tnh xch tay hin nay chuyn sang tc 5400 rpm p ng nhu cu c/ghi d liu nhanh hn. 7.200 rpm: Thng dng vi cc a cng sn xut trong thi gian hin ti (2007) 10.000 rpm, 15.000 rpm: Thng s dng cho cc a cng trong cc my tnh c nhn cao cp, my trm v cc my ch c s dng giao tip SCSI
5.2.4 Cc thng s v thi gian trong a cng * Thi gian tm kim trung bnh Thi gian tm kim trung bnh (Average Seek Time) l khong thi gian trung bnh (theo mili giy: ms) m u c c th di chuyn t mt cylinder ny n mt cylinder khc ngu nhin ( v tr xa chng). Thi gian tm kim trung bnh c cung cp bi nh sn xut khi h tin hnh hng lot cc vic th vic c/ghi cc v tr khc nhau ri chia cho s ln thc hin c kt qu thng s cui cng.Thng s ny cng thp cng tt. Thi gian tm kim trung bnh khng kim tra bng cc phn mm bi cc phn mm khng can thip c su n cc hot ng ca a cng. * Thi gian truy cp ngu nhin Thi gian truy cp ngu nhin (Random Access Time): L khong thi gian trung bnh a cng tm kim mt d liu ngu nhin. Tnh bng mili giy (ms). y l tham s quan trng do chng nh hng n hiu nng lm vic ca h thng, do ngi s dng nn quan tm n chng khi la chn gia cc a cng. Thng s ny cng thp cng tt. Tham s: Cc a cng sn xut gn y (2007) c thi gian truy cp ngu nhin trong khong: 5 n 15 ms.
* Thi gian lm vic tin cy Thi gian lm vic tin cy MTBF: (Mean Time Between Failures) c tnh theo gi (hay c th hiu mt cch n thun l tui th ca a cng). y l khong thi gian m nh sn xut d tnh a cng hot ng n nh m sau thi gian ny a cng c th s xut hin li (v khng m bo tin cy). Mt s nh sn xut cng b a cng ca h hot ng vi tc 10.000 rpm vi tham s: MTBF ln ti 1 triu gi, hoc vi a cng hot ng tc 15.000 rpm c gi tr MTBF n 1,4 triu gi th nhng thng s ny ch l kt qu ca cc tnh ton trn l thuyt. Hy hnh dung s nm m n hot ng tin cy (khi chia thng s MTBF cho (24 gi/ngy 365 ngy/nm) s thy rng n c th di hn lch s ca bt k hng sn xut a cng no, do ngi s dng c th khng cn quan tm n thng s ny. * B nh m B nh m (cache hoc buffer) trong a cng cng ging nh RAM ca my tnh, chng c nhim v lu tm d liu trong qu trnh lm vic ca a cng. ln ca b nh m c nh hng ng k ti hiu sut hot ng ca a cng bi vic c/ghi khng xy ra tc thi (do ph thuc vo s di chuyn ca u c/ghi, d liu c truyn ti hoc i) s c t tm trong b nh m. n v thng bnh bng kB hoc MB. Trong thi im nm 2007, dung lng b nh m thng l 2 hoc 8 MB cho cc loi a cng dung lng n khong 160 GB, vi cc a cng dng lng ln hn chng thng s dng b nh m n 16 MB hoc cao hn. B nh m cng ln th cng tt, nhng hiu nng chung ca a cng s chng li mt gi tr b nh m nht nh m t b nh m c th tng ln nhng hiu nng khng tng ng k.
H iu hnh cng c th ly mt phn b nh ca h thng (RAM) to ra mt b nh m lu tr d liu c ly t a cng nhm ti u vic x l i vi cc d liu thng xuyn phi truy cp, y ch l mt cch dng ring ca h iu hnh m chng khng nh hng n cch hot ng hoc hiu sut vn c ca mi loi a cng. C rt nhiu phn mm cho php tinh chnh cc thng s ny ca h iu hnh tu thuc vo s d tha RAM trn h thng.
5.2.4 Cc chun kt ni cng Hin nay cng gn trong c 2 chun kt ni thng dng l IDE v SATA. IDE (EIDE) Parallel ATA (PATA) hay cn c gi l EIDE (Enhanced intergrated drive electronics) c bit n nh l 1 chun kt ni cng thng dng hn 10 nm nay. Tc truyn ti d liu ti a l 100 MB/giy. Cc bo mch ch mi nht hin nay gn nh b hn chun kt ni ny, tuy nhin, ngi dng vn c th mua loi card PCI EIDE Controller nu mun s dng tip cng EIDE. SATA (Serial ATA) Nhanh chng tr thnh chun kt ni mi trong cng ngh cng nh vo nhng kh nng u vit hn chun IDE v tc x l v truyn ti d liu. SATA l kt qu ca vic lm gim ting n, tng cc lung khng kh trong h thng do nhng dy cp SATA hp hn 400% so vi dy cp IDE. Tc truyn ti d liu ti a ln n 150 - 300 MB/giy. y l l do v sao ta khng nn s dng cng IDE chung vi cng SATA trn cng mt h thng. cng IDE s ko tc cng SATA bng vi mnh, khin cng SATA khng th hot ng ng vi sc lc ca mnh. Ngy nay, SATA l chun kt ni cng thng dng nht v cng nh trn, ta c th p dng card PCI SATA Controller nu bo mch ch khng h tr chun kt ni ny cc phin bn Windows 2000/XP/2003/Vista hay phn mm s nhn dng v tng thch tt vi c cng IDE ln SATA. Tuy vy, cch thc ci t chng vo h thng th khc nhau. Do , ta cn bit cch phn bit gia cng IDE v SATA c th t ci t vo h thng ca mnh khi cn thit. Cch thc n gin nht phn bit l nhn vo pha sau ca cng, phn kt ni ca n. cng PATA (IDE) vi 40-pin kt ni song song, phn thit lp jumper (10-pin vi thit lp master/slave/cable select) v phn ni kt ngun in 4-pin, rng l 3,5-inch. C th gn 2 thit b IDE trn cng 1 dy cp, c
ngha l 1 cp IDE s c 3 u kt ni, 1 s gn kt vo bo mch ch v 2 u cn li s vo 2 thit b IDE. cng SATA c cng kiu dng v kch c, v dy c th s mng hn cng IDE do cc hng sn xut cng ngy cng ci tin v dy. im khc bit d phn bit l kiu kt ni in m chng yu cu giao tip vi bo mch ch, u kt ni ca cng SATA s nh hn, ngun ng cht, jumper 8-pin v khng c phn thit lp Master/Slave/Cable Select, kt ni Serial ATA ring bit. Cp SATA ch c th gn kt 1 cng SATA. * Hai chun kt ni cho cng gn ngoi l USB, FireWire. u im ca 2 loi kt ni ny so vi IDE v SATA l chng c th cm nng ri s dng ngay ch khng cn phi khi ng li h thng.
CHNG 6: LP RP CI T MY TNH 6.1. Kho st, lp rp cc thnh phn phn cng my tnh 6.2. Kho st BIOS c hiu catalog 6.3. Ci t WINDOWS XP, cc driver thit b 6.4. Phn chia, nh dng a cng bng WINDOWS 6.5. Ci t phn mm ng dng CHNG 7: SAO LU PHC HI D LIU 7.1. Phn chia a. 7.2. Backup, restore. 7.3. To file Image cho 1 partition. 7.4. Phc hi partition t file Image to. CHNG 8: BO MT VI REGISTRY, GROUP POLICY 8.1. Gii thiu 8.2. Cu hnh my tnh vi Registry, Group Policy 8.3. Bo v my tnh vi Registry, Group Policy

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CHNG 1 KIN TRC C BN CA MY TNH 1. Nhng thnh phn c bn ca my tnh Biu din thng tin trong my tnh I.

B nh trong (Memory) ROM-RAM

B nh ngoi (Mass store Unit)

Phi ghp vo/ra (I/O)

Thit b vo (Input Unit) Thit b ra (Output Unit)

Hnh 2.4: D liu lu c a vo CPU

Hnh 2.4.3: Truyn ti nhiu d liu trn mi chu k clock

Hnh 2.4.6. Gii php nhnh khng iu kin

Hiu sut 400 MHz 533 MHz

Tc truyn 3.2 GB/s 4.2 GB/s

ci thin hiu sut. Chng ta s ni k hn v vn ny phn di.

Hnh 2.7.2: Khi tm np v b gii m ch lnh trong kin trc Core

Di y l nhng tm tt v cc tnh nng chnh ca h Core 2:

Trn hnh 2.7.1 ta c th thy c mt bc tranh v chn ca Core 2 Duo CPU.

Hnh 2.7.1: Chn ca b vi x l Core 2

0.962V -1.35V 0.962V -1.35V -

143 65 W 60.1 mm2

2.13 SL94T E6420 GHz

143 65 W 60.1 mm2

E450 2.20 800 2 0 GHz MHz MB 2 GH 800 2 MB z MHz

SL93F E4400 SLA98

111 1.16V65 W 61.4 mm2 1.31V 65 W 73.3 1.16V1.31V

800 E440 2 2 MHz 0 GHz MB 1.8 800 2 MB GHz MHz

111 167 millio mm2 n 167 million

111 0.85V65 W 61.4 mm2 1.35V

SLACQ Q6700 2.66 GHz SL9UM Q6600 2.4 GHz

105 1.10V62,2 W 1.37V

SL9UM Q6600 2.4 GHz

1,066 105 1.10V8 MB 62,2 MHz W 1.37V

2.60 800 MHz 4 MB 44 W 100 GHz

Pentium Core Duo Core Solo M (Yonah)

Network Intel PRO Wireles / Wireless s 4965AG N

Multibus II Versabus VME

TM TRL TDS TMH TRH TDH

2.2 Bus m rng (Expansion bus)

3.1. Cc c trng ca b nh.

do lm thay i s tn x ca in t trn cc spin v l cc hiu n gin v hiu ng GMR.

Di y l mt hnh chp MRAM pht trin bi SPINTEC

Hnh 5. nh chp mt MRAM pht trin bi SPINTEC.

Hnh 4.1.1 s kt ni cng song song

Thanh ghi trng thi my in (ch c):

Thanh ghi iu khin my in:

4.4.3. Giao tip vi bn phm

Thanh ghi iu khin (64h)

4.4.5. PCI EXPRESS

php tc truyn d liu ln ti t 512MB ti 1GB/s

CHNG 5: CC THIT B NGOI VI

Bc lm sch s sch mc toner v kh in tch cn st li trn trng.

5.2. Cc thit b lu tr d liu

456 432 416 384 360

233.472 221.184 212.992 196.608 184.320

S dng ng c bc truyn chuyn ng. S dng cun cm di chuyn cn bng lc t.

Trong qu trnh lm vic ca cng lai, vai tr ca phn b nh flash nh sau:

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