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Appendix E.
Digital Circuit Kit of Han Baek Electronics 1
Chapter 11. FSM(Finite State Machine) Design 1
Appendix D. verilog HDL 1
Appendix C. Internet Website regarding Digital Circuit 1
Appendix B. MAX+plus User Guide 1
Electric Circuit Experiment
Appendix E. Digital Circuit Kit of Han Baek Electronics 2
Analog Circuits
Experiment Guideline
Chapter 1. Basic Circuit Backgrounds
Chapter 3. Oscilloscope and Resonance Circuit
Chapter 4. Various Diodes and its Properties
Chapter 5. Battery Tester and Charging Circuit analysis
Chapter 6. Audio Amplifier Circuit Design Logic Circuits
Chapter 7. Basic Logic Gate Design
Chapter 8. Combination Logic Circuit Design
Chapter 9. Calculation Circuit Design
Chapter 10. Flip-Flop and Counter Design
Chapter 11. FSM(Finite State Machine) Design
Chapter 12. Design Project
Chapter 13. Design Project
Appendix A. TTL Chip
Appendix B. MAX+plus User Guide
Appendix C. Internet Website Regarding Digital Circuit
Appendix D. verilog HDL
Appendix E. Digital Circuit Kit of Han Baek Electronics
English Index
Korean Index
ELECTRICAL AND ELECTRONIC ENGINEERING EXPERIMENTS:FUNDAMENTALS
Experiment Guideline
1. Purpose
Understand basic method of circuit experiment and its measuring tools. Als o, safety rules will be introduced to ensure safe experiment.
2. Summary
Method of Experimental Tools
Identifying resistance and capacitor Soldering Safety rules
3. Thoery
(1) Method of Experimental Tools
. Ammeter There are 2 types of ammeter;DC ammeter and AC ammeter. When you want to measure current in circuit as depicted in fig 1(a), connect ammeter in serial manner where the current has to be measured(see fig 1(b)). The measured value is less tha
n theoretical value because of internal resistance(Rm) inside ammeter. In order words , theoretically has to be observed but, actually it shows relations
hip. Therefore, internal resistance inside ammeter has to be small. In case of accurat e experiment, you have to measure internal resistance in advance, and compensate it s experimental value. As for DC ammeter, you have to be aware of its polarity. (+) probe has to be c onnected to higher voltage node, and (-) probe has to be connected to lower voltag e node. When you want to measure unknown current, it has to be measured in large scale to avoid damage to the ammeter.
fig 1. Connection of Ammeter
. Voltmeter There are 2 types of voltmeter; DC voltmeter and AC voltmeter. When you want measure voltage of circuit, connect voltmeter to the nodes that
has to be measured. That is, it has to be connected in parallel manner. In fig 2(a), VL is the theoretical voltage over RL load, and Vm is experimental voltage. Similarly , experimental value is less than theoretical value due to the internal resistance insid e voltmeter. Therefore, internal resistance have to be large to minimize error. Actual ly voltmeter usually has large internal resistance. Noting polarities, (+) probe has to be connected to higher voltage node, and (-) probe has to be connected to lower voltage node. When you want to measure unkno wn voltage, it has to be measured in large scale first to avoid damage to the volt m eter.
fig 2. Connection of voltmeter
. How to Use Multimeter With multimeter, you can measure many kinds of values such as voltage, current, resistance and so on. By using select switch, you can easily change the mode what
you want. It's quite convenient and basic device in analyzing circuit. Most of multimeters are designed to measure up to 1000[V] (DC/AC), 250[m A] (DC/AC), and 20[M]. Each mode has 35 ranges. Generally one multimete r has 50 [A]100 [A] DC ammeter and many electrical shunts and voltage dividers, and select switch. Also, internal battery is used for measuring resistance .
. Basic instructions to be observed Do not change the range while tester is connected to circuit
Make sure the polarity is correct when measure Vdc/Idc Do not leave the tester on '' mode after finished measuring. Measure after the tester's pointer stopped completely. Start with large scale range when measuring unknown value
How to Measure Resistance Set select switch on OHMS mode. Short two probes and initialize the mode. (Every time when mode changes) Connect the probes onto each nodes. Read the value. (1/2~2/3 of range would be appropriate.) fig 3. Multimeter Record the measured value.
. Mechanism of Resistance Meter
fig 4. Resistance Meter
In fig 4, ammeter shows 0[A] when
If you control
to be
as a maximum value(F.S) of ammeter, you
can use ammeter as resistance meter. In fig 4. node a, b is measuring point, and become controller of resistance. When is small, you have to add shunt in p
arallel to the circuit so that you may broaden the range of ammeter. Don't forget to set and modify (0 ohm adjustment) after you change the range.
Measuring Internal Resistance of Ammeter
fig 5. Measuring Internal Resistance of Ammeter Modulating in fig. 5, we can get , which induces maximum current, and
, which induces half current. Then, we can obtain internal resistance by calculatin g .
. Shunt
6. Shunt
As depicted in fig. 6, we can see the resister to broaden the range of ammeter. It's called Shunt Resister. Let's say as current measured by ammeter, as internal resistance of
ammeter, and
as shunt resister. We can obtain the ratio of current;
, and shunt resister can be calculated as following formula.
. Multiplier
Multiplier is the resister which is connected in parallel to voltmeter for broadenin g the range of the voltmeter.
Let's say of voltmeter, and
as voltage measured by voltmeter, as multiplier resister.
as internal resistance
fig 7. Multiplier
Using
, we can calculate multiplier resister as follows.
. Experimental Error It's usually assumed that there is no error when we conduct an experiment, but actually it's inevitable in most of practical cases due to several reasons. Common err or is caused by reading ammeter. It can be avoided if we practice reading measurem ent many times, or take average value of measured values. Pointer which indicates m iddle value between scales can cause error. Measuring level(the level difference betwe
en eyes and scale) can also cause error which can be easily revised. To remove this error, we can place mirror under the pointer of ammeter. At the level that the poin ter is not reflected by the mirror, we can read value precisely. There are other erro rs that cannot be removed easily. One of them is characteristic error of tools. It's u sually described explicitly. General purpose VOM and other measuring devices have 25% of error. Some special purpose devices have less than 1% of error. Where there are some changes in condition to circuit, it's often read imprecisely. Therefore, you have to take this error into account.
3-2. Identifying Resistance and Capacitor

A. Experimental Backgrounds Electrical engineering is the study of dealing with electrical energy and signal pro cess; generation, transformation, and transmission. Actually, Electrical signals from T V, Radio, communication devices are transformed and restored in various way. These complicated process can be implemented by using electrical circuits and devices. Co nsequently, it's necessary to understand the basic mechanism of electrical circuits an d devices. The properties of circuits and devices can be understood based on their basic el
ectrical quantities. Electrical charge is the most fundamental factor which determines various electrical effects. Primary charge is regarding proton and cation. Secondary c harge is regarding electron and anion. Amount of charge which one electron has cannot be divided more, that is, minim um value of charge. Charge has to move to transmit energy in circuits, Movement of the charge caus e current. Strength of the current can be defined as the amount of charges per unit surface per unit time, and its unit is Ampere. 1 ampere is the current which flows with amount of 1 coulomb per 1 second. You always have to concern that transmissi
on and transformation of energy certainly happen where there is current. Loss of the energy caused by charges movement is called voltage difference, or just voltage, an d its unit is Volt. Similarly, we define power which is transferred energy per unit tim e, and its unit is Watt. There are several basic elements in typical circuit. General properties of each ele ment are usually expressed by the relationship between voltage and current observed on the element. According to that relationship we, those elements can be categoriz ed into three. Resistance - It shows impressed voltage which is in proportion to its curre
nt. The coefficient of this relationship is defined as resistance. This elemen t is related to the amount of electrical energy which is transformed to hea t energy. Inductor - Its impressed voltage is in proportion to the rate of change of its current. The coefficient of this relationship is defined as inductance. Th is is element is related to the magnetic energy which is accumulated inside the circuit. Capacitor - Its impressed voltage is in proportion to the integral value of its current. The reciprocal of this coefficient is called capacitance. This ele
ment is related to the electrical energy which is accumulated inside the cir cuit. These three elements are called passive elements because the elements themselves cannot affect circuit without supply of voltage or current. In c ontrast, element which provides electrical energy(like power supply) is calle d active element. Active element is also categorized according to the relat ionship of voltage and current. Practical power supply has varying voltage and current that are modified depending on changes of load circuit. Some power supply provide constant output current regardless of change of volat
age or current in load circuit. When we discuss properties of actual power supply, its quite convenien t to think of ideal power supply which is connected to passive elements in serial or parallel.
constant voltage power supply - Ideal power supply which provides constan t load voltage and has the time function regardless of load. constant current power supply - Ideal power supply which provides consta nt load current and has the time function regardless of load.
Actual elements show linear relationship of voltage and current in limited range, and have duality. So, it's efficient to replace some circuit with equivalent circuit whe n we analyze more than two circuits. This relationship is called similarity or duality. Serial-circuit/parallel-circuit, voltage source/current source, R/C and R/C can be ex amples. Circuits can be simplified by using R, L, C which shows the same properties as previous one, and it's called equivalent circuit ro equivalent model. One difficult thing in implementing equivalent circuit is that there are many parasitic capacitance a nd inductance which are not desired. Coil which is desired to be zero resistance has
loss in coil, and even wire has inductance and capacitance. Condenser also has unw anted capacitor and dielectric loss. Moreover, transformer, quartz vibrator, transmissi on line, and antenna have a lot more complicated electrical effect. It's impossible to consider equivalent circuit which is perfectly the same, so we need to think of appro ximation depending on the extent of exactness. Next, let's talk about resonance which is pretty important in circuit theory. If sm all periodic force is applied to a certain object which has the same frequency as that of force, it's possible to cause big oscillation with small amount of force. It's called resonance. In electrical system, where there is matching source frequency which is th
e same as that of circuit, there is big electrical oscillation. To cause this, energy e xchange is needed between inductor's magnetic energy and condenser's electrical ene rgy. Therefore, resonance circuits must have both L and C and it's divided into seri al resonance, parallel resonance, and serial-parallel resonance depending on the conn ection. Modifying values of elements of circuit to match resonance frequency is called tuning, and unmatched state is called detuning.
B. Definition of Resistance we can observe many voltage-current relationship if we measure conductor to wh ich the voltage is applied. See fig 8. Like fig 8. (a), the element which allows current in one direction is called unilateral element, and likewise, the element which allows current in both direction is called bilateral element. In both cases, they show linear r elationship with small current. In this range, we can think it as v = Ri (Volt). R is c oefficient of voltage and currnet, and it's called resistance.
fig 8. voltage-current relationship of conductor
MKS unit of resistance is Ohm which has amount of resistance when 1 ampere o f current flows with 1 volt. Also, we call this relationship as Ohm's Law.
(Amp)
is called conductance, and its unit is Mho. Every conductor has some amount of resistance, and, of course, this causes Joul e heating owing to free electrons moving inside conductor. For there is electrical ene rgy consumption, a drop of electric pressure occurs.
C. Resistance Color Table
Three are four colors for identifying resistance as shown in fig 1. We can read c olor marked on reistance from left to right.(left side is slightly tilted more from the middle.) Usually the very right side color is gold or silver
fig 1. common resistance color table color first second third forth
black brown red orange yellow green blue purple gray white
0 1 2 3 4 5 6 7 8 9
0 1 2 3 4 5 6 7 8 9
100 101 102 103 104 105 106 -
1 (%) 2 (%) 3 (%) 4 (%) 0.5 (%) -
gold silver unmarked
10-1 10-2 -
5 (%) 10 (%) 20 (%)
values of resistance significant number exponent allowable error
First and second color stand for significant numbers. Third one means exponent of 10. Forth color shows an allowable error, and if case of 3 color, that is forth colo r is unmarked, it means the allowable error of that resistance is 20%. Special resistance for precise experiment has 5 color band which means that first three color bands show significant number, and forth color is exponent, and fifth col
or is an allowable error. Fig 2. shows the color table of the special resistance.
fig 2. special resistance color table color significant number exponent allowable error
black brown red orange yellow green blue purple gray white
0 1 2 3 4 5 6 7 8 9
100 101 102 103 104 105 106 107 108 0.5 (%) 0.25 (%) 0.1 (%) 0.05 (%) 1 (%) 2 (%)
gold silver
10-1 10-2
5 (%) 10 (%)
D. Identifying Condenser First 2 initial characters show the type of condenser.(For example, CF means ele ctrolytic condenser.) Second character shows electrical properties.(For example, M shows electrical pro perties.) Third character means electric capacity of condenser. The First two is significant number and last one is exponent. It's unit is [PF] and we express float number usin g R. Forth character is an allowable error which is the same as in fig 3. Also, % is us
ed for condenser whose capacity is more than 10PF, and PF is used for condenser l ess than 10PF. Rated voltage is displayed by using two characters. For example, 3B means that 3 is an exponent, and B is a significant number. Hence, we can determine it's 1250 [V] in table 4.
Table 3. Error of Condenser charactor B C D F G J K M N V X Z P
allowable error (%) allowable error (PF)

0.1 0.25 0.5 0.1 0.25 0.5
1 2 5 10
20
+ 20 + 40 + 80 + 100 30 - 10 - 10 - 20 - 0
1 2
Table 4. Rated Voltage of Condenser
A 0 1 2 3 1 10 100 1000
B 1.25 12.5 125 1250
C 1.6 16 160 1600
D 2.0 20 200 2000
E 2.5 25 250 2500
F 3.15 31.5 315 3150
G 4.0 40 400 4000
H 5.0 50 500 5000
J 6.3 63 630 6300
K 8.0 80 800 8000
3-3. Soldering
A. Organizing for soldering
Tools to be placed on the right side. - soldering iron, iron board, wet towel, radio pincher, nipper Tools to be placed on the left side. - soler, wire Tools to be placed on the center. - board, board supporter B. Soldering practice Put naked wire into the element side of practice board(not solder side) Bend the remnant wire with the degree of 90.
Cut out the wire, which exceeds copper coating, with nipper. Put the iron to the board slightly so that the copper coating and wire may be heated.(for 2 seconds) Start to solder maintaining the iron with the degree of 45.
fig 9. Way of Soldering
If solder is applied properly, detach both solder and iron. Don't move the board until solder is firmly applied.
Practice many times to get used to it.
C. Good Soldering and Bad Soldering Good soldering - Solder is applied properly. Its amount is the same, and it shows good polishing. Bad soldering - The amount of solder is irregular, and it has different size. - Remnant wire is so long, that it's possible to cause short.
- Insufficient solder could cause poor connection. - Excessive solder might be connected to the other unwanted part.
D. Cautions of Soldering Do not leave soldering iron with high temperature for a long time. Solder needs to be applied with proper amount, and it has to be flat. Wh en solder is applied to the board, it has to be a shape of semicircle. If it is closer to circle than semicircle, it's easy to get detached and cause po or connection and system error after completing the circuit.
IC elements are very sensitive to heat, so the quicker soldering is needed and try not to heat them for a long time. You can think of socket when solder that kinds of element like IC to prevent damage. The socket will protect heat transfer to the element, and also make it easy to replace it. Do not cut the edge of iron with nipper. The blunt iron cannot perform g ood soldering. When it is blunt, replace it with new one. Be careful not to get burnt the iron is hot. Make sure it is in ironing sta nd after use. When soldering is finished, unplug soldering iron and wait for a long time
until it is cooled enough.
Informing Experiment Cautions Inform experimental cautions because other devices are used as well as soldering iron.
3-4. Experiment Safety Rules

The laboratory must be clean and neat at all time. Students and instructors must follow all the safety rules of the laborato ry. Finish safety training before starting experiment, and make full understa nding of each experiment, specific dealing of tools, and other safety ste ps for an emergency situation. Follow the instructions of TA in laboratory, do not try unplanned expe riment.
Make full understanding of action for an emergency situation.(Location of telephone, extinguisher, fire alarm, and power breaker in case of fire or an emergency patient.) Understand how to user fire extinguisher and check its availability all t he time. Smoking, eating, gaming is not allowed in laboratory. Protector has to be worn when conducting experiment. (goggle, protection mask, protection globes, lab coat) Check electrical devices, isolation of flammable substance, secure of da
ngerous substance, water flow, arrangement of tools before leaving.. Experiment sockets must match rated capacity, and wire must be check ed if it's suitable, damaged, or heated. Experimental devices must not connected with one multiple socket. Electrical heating instrument are prohibited in laboratory.
3-5. Handing in Experiment Report

For efficient experiment class, students need to hand in pre-report before startin g experiment, and write result-report after finishing experiment. It's due on next exp
eriment class.
1. Objective
Based on basic understanding of current and voltage, Check out Kirchhoff' s Law. Also, by understanding concept of superposition, broaden basic circuit theory.
2. Key points
current and voltage Kirchhoff's Law Superposition
3. Theory
3-1. Current and Voltage
Properties of circuit are determined by amount of electrical quantity. The
most basic concept is electric charge. All kinds of electrical effect is caused by amount and movement of the electric charge. There are two kinds of char ge; positive one and negative one. The amount of charge of one electron is t he minimum value of electric charge, and it's C. The movement
of charge could cause transmission of energy, that is, current. This can be de fined as "the amount of electric charges which pass through a certain surface per unit time.". Moreover, voltage can be defined as "the amount energy wh ich unit charge gains or loses when it moves from one point to another in cir cuit.
3-2. Kirchhoff's Law

. Kirchhoff's Current Law (the 1st law : KCL) Kirchhoff's law is very important principle when we determine values of current a nd voltage. It's developed from ohm's law, and it has current law(the 1st law) and v oltage law(the 2nd law). Kirchhoff's current law can be summarized as "the sum of current which is flowin g in and out at arbitrary node is zero.". It can be also expressed as follows.
fig 1-1. Kirchhoff's current law
. Kirchhoff's Voltage Law (the 2nd law : KVL) Kirchhoff's voltage law can be summarized as "the total voltage around a closed loop must be zero." It can be expressed as [ ]. Let's say direction of close
d loop is clockwise, and a rise of voltage is (+) sign, and a drop of voltage is (-) sig n. We can draw this as in fig 1-2.
fig 1-2. Kirchhoff's voltage law
For example, we can apply Kirchhoff's voltage law when analyzing circuit as in fi g 1-3.
fig 1-3. the application of KVL
In Loop 1 In Loop 2 In Loop 3 we can get the exact value by calculating these equations.
3-3. Superposition
A. Law of Superposition
We can also apply the law of superposition to the electric circuit which has linea r elements with multiple power supply. It can be decomposed into separate circuits w hose summation is the same as the original one. Applying multiple power separately means that we connect one power while the others are disconnected. In other words, the principle of superposition can be universally applied to all kin ds of system which is expressed by using linear differential equation. Details are as f ollows.
fig 1-4. applying law of superposition If certain system has linear relationship(the result is proportional to the cause), s ummation of each case is equal to the whole system analyzed simultaneously. Therefo re, as for the circuits, an arbitrary voltage of certain nodes is the same as the sum
mation of each voltage for each power supply. Even if the supply is the function of t ime, this principle holds good. Applying this principle means can be analyzed as thin king of only one power while the others are off. Law of superposition is very important concept which is essential to high quality sound process, communication, broadcasting, and so on. shown in fig. 1-4(a), can be decomposed into and
as in fig 1-4(b), 1-4(c). Then, we can simply add up each current as follows.
4. Pre-report Basic Circuit Backgrounds .

Department Year Student ID Class Team Name
Current, voltage
What is charge, current, and voltage?
Explain passive element. Explain how to measure the voltage and current of resistor and several cautions.
Kirchhoff's Low
Kirchhoff's current low is callad node -voltage method. Using this method , express current in fig 1-9 as an equation of emf(E) Kirchhoff's current low is called mesh-current method. Using this metho d, express voltage for each resistor in fig 1-10 as an equation of emf(E)
Superposition
Calculate current for each resistor in fig 1 -14 by using both KCL and KV L. Calculate Calculate , , in fig 1-15(a). in fig 1-15(b).
Check if the value of I3 in fig 1-14 is equal to the sum of I3and I3in fi g 1-15.
5. Arrangements
unknown resistors, unknown condensers power supply resistor box : 1 [k]4, 100 [k]4, 200 [], 300 [], 500 [], 2 [k], 3 [k], 10 [k ], 20 [k], 40 [k], 50 [k], 100 [k] variable resistor : Rm = 10 [k], Rs = 500 []
DC ammeter : Full Scale 10 [mA] 4EA DC voltage meter : Full Scale 10 [V] 3EA tester, switch, galvanometer
6. Procedure
6-1. current, voltage
A. ammeter and voltage meter Set tester on DC, V mode and organize the circuit as in fig 1 -5(a). R
ecord the each value of voltage across
with tester(0, 50, 100 []
, 1 k, 5 k, 10 k, 20 k, 40 k, 60 k, 100 [k]). Similarly, Set tester on AC, V mode and organize the circuit as in fig 1-5(b). Record the each value of voltage across s before). with tester(same a
(a)
(b)
fig 1-5. AC, DC test circuit table 1-1.

[ 0 50 ] multiplier V[DC]
table 1-2.
100 1K 5K 10K 20K 40K 60K 100K
[ 0 50
multiplier
V[AC]
100 1K 5K 10K 20K 40K 60K 100K
B. Serial, parallel circuit. Connect R1, R2, R3 in serial as shown in fig 1-6. Measure I1, I2, I3, I4 a
nd V1, V2, V3 across each resistor, then record on table 1-3.
fig 1-6. serial circuit
As shown in fig 1-7, connect R1, R2, R3 in parallel. Measure I 1, I2, I3,
I4 and V1, V2, V3 across each resistor, then record on table 1-3. , , ,
fig 1-7. parallel circuit
table 1-3. connection current for each node I1 serial I2 I3 I4 I1 parallel I2 I3 voltage for each resistor V1 V2 V3 V1 V2
I4
V3
C. Resistance meter Set the circuit as in fig 1 -8 with variable resistor ](Supply voltage is 5[V], and a, b node is open.) Short a, b node, and set to have ammeter indicate maximum value tuned to 10 [k
. Open the nodes and check ammeter indicates 0 value. Now connect resistor box into a,b nodes. and measure the current for
each resistor, then record on table 1-4.
table 1-4. fixed resistor current measured by ammeter[mA] 0 1 2 3 4 5 6 7 8 9 10
Based on table 1-4, design resistance meter with ammeter. With this resistance meter, measure unknown resistors in table 1 -4, th
en record on table 1-5.
fig 1-8. circuit of 1/10 resistance meter
table 1-5.
resistance measured by tester [mA] resistance meter []
Set the circuit by adding resistance divider switch is off and a, b node is open) Connect
as shown in fig 1-8.(The
with the value of 1/10 of center value(5 [mA]) on a, b n
ode. After closed the switch, adjust ammeter to indicate center value(5
[mA]) by tuning
. Then, short the circuit again, and adjust ammete
r to indicate maximum value. Iterate this procedure, and we can get 1/ 10 scale resistance meter. Adjusting e 1-4. , measure the current for each resistor and record on tabl
table 1-6. fixed resistor 0 1 2 3 4 5 6 7 8 9 10
ammeter[mA]
referring table 1-6, design 1/10 resistance meter. Using this resistance meter, measure unknown resistors and record on table 1-7.
table 1-7. unknown resistor measured by tester
[mA] resistance meter []
6-2. Kirchhoff's law

. Kirchhoff's current law Set the circuit as shown in fig 1-9 onto the bread board. Adjust power supply of 12[V]. Reading ammeter, record on table 1 -8.
Check entering current( ) is equal to the summation of leaving current ( ).
table 1-8. I1 experimental value calculated value I2 I3 Ii
fig 1-9. circuit for confirming KCL
. Kirchhoff's voltage law
fig 1-10. circuit for confirming KVL
Set the circuit as shown in fig 1 -10. Adjust power supply of 12[V].
Measure the each voltage and record on table 1 -9. E= , R1= , fig 1-9. E1 experimental value calculated value E2 E3 R2= , R3=
Check if voltage source is equal to the summation of each voltage. Set the circuit as shown in fig 1 -11. Apply 10[V] to constant current circuit. Check if the current is 3mA a
nd connect the circuit on that in serial. Connect voltage source 5[V] onto the organized circuit. Measure the current and voltage of each resistor, and record on table 1-10. fig 1-10. experimental value voltage source[V] current source [mA] calculated value
V(R1) I(R1) V(R2) I(R2)
fig 1-11. basic circuit(1) for measure Organize the circuit as shown in fig 1 -12. Connect voltage of 5[V] 3[V] onto the circuit.
Measure the voltage and current for each resistor and record on table 1-11. table 1-11. experimental value voltage source[V] current source [mA] V(R1) I(R1) calculated value
V(R2) I(R2)
Organize the circuit as shown in fig 1 -13. Connect voltage of 5[V] onto the circuit. Measure voltage for each resistor as shown in fig 1 -12.
table 1-12. voltage [V] R1 [V] [] R2 [V] [] R3 [V] [] [V] [V] [V] experimental value calculated value
R4 [V] [] R5 [V] [] R6 [V] [] R7 [V] [] [V] [V] [V] [V]
R8 [V] [] R9 [V] [] [V] [V]
fig 1-12. basic circuit for measure(2) fig 1-13. basic circuit for measure(3)
6-3. Superposition
A. Principle of superposition
fig 1-14. circuit all Vdc is applied
fig 1-15. circuit each Vdc is applied
Organize circuit as shown in fig 1-14, and measure each current , and record on table 1-13.
Organize circuit as shown in fig 1 -15 (a), (b), and measure each curre nt; , , , , and record on table 1-13.
Check the principle of superposition from measu red values.
table 1-13. branch current I1 I2 I3 theoretical value [mA] measured value [mA]
I1' I2' I3' I1'' I2'' I3''
7. Report Basic Circuit Backgrounds
Team Name
Department
Year
Student ID
Class
Current, voltage
Analyzing the table from 1-1 to 1-7, explain why there are some d
ifferences between theoretical values and experimental values. Verify Ohm's law in serial/parallel connection of resistors.
Kirchhoff's Low
Verify Kirchhoffo's low on table from 1-8 to 1-12. If it does not ma tch exactly, explain the reason.
Superposition
Verify the principle of superposition from the table 1-13.
If there are some differences between calculated values and experime ntal values on table 1-13, explain the reason. Calculating each voltage in fig 1-14 and in fig 1-15(a),(b) across R3, verify the principle of superposition by using this data. If the voltage across is different from the calculated value, explain t he reason.
1. Objective
Understand the purpose of Thevenin's and Norton's equivalent circuit and its method. Know the importance of transmission of energy in DC circuit, and learn how to maximize it by reducing power loss. Understand equilibrium brid ge circuit and conduct actual experiment.
2. Key points
Thevenin's and Norton's theorem Condition of maximum transmission of energy Equilibrium bridge circuit
3. Theory
3-1. Thevenin's and Norton's theorem
We can replace all the circuit with equivalent circuit which has one voltage sourc e and one resister by choosing arbitrary nodes. It's quite useful when analyzing a certain circuit which contains many unknown re sistors. There are two kinds of equivalent circuits; Thevenin's equivalent circuit and Norton's equivalent circuit.
A. Thevenin's theorem In fig 2-1, is the same as the voltage of open circuit. is the same
as the resultant resistor which is replacing all source into internal resistor between the two nodes.
(a) arbitrary circuit
(b) Thevenin equivalent circuit
fig 2-1. Thevenin's theorem
Replace an arbitrary circuit in fig 2-1 into Thevenin equivalent circuit in fig 2-2 by using and connected in serial. Voltage and current measured in node a,b h
ave to be the same regardless of the load. This equivalence always makes sense for all kinds of load. We can apply Kirchhoff's voltage law for an arbitrary circuit in fig 2-2.
(2-1)
fig 2-2. circuit in fig 2-1
3-2 The condition of maximum power transmission

Power is the energy which is transferred per unit time, and its MKS unit is watt. One watt is the amount of power when one joule of energy is transferred
per one second. Therefore,
watt for constanct energy transfer.
For a drop of voltage in current direction, it shows P=iv because the power i s transmitted to that circuit. If the direction is opposite to that of current, P has ne gative sign, and it means the power is generated or supplied from other circuit at th at part.
We need to get interested in this power transmission. Most of load is the device which reacts to the transmitted power such as speaker, antenna, earphone and so o n. Consequently, it's an important matter to maximize power transmitted to the load. In fig 2-3, Thevenin voltage source(Vs), source resistor(Rs), load resistor(RL) is con nected. The current of RL is (2-2)
and the voltage of RL is
(2-3)
fig 2-3. power transmission in voltage divider circuit Thus, we can calculate power.
(2-4)
If Rs is fixed, the transmitted power varies depending on RL. For example, P is li ttle for small RL. If RL is a very large value, Rs can be neglected, so the equation is expressed as P = vs2/R, and it has a small value. This means that P has the minimu m value for large or small RL, the maximum value for mean RL. To calculate RL for maximum power transmission, differentiate the equation(2-4) fo
r RL, then, find the condition which makes it zero.
(2-5)
(2-5) shows P is maximum when RL = Rs for equation(2-4), and
(2-6)
is the maximum value of the transmitted power to the load.
3-3. Equilibrium bridge circuit

Measurer like VOM or EVM is the device which displays directly according to th e amount of current. It shows the measured value onto its panel. Bridge circuit is ki nd of an indicating instrument which consists of galvanometer, variable resistor, and voltage source. galvanometer indicates zero for equilibrium state.
The circuit depicted in fig 2-4. is called Wheaston bridge which has for resistor f orming diamond-shape.
fig 2-4. Wheaston bridge
Unknown Rx is connected between B and D. R1 and R2 is called ratio arm which is fixed value, and R3 is called standard arm which is variable. In fig 2-4, G is galvanometer which indicates zero when ther is no current. If th ere is a voltage drop between C and D, it means that the current flows through G. In other words, Vcd is zero when G indicates zero. It's called "the bridge is in equil ibrium", and of course, Vc = Vd.
4. Pre-report Basic Circuit Backgrounds .

Thevenin's and Norton's equivalent circuit

Describe Thevenin's and Norton's theorem. Solve the equivalent circuit problems by using Thevenin's and Norton's
theorem. Get the Thevenin's and Norton's equivalent circuit each for the circuit in fig 2-6. When RL = 30 , calculate the each voltage and current for the circuit in fig 2-6.
Maximum power transmission

Explain how to get maximum power transmission for VDC. Calculateand RL for maximum power transmission in fig 2-5 and its pow er Pmax.
fig 2-5. Circuit for maximum power transmission
Equilibrium bridge circuit

Describe the principle of equilibrium bridge circuit. Take an example how this circuit is used in the field.
5. Arrangements
unknown resistors, unknown condensers power supply resistor box : 1 [k]4, 100 [k]4, 4.7 [k]2 200 [], 300 [], 500 [], 2 [k], 3 [k], 5 [k] , 10 [k], 20 [k], 40 [k], 50 [k], 56 [k], 100 [k]
variable resistor : 10 [k] DC ammeter : Full Scale 10 [mA] 4EA DC voltage meter : Full Scale 10 [V] 3EA tester, switch, galvanometer
6. Procedure
6-1. Thevenin's and Norton's theorem
A. Verify Thevenin's and Norton's theorem for the circuit in fig 2-6.
Set the circuit as shown in fig 2 -6, and measure VL and IL across a, b node, then record on table 2-1.
table 2-1. measured value RL 470 [] 1 [k] 2 [k] theoretical value
VL
IL
VL
IL
3 [k] 10 [k]
Open a, b node in fig 2 -6, and measure cord on table 2-2.
between the nodes and re
Remove voltage source in fig 2 -6, and measure ode, then record on table 2-2.
between a and b n
Shore the a, b node in fig 2 -6, and measure en record on table 2-2. table 2-2.
between the nodes, th
veq [V]
theoretical measured
Req []
isc [mA]
fig 2-6. circuit diagram for table 2-3.
Replace RL with variable resistor, and modulate it for having 1/2
vol
tage drop between a and b node, then measure its resistance and recor d on table 2-3.(It's resistance is equal to .)
table 2-3.
Req []
theoretical meausred
Set the circuit as shown in 2-7, and measure Vab for each case by ch anging parameters;R1, R2, V1, V2, then record on table 2-4.
2-7. circuit diagram for table 2-4.
table 2-4.
R1
100 []
300 []
1 [k]
3 [k]
R1 V1 V2
theoretical [V] measured [V]
300 [] 2 [V] 2 [V]
500 [] 6 [V] 10 [V]
3 [k] 12 [V] 12 [V]
5 [k] 24 [V] 20 [V]
6-2. Condition for maximum power transmission
A. Check the condition for maximum power transmission in VDC. Set the circuit as shown in fig 2-8, and use the switch to "on-off" the circuit easily. Open the switch and let R L = 0. Close the switch again, and measure VL across RL. Let RL = 100 []. Close the switch again, and measure V L across RL..
table 2-5. RL VL WL WL 0.1K 1K 5K 10K 20K
Repeat previous procedure for all RL in table 2-5. Calculate WL and WT from VL and RL.
fig 2-8. circuit diagram
6-3. Equilibrium bridge circuit

A. Measure unknown in one ratio arm - Weatstone bridge.
Set the circuit which has one ration arm as shown in fig 2 -9. Open S1 , S2, and apply V = 6[V]. Use variable resistor for R 3, and let it have maximum value. The reason of adding R 4 is to prevent damage to the galvanometer when S1 is closed. Connect Rx between BD, then close S1(Rx should be smaller than 10 [k ]). In this case, keep S2 open. When the galvanometer doesn't react, ch eck if R3 is maximized. Reduce R3 gradually to have the galvanometer indicate zero, then close S2, retry this method if necessary. Read R3, and calculate Rx.
Open S1, S2 and maximize R3 again. Remove Rx, and repeat this proced ure with resistors shown in table 2-7. table 2-7.
Rx Measured R3 Rx
1 [k]
2 [k]
5 [k]
7 [k]
Measure Rx in ten ratio arm - Weatstone bridge. Let R1 = 470 [], R2 = 4.7 [k], making ratio arm(R2/R1) = 10. Then re
peat procedure(1).(Rx should be smaller than 100 [k].) Record on table 2 -8. table 2-8.
Rx Measured R3 Rx
10 [k]
20 [k]
50 [k]
70 [k]
fig 2-9. Weatstone bridge circuit diagram
7. Report Basic Circuit Backgrounds

Thevenin's and Norton's theorem

Draw Thevenin's and Norton's equivalent circuit from the result. And c heck if .
Observe variable resister RL measured in procedure is equal to Req. Explain the reason why there is a difference between experimental valu e of fig 2-7 and calculated value
Condition of maximum power transmission

Draw graph from the result by setting horizontal axis into RL and vertic al axis into WL. Draw graph from the result by setting al axis into WT. horizontal axis into RL and vertic
If WL and WT is different from calculated value, explain the reason. Get the relationship of Rs and RL for maximum power transmission from the result.. Discuss the condition of maximum power transmission for AC with simp le circuit diagram.
Equilibrium bridge circuit

What factor determines the exactness of this experiment? Why is the sensitive galvanometer used for this experiment?
Why is the resister added to the galvanometer?
Chapter 3.
Oscilloscope and Resonance Circuit
1. Objective
Oscilloscope is often used in circuit experiment to measure voltage and cu rrent. In chapter 3, we understand this device and learn how to use it. Also, applying the theory of calculus to electric circuit, understand R-C-L serial/p arallel resonance circuit, and its resonance frequency.
2. Key Points
Oscilloscope R-C, R-L serial/parallel circuit R-C-L serial/parallel resonance circuit
3. Theory
3-1. Fundamentals of Oscilloscope
Oscilloscope is widely used to analyze circuit visually and its official name is "Ca thode Ray Oscilloscope". This device shows varying signals onto its panel graphically, and it's used to analyze and measure electrical changes. Electrons emit lights when they collided with fluorescent material on the surface of cathode ray panel, and the s pecific circuit controls the locations of electrons. In addition, using oscilloscope, we c an observe many kinds of graph such as high frequency, pulse, output voltage and c urrent which general devices can't measure.
A. Basic usage Getting signal by using oscilloscope To prevent damaging oscilloscope, try not to exceed 400[V](Vdc+Vac) when oper ating oscilloscope. Connect probe or BNC cable to channel 1 to get signal.(When yo u use probe, set the probe ratio.) Modify the vertical scale to let it show the actual voltage level in probe tip. To set the probe ratio, press VERTICAL menu, then press Probe soft key rep eatedly to match the using probe and modify the ratio. To adapt the properties of probe to oscilloscope, make a good modification. If
we use 10:1 probe, we should observe the following steps. A) Connect 10:1 probe in channel 1, to the adjusting signal ous panel. B) Press "Autoscale" C) Using non-metallic tool, adjust trimmer condenser to flat the pulse signal on the screen. Fig 3-1 shows the shapes of pulse signal for each case. Overcompensation causes sharp peak(a), undercompensat ion causes blunt shape(c), exactcompensation makes signal flat(b). in previ
fig 3-1. compensation and the shape pulse signal
measuring voltage We can measure voltage parameters such as V(p-p), V(avg), V(rms), V(max), V( min), V(top), and V(base) using oscilloscope. Fig 3-2 and fig 3-3 is pulse signals me
asured at various point.
fig 3-2. pulse with clear V(top) and V(base)
A) Connecting the signal to oscilloscope, stabilize the graph on the scree
n. B) Press "Voltage" key, then soft key menu shows up with 6 items. of them is for measuring voltage. Source : Select channel for measuring voltage. Voltage Measurement : Vp-p, Vavg, Vrms can be measured. Measured value is determined by the voltage histogram. 3
fig 3-3. pulse with unclear V(top) and V(base) Clear Meas : Delete the result and remove vertical/horizontal curso r on the screen. Next Menu : Other menu with 6 soft key select items come s up ins tead of current menu.
) Press Vrms soft key. Then, oscilloscope measures Vrms automatically, and displa ys the result on the screen. Oscilloscope also measures initial pulse and perio d automatically..
B. Measurment of Frequance and Phase by Lissajous-figure using on X-Y Operation Put on those two same signal-voltages on Vertical Input and Horizontal Input of oscilloscope. One Input is the Unknown signal, the other inp
ut is Known-having readable frequency- sinusoidal oscillating signal. An d then, we obtain the Lisajous-figure (named fot French physicist Jules Antoine Lissajous and pronounced LEE-sa-zhoo) shown in Figure 3-4 those two signals of different frequency and phase , after that we adjus t the two signals with a fixed number. So we can take frequency ratio and phase of two signals by Lisajous-fiqure. Changing time axis (X-axis) into voltage axis (X-axis) in horizontal axis , we can obtain X-Y display mode and Lissajous-figure. (In our Laborat ory, pushing the Display button on the oscilloscope and change YT int
o XY in Format.) To get the unknown frequency by Lisajous-figure, give the unknown fre qeuncy signal on the Horizontal Axis (X-axis), and known-frequency sig nal on the Vertical Axis (Y-axis). If two input signal's voltage amplitud e are not same level, get the full Lisajous-figure within the square LC D pannel by using vertical two knobes. If its shape is same figure with shown in Figure 3-4, we can know the unknown frequency by the foll owing equation.
Figure 3-4 Lisajous-figure
In order to measure the phase difference between two sinusoidal signals of equal frequency, put those two signals into vertical input and horizontal input and adjust t he vertical knobes to get the full Lisajous-figure within the square LCD pannel. In F igure 3-5, with a phase difference of 0 ~ 90 degrees in the two signals to show the Lisajous-figure configuration, calculate the keeping in mind that vertical amplitude is V = Vmsin in time shown in figure 3-5 (a). = sin-1(V/Vm) (3-2)
Where the values of V and Vm, can be easily obtained from the Lisajous-figure. As phase difference shown in figure 3-5,
sin = (A/B)
= sin-1(A/B)
(3-3)
In (b) shown in figure 3-5, A is 2.4 DIV, B is 4.4 DIV, so by equation (3-2) phase difference is,
= sin-1 (2.4 / 4.4) = 33.1
(3-4)
Figure 3-5. In addition, phase difference is calculated by equation (3-5) from the Lisajous -figure with 0 ~ 90 degrees in the two signals. = 180 - sin-1 (A/B) (3-5)
If the shape is straight line, two signals have same phase degree or 180 phase diff erence. In the same amplitude of two signals, angle at the horizontal axis of the line ar shape is exactly 45. In the unlike amplitude of two signals, angle is greater or smaller than 45. When two signals' circular amplitude are same, phase difference is
90 or 270. When those are not same, it is ellipse.
Figure 3-6.
3-2. R-C, R-L serial/parallel circuit

Let us think about simple R-C/R-L circuit. Depending on the response of circui t, it is called differentiating circuit or integrating circuit. These circuits can be imple mented by using passive elements or operational amplifier. In this chapter, we simply use passive elements to make differentiating/integrating circuit. Fig 3-4(a) is differen
tiating circuit of R-C, and (b) is intergrating circuit.
(a) differentiating circuit
(b) intergrating circuit
fig 3-4. differentiating/integrating circuit
A. Phase relationship of voltage and current of R, L, C elements In case of R, = R and = 0(same phase) In case of L, = XL = jL, so V is faster than I by 90
In case of C, = XC =
, so V is slower than I by 90
B. Impedance and phase of R-L, R-C serial circuit
= R + jL
fig 3-5. R-L serial circuit
fig 3-6. R-C serial circuit
C. Admittance and phase of R-L, R-C parallel circuit
fig 3-7. R-L parallel circuit
fig 3-8. R-C parallel
3-3. R-C-L serial/parallel resonance circuit.

A. Serial resonance circuit Fig 3-9 shows simple serial resonance circuit, it's phase varies according to the change of source frequency. Analyzing serial resonance is similar to parallel resonanc e. Note that the amplitude of current goes to 0 when the frequency is very large or small..
fig 3-9. basic serial resonance circuit
fig 3-10. basic parallel resonance circuit
Capacitor blocks low frequency, and inductor blocks high frequency. Maximum p oint Vm/R(amplitude of current) is located where the reactance of inductor and capa citor is canceled out. Thus, resonance frequency can be expressed as,
This expression is the same as the resonance frequency of parallel resonance c ircuit. The relationship between Im and frequency can be described as shown in fi g 3-11, and its expressions are calculated as follows.
Bandwidth is defined where Im or Vm is 1/
of the maximum value. Therefore, R. Fig 3-11 shows r
that frequency is the point where impedance Z is equal to
esonance frequency and 3-db frequency. Bandwidth in serial resonance circuit is calc ulated as R/L, and we also define Q as follows.
For very large Q, resonance frequency is located as the center of bandwidth.
fig 3-11. the frequency response of resonance circuit
4. Pre-report Oscilloscope and Resonance Circuit

Mechanism of oscilloscope
Find out about the mechanism of oscilloscope and cathode cay display. Describe the way of connecting signal to oscilloscope, triggering, and m
easuring time/voltage/frequency.
R-C, R-L serial/parallel circuit

Observe output signal if step function, or square wave is applied to th e differentiating/integrating circuit. Explain the reason why the voltage, current and impedance become co mplex value in AC circuit. Explain the concepts of inductance, capacitance, reactance, impedance and admittance. And analyze voltage-current relationship of the R, L, C circuit.
R-C-L serial/parallel circuit

State the definition of resonance, and explain why it's important in seri al/parallel circuit. Analyze serial/parallel circuit. With the analyzed circuit in , draw its graph of V and I regarding fr equency. Derivate the formula about resonance frequency and Q. Describe what if Q is very large or small. Show the relationship between Q and bandwidth.
5. Arrangements
power supply Multi-Tester oscilloscope, signal generator resistors : 100[], 470[], 1[k], 3[k], 3.3[k], 4.7[k], 10[k]2 , 20[k], 500[k]
variable resistor : 5[k] condenser : 0.005[uF], 0.01[uF], 0.1[uF]
inductor : 20[mH]
6. Procedure
6-1. Oscilloscope
A. DC & AC voltage measuring Adjust oscilloscope to make it suitable to this experiment. Set the circuit as shown in fig 3 -12(a), and measure Vo for each R2 i n table 3-1 by using oscilloscope.
Measuring Vo with multi-testor, record on table 3-1(a). Set the circuit as shown in f ig 3-12(b), modify the signal generator to have 4Vp-p 1 [KHz].
fig 3-12. DC / AC circuit for measuring voltage Using oscilloscope, measure Vac(Vo) for each resistor in table 3 -1(b), t hen record on the table. Repeat using multi-tester.
table 3-1. (a) R2 Vo [V] (oscilloscope) theoretical experimental 3 [k] 4.7 [k] 10 [k] 20 [k]
error theoretical Vo [V] (multi-tester) experimental error
table 3-1. (b) R2 Vo[Vp-p] (theoretical) calculated Vrms 3 [k] 4.7 [k] 10 [k] 20 [k]
experimental Vo[Vp-p] (oscilloscope) Vrms error Vo[Vp-p] (multi-tester) experimental error
B. Measuring period and frequency. Connect the output of signal generator to the input node(vertical input)
of oscilloscope. Set the signal generator to have 2Vp-p and measure T for each frequen cy in table 3-2, then record its value. Also calculate its frequency(f)
table 3-2. signal frequency 1 [kHz] 15 [kHz] 30 [kHz] period (T) frequency (f)
C. Measuring time/phase difference between two signals For the frequency instructed in table 3-3, measure the input signal in
fig 3-13(a), (b), and the output signal. Then, calculate time/phase differ ence. Phase difference can be calculated like this.
fig 3-13. (a) RC circuit, (b) CR circuit
table 3-3. RC circuit input signal phase difference time theoreti measur cal 1 [kHz] 15 [kHz] 30 [kHz] ed diffe. error, CR circuit phase difference error, time diff. theoreti measur cal ed
6-2. R-C, R-L serial/parallel circuit

Set the circuit as shown fig 3 -14( R = 5 [k] in (a), C = 0.005 [F] , R = 500 [k] in (b), C = 0.005 [F]), and apply input with 1 kH z, 10 Vp-p of square wave and sinusoidal wave. Then draw its graph i n the following table. (a) differential circuit (b) integral circuit
Set the circuit as shown in fig 3 -15, and modify Vout to have 10 [kHz], 1 Vp-p sinusoidal wave. Measure VR and VL, then record on table 3-4. ( for each case, R = 100 [] )
table 3-4. ( f = 10 [kHz]) R 100 [] 470 [] 1 [k] 3 [k]
vR vL vOUT L theoretical =
Change the value of R as instructed in table 3-4, and repeate step (Maintain output of the generater to have 1 Vp-p after R is replaced)
(a) R-C differential circuit
(b) R-C integral circuit
fig 3-14. R-C differential/integral circuit
fig 3-15. R-L circuit with varying R
Calculate impedance(||), phase(), inductance(L) for each case in table 3-4. [ Hint ]
multiplying current(i) to = R + jL, then i = iR + jLi, such that
, and
Set the circuit as shown in fig 3-16, and modify R to let Lissajous' fig
ure have 45 phase difference. Measure R at that moment, then calcul ate inductance L. (Set oscilloscope on X-Y node) [ Hint ]
, = 45, thus, R=L
fig 3-16. circuit to modify phase difference Set the circuit as shown fig 3 -17, and adjust the output of generator t o have 1 Vp-p for 1 [k] resistor load. For R instructed in table 3 -5, measure Vout of RL parallel circuit, calcu
lte inductance(L), then record on table 3-5.
table 3-5. (f = 10 [kHz], Io = 1 [mAp-p]) R 100 [] 470 [] 1 [k] 3 [k]
vOUT [Vp-p] iR [mAp-p] iL [mAp-p] L
(Maintain voltage of the load to have 1 Vp-p after R is replaced)
[ Hint ]
fig 3-17. R-L parallel circuit
Set the circuit as shown in fig 3-18, then measuring resistor in table 3-6, calculate impedance(
for each
), phase(), and capacitor
(C), record on table 3-6. table 3-6. (f = 1 [kHz], C = 0.1 [F]) R 100 [] 470 [] 1 [k] 3 [k]
R vC vOUT C
theoretical =
(Maintain [ Hint ]
of generator to have 1 Vp-p after R is replaced)
fig 3-18. R-C with varying R
Set the circuit as shown in fig 3-19, and adjust R to let Lissajous figure have [ Hint ] phase. Calculate the capacitance(C) by measuring R.
fig 3-19. circuit to adjust phase
Set the circuit as shown in fig 3 -20, and adjust the output of generato r to have 1 Vp-p for 1 [k] resistor load.
For each resistor in table 3-7, measure lculate , then record on table 3-7.
of R-C parallel circuit, ca
table 3-7. (f = 1 [kHz], C = 0.1 [F]) R 100 [] 470 [] 1 [k] 3 [k]
vOUT [Vp-p] iR iC C
(Maintain [ Hint ]
of generator to have 1 Vp-p after R is replaced)
fig 3-20. R-C parallel circuit
6-3. R-C-L serial/parallel resonance circuit

Set the circuit as shown in fig 3 -21 with R = 100 [], C = 0.01 [F
], and measure VR, VL, VC, Vx as changing the frequency of generator as instructed in table 3-8. You have to keep output voltage(V out) equal to 1 [Vp-p] everytime after changed the frequency. Need to measure the frequency precisely that Vx = 0(or minimum) and Vx = VR. This is called resonance frequency and half power point frequency each, which is a very important concept. table 3-8. (Vout = 1 [Vp-p]) f [Hz] frequency of generator 7 [kHz] 20 [kHz]
vR [Vp-p] vL [vp-p] vC [Vp-p]

Vx
[Vp-p]
vout
[notice] The range of frequency(7 [KHz] 20 [KHz]) given in table 3-8 is not fixed, you can pick an arbitrary value
fig 3-21. R-L-C serial resonance circuit
Set the circuit as shown in fig 3 -22, and observe Lissajous figure on oscilloscope as changing the frequency of generator. Especially, measure t he frequency that makes Lissajous figure' phase "0"(resonance frequency), or 45(half power point).
fig 3-22. R-L-C circuit for observing output of serial circuit.
Set the circuit as shown in fig 3-23.(To conduct this experiment, it ne eds AC constant current source. Since it's not arranged on list, we ca
n replace this by connecting resistor(1 [K]) in serial to R -L-C parall el resonance circuit and adjusting output voltage of generator to keep t he load voltage(1 [K]) constant. Therefore, we need to keep the load voltage(1 [K]) constant after changed frequency.(In this experiment, we keep 1 [Vp-p].)
fig 3-23. R-L-C parallel resonance circuit
Changing the frequency of generator from 5 [KHz] to 20 [KHz], measu re Vout[Vp-p], and record on table 3-9. Don't forget to keep 1 [Vp-p],
and measure the point that has maximum Vout(resonance frequency), or 0.7 times of maximum Vout (half power point). Then record on table.
table 3-9. (io = 1 [mAp-p]) frequency [Hz] 5 [kHz] 20 [kHz]
vout [Vp-p] iR iC
ix iL
Set the circuit as shown in fig 3 -24. and observe Lissajous figure on oscilloscope as changing the frequency of generator. Especially, measure t he frequency that makes Lissajous figure' phase "0"(resonance frequency),
or 45(half power point).
fig 3-24. R-L-C circuit for observing the output of parallel circuit
7. Report Oscilloscope and Resonance Circuit

Mechanism of oscilloscope
Describe the electrical parameters that we can measure using oscillosco pe.
What are the errors that can be generated during measuring voltage wi th oscilloscope? When VOLTS/DIV is 0.2 [V]/DIV, and TIME/DIV is 0.5[ms]/DIVC, c alculate amplitude and frequency from the signal of oscilloscope in fig 3 -25..
fig 3-25. square wave from oscilloscope
Explain what we can measure with oscilloscope or not. What kind of m ethod can we use to measure current.
R-C, R-L serial/parallel circuit.

What's the phase differnce( ) between R and C in Why do we have to adjust the output of generator to have 1 V p-p when ever the resistor is changed in Compare L in and . Why do we have to adjust the output of generator to let load voltage( 1[k]) have 1Vp-p?
Compare C in and .
R-C-L serial/parallel circuit

From table 3-8, calculate the resonance frequency, half power point fre quency, and Q. Is V(R) = VOUT for the resonance state? If it isn't, why? Considering V(L), V(C) for the resonance state, What is Q of this res onance circuit?
Is Q in the same as that in ? If it is, what does that mean? (Neg lect the error between those values.) Graph the resonance line using table 3-8. What's the frequency which makes 0 phase in ? It this frequency the same as the resonance frequency in experiment (1)? Is the frequen cy, which makes 45 phase, the same as the half power point frequen cy measured in experiment (1)? If there are errors, analyze the reason.
Chapter 4. Various Diodes and its Properties
1. Objective
We learn about various diodes and its properties in this chapter. Firstly, measure the bias effect in junction diode, and observe its V-I property. Also , understand the forward bias, reverse bias in zener diode, and observe the r ange of constant voltage in experiment. Lastly, understand the rectifying circu
it using LED(Light Emitting Diode).
2. Key Points
junction diode zener diode LED(Light Emitting Diode) and its rectifying circuit
3. Theory
3-1. Junction diode
A. Analyzing ideal diode What's the feature of diode? Diode allows current in forward bias, and blocks cu rrent in reverse bias. Based on this property, we can graph the line for ideal diode as shown in fig 4-1, which works as perfect conductor for forward bias, perfect insul ator for reverse bias. 'Approximation 1" is called ideal diode. This makes it easy to analyze diode circuit.
(a) I-V graph
(b) forward bias
(c) reverse bias
fig 4-1. ideal diode
B. Analyzing diode with threshold voltage Generally, 0.7 V of forward direction is needed to conduct Si diode. Because
of this, it's necessary to consider this amount of voltage when dealing with small volt age source circuit. Fig 4-2(a) is I-V graph which shows 'approximation 2'. This figur e shows that the voltage drop of diode is constantly 0.7 V before it's over 0.7 V(Ge diode is 0.3 V). In orther words, 0.7 V is called threshold voltage. The equivalent circuit according to 'appromximation 2' is shown in fig 4-2(b).
(a) I-V graph
(b) equivalent circuit for forward bias
fig 4-2. diode property with 'approximation 2'
C. Analyzing diode with bulk resistance It the voltage is over threshold voltage, current through diode increases dramatic ally. In other words, the amount of current increase is large with small amount of vo ltage increase. The resistance from P, N junction measured over threshold voltage is called bulk resistance. This value( 'Approximation 3' shows ) is about 1 25 . ). After Si
in fig 4-3 (a) including bulk resistance(
diode is conducted, current cause voltage drop of crease voltage to increase current.
. Therefore, it's necessary to in
fig 4-3. I-V graph according with 'approximation 3'
3-2. Zener diode

A. Voltage Calibration
Zener diode is widely used to voltage regulator/voltage standard. Fig 4 -4 shows the diode circuit that dividing type voltage regulator is used. Th e diode is connected to load RL in parallel. Zener diode mainly keeps co
nstant load voltage in given range for varying load resistance or varying o utput voltage of DC source. Let us consider the behavior of circuit when source(VAA) is constant and l oad current(IL) varies. For output voltage(VOUT) is constant, such that IL = VOUT/RL, IT =
VO/RZIZ, then we can get the expression(voltage/current) as follows.

total current
I T = IL + IZ
load voltage(R)
V R = IT R VAA = VR + VOUT
For constant VAA and VOUT, VR is also constant. Consequently, total cur rent(IT) has to be constant as well. This is done by compensating change of I2. That is, for constant IT, and varying IL, then IZ = IT - IL. If voltage of zener diode(VZ) is equal to VOUT, that expression makes sense.
fig 4-4. zener diode used to parallel voltage regulator
For only enough varying V OUT, there can be a change of diode current( IZ) which is able to compensate load current difference(I L). So we have to choose the zener diode whose properties(voltage, current) meet the conditi
on of circuit. The diode shown in fig 4-4, is used to prevent the change of serial voltage source maintaining output voltage(V OUT) and load current( IL) constant. Think about a circuit applied by serial voltage source(V AA). If the source voltage(VAA) is increased, output voltage(VOUT) is apt to increa se. As a result, zener current(I Z) and voltage drop of R(V R) increase. Also IT increases. If we design regulator circuit properly, V R is equal to V
AA,
and VOUT goes back to its initial value. In same way, if V AA decreases,
IZ also decreases, which makes VOUT have initial value. R is determined b y the properties of diode, and the state of V AA and IL.
3-3. LED and diode rectifying circuit

A. Light Emitting Diode LED stands for Light Emitting Diode. It emits light when current flows PN juncti on semiconductor. LED is first used for displaying goods of U.S. army in 1968. It's l ight emitting device that solved filament's drawback, and its market is growing rapidl y. LED's light color covers most part of range of visible light, and it's slightly differ
ent depending on the material. GaAsP, GaP, GaAlAs is generally used, but recenly AlGaInP(from red to yellow), InGaN(from blue to green) is widely used.
B. Rectification circuit LED, one of diodes, allows current in forward bias, blocks current in reverse bias. This is called rectification.
(a) half wave rectification circuit
(b) input-output signal
fig 4-5. half wave rectification circuit Rectification can be divided into half-wave rectification and full-wave rectificat ion. Half-wave rectification circuit can be described as in fig 4-5(b) by comparin g input/output signal for v(t) = Vm sint.
Full-wave rectification has two method. One is to use transformer with center ta p, and the other is to use bridge diode.
Using transformer with center tap If we set full-wave rectification circuit using center tap transformer and two diod es as shown in fig 4-6(a), we can full-wave rectified signal at the load because diode D1, D2 operate in alternate manner for each half period.
(a) full wave rectification circuit using transformer with center tap
(b) input-output signal fig 4-6. full wave rectification circuit using center tap of transformer Using bridge diode circuit Fig 4-7 shows full-wave rectification circuit using bridge diode circuit.
(a) bridge diode full-wave rectification circuit (b) current for positive period
(c) current for negative period
(d) output signal of bridge diode circuit
fig 4-7. bridge diode full-wave rectification circuit
the average value and frequency of output voltage of bridge diode full-wave rectif
ication circuit is equal to that of transformer with center tap. The difference is source voltage. 2nd voltage of transformer is a half as large as one with center tap, and so is reverse bias voltage. Practical diode with center tap, which is not ideal, shows output voltage for forward bias 0.7[V] smaller than input v oltage, but bridge diode full-wave rectification circuit has tow diodes that are conduc ted. Thus this makes 1.4[V] voltage drop.
4. Pre-report Various Diodes and its Properties

junction diode
What is bias? Why do we use bias when it comes to circuit.
Explain why junction diode allows current when forward bias, and does not when reverse bias. With 'approximation 3', estimate equivalent circuit of junction diode in fig 4-3. Why resistance is necessary in the equivalent circuit of diode?
zener diode
Compared with junction diode, what's the primary difference of zener di ode? Describe the mechanism of rectification properties of zener diode. Describe the behavior of parallel voltage regulator using zener diode.
Which bias is used for zener diode? Forward bias, or reverse bias?
LED and diode rectification circuit

Explain the mechanism of luminescence of LED and its type. Compare the mean value of half-wave rectification circuit and that of f ull-wave rectification circuit.. Get V(rms), amplitude of voltage source, and reverse peak voltage of f ull-wave rectification circuit using center tap. Compare reverse peak voltage of full -wave rectification circuit using ce nter tap and that of full-wave rectification circuit with bridge diode.
5. Arrangements
power supply : variable low voltage source, high current source, consta nt V(DC) source, DMM, VOM, milli-ammeter, curve tracer for experiment(20,000 /V) resistor : 470 (1/4W) resistance : 3.3k-1/4W, 1K-2W, 500-5W Si diode : 1N914 (alternative : 1N914 or small signal Si diode) Ge diode : 1N60 (alternative : 1N4454 or small signal Ge diode)
semiconductor device : 1N4740 (alternative : 1 W -10 V zener diode re gardless of its type 1N5240) 3-coil transformer (primary winding 220 [V], secondary winding , 0 [V], 15 [V]) oscilloscope 1N40044 15 [V]
6. Procedure
6-1. junction diode

Set the circuit as shown in fig 4-8 to have 1N914 Si diode under forw ard bias. What node has to be connected to secondary node to make i t under forward bias? Adjust variable DC voltage source to let voltage measured in diode(V AK ) have 0.7V. Measure the diode current(ID) and record on table 4-1. Connect diode in opposite direction, measure ID, then, record on table 4-1. Set the diode under reverse bias, measure V AK, then record on table 4 -1 Calculate the resistance(V AK/ID) for each case(forward bias, reverse bias).
Separating diode from the circuit, measure its resistance. Switch
the p
robe of ohm-meter and measure it again. Internal battery of ohm-meter has polarity, so its probe will have polarity. Record the data on table 4-1 which is measured with correct polarity.
table 4-1. measuring diode order 2 3,4 5 X X forward bias : reverse bias : VAK 0.7V ID R of diode
12
RB :
fig 4-8. circuit diagram for step (1)(5)
Reconnect diode to the circuit and apply voltage to set it under forwar d bias. Adjust variable DC source to V AK given in table 4-2, then meas ure and record ID for VAK. Connect the diode in opposite direction to set it under reverse bias, a nd adjust variable DC source with the value instructed in table 4-2. T hen measure and record ID. This value is small, so sensitive multi-meter (A) is needed. With the point of VAK along X-axis and the point of ID along Y-axis, gr aph characteristic curve.
Graph characteristic curve of approximation 1/2/3 on the plot in 'step 8' Using two points on the characteristic curve of forward bias regarding VAK and ID, calculate bulk resistance(rB) and record on table 4-2.
table 4-2. I-V characteristic step 6 VAK, V forward bias ID, mA step 7 VAK, V reverse bias ID, A
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0 -5 -10 -15 -20 -25 -30 -35 -40
6-2. characteristics of zener diode

A. I-V characteristics of reverse bias Set the circuit as shown in fig 4 -9, and open the switch S. V AA is con stant source adjusted to 0 V. Adjust M to minimum current range(20,0 00 /V VOM). Set the circuit as shown in fig 4 -9, and open the switch S. If there is current through diode when VAA = 0, measure it. Then, record on table 4-3.
Adjust output(VAA) to let VAB = 2.0 V. Measure the current through di ode, and record on table 4-3. Repeat 'step 3' for each VAB in table 4-3. You can modify the range of M if necessary. Calculate RZ (RZ = VAB/I), then record on table 4-3.
fig 4-3. reverse bias step 2 3 I, mA step 6 6 I, mA 5 10
4 4 4 5 2.0
6 6 6 6
20 30 40 50
Adjust output(VAA) to have diode current I = 2 mA. Measure VAB across the diode, and record on table 4-3. Also calculate RZ, and record on table 4-3.
Repeat 'step 5' for each current value, and record each V AB and RZ on table 4-3.
fig 4-9. circuit for observing zener diode reverse bias effect
B. I-V characteristics of forward bias Open switch S so that power is not applied to circuit. Modify source o utput voltage to 0 V, and connect it in opposite direction. table 4-4. forward bias step 8 I, mA RF 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Close switch S, and measure the forward bias current of diode for giv en VAB in table 4-4. Calculating RF = VAB/I, and record on table 4-4.
With table 4-3, 4-4, plot the following instructions. (a) diode voltage vs diode current(Y axis) (b) diode voltage in zener range vs diode current (c) diode resistance vs voltage for each case:forward bias, reverse bias.
fig 4-10. voltage regulator experimental circuit
C. zener diode as a voltage regulator Set the circuit as shown in fig 4 -10, then open switch S. Setting V AA t o 0 V, and M is milli-ammeter with 100mA scale. Close switch S, then steadily increase VAA until I2 = 20 mA. Measuring source voltage and load voltage, then record on table 4-5. Determine the range of VAB which keeps VAB in step 11 constant in 0.1 V deviation. In this range, measure the change of I Z and IT , then record on table 4-5.
table 4-5. voltage adjustment step 11 12 13 + 0.1 - 0.1 ,mA 20 ,mA
6-3. LED and rectifier circuit
Set the following parameters of oscilloscope : SWEEP TIME/DIV = 5 [ ], VOLTS/DIV of channel A, B = 20 [V], channel select mode = dual , channel input mode = DC
fig 4-11. half-wave rectifying circuit
Set the circuit as shown in fig 4 -11, and close SW. Observe input volt age vi(t) and output voltage vo(t), then record on table 4-6.
Using center tap of transformer, set the circuit as shown in fig 4 -12, and close SW. Observe input voltage vi(t) and output voltage vo(t), the n record on table 4-7. table 4-6. input and output voltage of half-wave rectifying circuit (a) wave on channel A(vi) (b) wave on channel B(vo)
table 4-7. input and output voltage of full-wave rectifying circuit using center tap (a) wave on channel A(vi) (b) wave on channel B(vo)
fig 4-12. half-wave rectifying circuit
Connect red(+) probe(channel A) to node C, black( -) probe(channel A)
to node A. red(+) probe(channel B) to node D, and black(-) probe(chan nel B) to node A. Then, measure input signal and diode voltage, and p lot the graph on table 4-8.
table 4-8. input voltage and reverse peak voltage (a) Channel A(input signal) (b) Channel B(diode voltage)
Set the circuit as shown in fig 4-12 using four diodes, and close SW.
Then, observe input voltage(v i(t)) and output voltage(vo(t)) with oscillosc ope, and plot the graph on table 4-9.
table 4-9. input voltage and output voltage of bridge diode full-wave rectifying circuit. (a) Channel A(input signal) (b) Channel B(output signal)
fig 4-13. bridge diode full-wave rectifying circuit
Connect red(+) probe(channel A) to node B, black( -) probe(channel A) to node C. red(+) probe(channel B) to node D, and black(-) probe(chan
nel B) to node C. Then, measure input signal and diode voltage, and p lot the graph on table 4-10.
table 4-10. input voltage and reverse peak voltage (a) Channel A(input signal) (b) Channel B(diode voltage)
7. Report Various Diodes and its Properties

junction diode
What are the other applications of diode in electrical devices.
Using 'approximation 3' in fig 4 -3, draw equivalent circuit of junction d iode.. Explain the reason why there is difference between measured value and calculated value in table 4-2.
zener diode
Example electrical devices that zener doide can be used. Compare junction diode and zenor diode. Compare I-V curve of zener diode and that of general diode.
LED and diode rectification circuit

Calculate the mean value of output voltage of half -wave rectifying circu it in table 4-6(b). Calculate the mean value of output voltage of full -wave rectifying circui t using transformer center tap in table 4-7(b). Get the reverse peak voltage from table 4 -8(b). Calculate the mean value of output voltage of full -wave bridge diode re ctifying circuit. Get the reverse peak voltage from table 4 -10(b). Compare the mean value of half-wave rectifying circuit and that of full-
wave rectifying circuit. Compare the reverse peak voltage of full -wave rectifying circuit using t ransformer center tap, and that of bridge diode full-wave rectifying circ uit.
Chapter 5. Battery Tester and Charging Circuit Analysis
1. Objective
Based on basic circuit theory and experiment, Design economical battery t ester & auto battery charging circuit and analyze its mechanism. By conducti ng this experiment, you'd deepen the knowledge of electrical electrical circuit.
2. Key Points
Economical battery tester Auto battery charging circuit
3. Theory
3-1. Economical battery tester circuit
A. Transistor the transistor used in this experiment(BC547B) is one kind of NPN BJT.
Therefore it has the structure like fig 5-1, and each node is called Emitter, Collector, Base.
fig 5-1. NPN BJT model
This BJT can be categorized as table 5-1 depending on its bias state of co nection. table 5-1. Base-Emitter junction cut off reverse active forward saturation forward active reverse reverse forward forward Base-Collector junction. reverse forward reverse forward
Concerning threshold voltage of PN junction, however, 0.7V has to be appli ed to base-emitter to turn-on base-emitter voltage. This VBE<0.7 region is ca lled cut-off region. Likewise, base-collector junction needs more than 0.7V, the n its behavior looks like forward saturation region. Considering all these conditi ons of PN junction, the characteristic region of BJT can be categorized as sho wn fig 5-2 : cut-off, active, and saturation region.
fig 5-2. operation region of BJT
3-2. Auto battery charging circuit

A. Characteristics of SCR Added Gate to PNPN Diode, SCR opens Anode-cathode when voltage is applied to Gate. We call Gate voltage as a trigger signal, and we can control the current fl owing into Anode-Cathode by adjusting this.
fig 5-3. 2P4M model
B. Mechanism If we (+) voltage to Anode, (-) voltage to Cathode, PN junction is in reverse bia
s. Thus, SCR operates in cut-off region. If we increase the trigger signal, the region gets weak and goes away. That is, SCR is on, and current flows from Anode to Ca thode. Once, SCR is on, it remains on even in low current by decreasing Gate volta ge. To off SCR, 0V, or (-) votlage has to be applied to Anode.
4. Pre-report Battery Tester and Charging Circuit Analysis

Economical battery tester circuit

Explain the mechanism of Economical battery tester
Analyze the elements of Economical battery tester and its circuit syste m. 1) Explain the quality difference in accordance with capacitor. 2) Applying the characteristics of transistor, explain the mechanism of circuit system. 3) Explain the difference in accordance with resistance ratio.
Auto battery charging circuit
Explain the mechanism of Auto battery charging circuit. Analyze the elements of Auto battery charging circuit and its circuit sy stem. 1) Explain the role of LED1, LED2. 2) Apply analysis of SCR to circuit. 3) Analyze of the behavior of zener diode depending on its characteristics. 4) Explain the role of R5. 5) Explain the role of D3.
6) Explain the role of other elements and devices.
5. Arrangements
power supply : AC 120Vrms transformer : 120V/12V resister : 1k, 10, 80, 39, 100, 1502 , 270, 470 variable resister : 10k, 100k,470k diode : 1N40015EA, zener 1N5227 SCR : 2P4M2EA rechargeable battery : 1.5V6EA
LED 3EA(red 2EA, green 1EA) Capacitor : 1nF switch 1EA(reset) transistor : BC547B 1EA
6. Procedure
6-1. Economical battery tester circuit
A. PSPICE simulation
Conduct PSPICE simulation referring fig 5-4, and analyze circuit
system.
To set the circuit which turns on LED when more than 6.5V is applied to battery tester, design the following circuit with PSPICE. Once, the circuit is set, by using DE sweep and Parameter sweep, chec k the battery tester. In this simulation we can check the current flowin g through R3 instead of checking light of LED. DC sweep Parameter sweep battery Change R4 from 400 to 700 from Parameter sweep.
fig 5-4. battery tester circuit for PSPICE simulation
B. designing actual circuit Battery tester is used to check the condition of battery. This specific battery tes ter consumes very low energy. The light of LED for a short moment means that the re is still enough voltage level in electrical device like radio receiver, cassette tape r ecorder, and so on. This flash is caused by the discharge of capacitor(C1). If we clos e switch(S1), conducting TR(T1), C1 discharges through R3 and LED. Required minimu m battery voltage is determined by voltage divider R1/R2. R2 and R3 can be calculate d as follows
(5-1) (5-2) If the minimum volatge is 6.5V(from 9V battery), for inatance, R2=10, R3=39. R4 ranges from 10 K to 1 M. For high R, its economic but it takes long time. It takes about 10 seconds for R4 = 100 K.
fig 5-5. battery tester circuit
6-2. Auto battery charging circuit

A. PSPICE simulation Conduct PSPICE simulation referring fig 5-6 and analyze circuit system.
fig 5-6. transformer circuit for PSPICE Set the transformer circuit using PSPICE with 120Vrms source, 12Vrms
output as shown in fig 5-6. attach this circuit diagram and its output signal to report. Use this transformer circuit for this experiment. Set parameter sweep w hich ranges from 5V to 6V for 6V battery, and check if current flows through LED.(The following circuit doesn't have LED, so check if curre nt flows through R2 and R4.) As battery is charged(from 5V to 6V), check if current flows through L ED by using transient analysis.
fig 5-7. Auto battery charging circuit with PSPICE
B. designing actual circuit Auto battery charging circuit shows state of battery using LED. For charge state , LED1 is on, then it goes dark as battery is charged. Finally it goes out when com pletely charged, and LED2 is on so that shows the charging is finished. To sum up, this circuit shows LED1-ON, LED2-OFF for charge state, LED1-OFF, LED2-ON for charge completion.
In auto battery charging circuit, the current from (+)node of bridge circuit follows into battery through via R1 and SCR1 for discharged battery. Once charging is com pleted, due to zener diode's characteristics, the current goes to ground in SCR2 dire ction.
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7. Report Battery Tester and Charging Circuit Analysis

Economical battery tester

Submit economical battery tester and its circuit diagram.
Record the data of economical battery tester. Compare PSCIPE simulation and actual experiment. Compare theoretical result and experimental result, and explain the rea son.
Auto battery charging circuit

Submit auto battery charging circuit and its circuit diagram. Assess the quality of auto battery charging circuit and record charging
time. Compare PSCIPE simulation and actual experiment. Compare theoretical result and experimental result, and explain the rea son.
Chapter 6. Audio Amplifier Circuit Design
1. Objective
To implement Audio Amplifier, first we need to understand power supply, which is AC to DC adapter. Understand the mechanism and elements used to
maintain constant DC voltage, and calculate its efficiency. Moreover, by impl ementing audio amp circuit which is has tone tuning function, deepen the und erstanding of actual audio device.
2. Key Points
Power Supply Audio Amplifier
3. Theory
3-1. Power Supply
A. rectifying circuit It needs 5V DC to run Audio Amplifier, so we discuss how to get 5V DC from commercial voltage in this part. Because we already talked about rectifying circuit in chap 3, in this experiment, let us think of the rectifying circuit with capacitor and r esistor.
3-2. Audio Amplifier

A. Op-amp First let us analyze ideal op-amp for general circuit analysis. Actually the real op -amp is used in experiment, so we need to modify it precisely. Fig 6-1 shows intern al structure of op-amp chip. As you see, general op-amp has 5 nodes. Consequently , it's slightly different from ideal op-amp. In this expression, V+ and V- is the power source of op-amp.
fig 6-1. structure of LM318
fig 6-2. equivalent circuit of op-amp
The equivalent circuit of op-amp is depicted as shown in fig 6-2, and it has diffe
rent power source and gain depending on the sort of op-amp B. Filter The concept of filter is conceived quite a long time ago. Especially electric filter is used to remove unwanted nose from electrical signal. This filter can be realized wi th RLC elements. RL or RC filter is called 1st order filter, and RLC filter is called 2nd order filter. In this experiment, using 2 RC filters, deign the audio amplifier that can amplify high/low frequency of audible signal. Fig 6-3 shows a simple filter. (a) is low pass filter, (b) is high pas filter.
(a) low pass filter
(b) high pass filter fig 6-3. RC filter
If we apply Laplace's transform to these circuits, we can anaylize Vout/Vin in fr equency domain. Comparing gain of low frequency band and high frequency band, we can identify the characteristics of filter.
4. Pre-report Audio Amplifier Circuit Design

Power Supply for an Audio Amplifier

Explain the mechanism of power supply in this experiment.
Understand the elements used in each step, then analyze circuit with r espect to following instructions. 1) characteristics of transformer 2) bridge rectifier 3) capacitor used in each step 4) Linear Voltage Regulator 5) MOSFET in step 6, and its necessity 6) Explain the definition of efficiency, and describe how to calculate .
Audio Amplifier
Explain the mechanism audio amplifier in this experim ent. Understand the elements used in each step, then analyze circuit with r espect to following instructions. 1) Calculate Vout/Vin using op-amp in fig 6-17. 2) variable resistor in fig 6-17 3) Understand capacitor in fig 6-20, and analyze the circuit in terms o f high/low frequency modification.
5. Arrangements
commercial voltage : 120Vrms transformer : 120V/12V resistor : 510, 2.2k, 10k3 , 12k2, 22k3, 1, 4 7 variable resistor : 10k, 100k capacitor: 560pF, 22nF, 0.1uF, 10uF2, 22uF, 100uF,
220uF2, 2200uF, 1nF voltage regulator: LM7805(5V standard) transistor: BS170 function generator LED 1EA op-amp: LM318(OP284 alternative), LM358(AD822 alternative) diode: 1N40014EA Male headphone jack 1EA , Female headphone jack 1EA
6. Procedure
6-1. Power Supply for an Audio Amplifier
A. PSPICE simulation Conduct PSIPCE simulation for each step, and check the circuit system. Set the circuit as shown in fig 6 -6, and get the half wave rectifying ci rcuit signal. Set the circuit as shown in fig 6 -7, and get the signal that has ripple.( To get ripple clearly, you can adjust capacitor)
Connect voltage regulator, then measure the wave. Is the ripple gone? Set the circuit as shown in fig 6-11, measure the current flowing throu gh transistor and the output signal of voltage regulator. Refer fig 6-4 f or this PSIPICE circuit diagram.
fig 6-4. PSPICE circuit diagram for analyzing fig 6-11
B. actual circuit design
The Transformer 1) Apply commercial voltage(120Vrms 60Hz) to the primary side of tran sformer, inducing low voltage to the secondary side. Caution : Never short secondary side.
120 Vrms ,60Hz (US WallOutlet)
Vout
fig 6-5. Transformer circuit 2) questions - Graph Vout using oscilloscope(Check Max, Min )
- Record Max/Min value of Vout. - Observe that Vout is not an exact sinusoidal wave, and think of the reaso n. - Measure the frequency of Vout, and analyze the reason.
Adding in the Bridge Rectifier 1) Set the circuit according to the following fig 6-6, fig 6-7.
120 Vrms ,60Hz (US WallOutlet)
Vout
fig 6-6. circuit with bridge rectifier
fig 6-7. circuit that load is added
2) questions - What's the role of diode?
- What's the capaciter in fig 6-7? - Graph Vout in fig 6-6 and fig 6-7 using oscilloscope. (To oberve ripple clearly, use 100uF, 10uF capacitor instead of 2200 uF) - Discuss if these results have to do with R,C element.
Adding the Linear Voltage Regulator 1) AC/DC converter shows good quality when the ripple of Vout is sm all. In the circuit above, DC voltage contains ripple and it needs to be
reduced.
Linear Voltage Regulator
Vin
OUTPUT GND
Vout
INPUT
fig 6-8. A simple linear voltage regulator
fig 6-9. LM340T5
And that's what voltage regulator does. Add simple linear voltage regul ator(M340T5) to the circuit as shown in fig 6-10. The last number in model no., five, means 5V regulation. Linear voltage has two resistor a s shown in fig 6-8. Vin is input voltage and Vout(V_reg) is output volt age. If input voltage changes, these two resistors get modified to maint ain the same output voltage.
fig 6-10. regulator added circuit in fig 6-7
2) questions - Graph Vout(V_reg).(Get mean value of Vout and ripple effect) - Discuss the role of linear voltage regulator
Response to Changing Load 1) When V_reg is applied to load, let us change the load for a moment . Then, load current changes, and so does V_reg. At this moment, if r egulator is a good one, it senses the difference of change and recover V_reg. The amount of time to do this work is one characteristic of reg ulater when determining its quality. To check this value, set the circuit as shown in fig 6-11. In this case, IL can be calculated by using V_re g - R relationship.
Transistor(BS170) used in this experiment is one sort of N-FET, whose drain-source current varies according to the voltage of gate. Thus, if we change the voltage of gate from 0V~10V as shown circuit, I L varies. Due to this charactercistic, there is some change in Vout, which lets regulator maintain 5V.
fig 6-11. AC/DC converter with varying load
2) questions
- Graph V_reg with varying load using oscilloscope. - Discuss the behavior of linear voltage regulator with varying load.
Efficiency 1) Efficiency is the ratio of output power to input power. Set the circu it as shown in fig 6-12 to calculate efficiency. Out power can be calcul ated easily, which is power applied to 50 load. To measure input power, add 1 resistor to transformer. If we measu re I and V over 1 resistor, instantaneous power can be calculated by
using P=VI. With this value, we can get the average power by using f ormula discussed in class. This value has smaller power than commercia l voltage for the efficiency of transformer is normally 97%. With this inf ormation, we can calculate the efficiency of actual circuit.
fig 6-12. circuit for calculating efficiency
2) What's the efficiency of this circuit? Why does it have low efficienc y.
6-2. Audio Amplifier

A. PSPICE simulation Conduct PSIPICE simulation minding the following steps, and analyze circuit syst em.
(This experiment uses DC 5V Supply which is already designed in previous exper iment, so we connect output of DC 5V supply to the input node of circuit.)
Actual audio amplifier need to capture voice signal, but in PSPICE sim mulation,s use three AC sources as input signals. Set the circuit as sh own in fig 6-13, and graph each input/output signal.(In cirucit diagram, Vcc = 5V, Vee = -5V, and use power supply in earlier experiment) To express variable resistor, use R4 and R5 as shown in fig 6-13. Explain the role of the variable resistor in the circuit, and analyze it.
6-13. Audio Amplifier circuit
fig 6-14. PSPICE simmulation of Tone Controller
Add Tone Controller to Audio Amplifier in fig 6-13, conforming like fig 6-14. Let input signal have 0.1V AC Voltage, and get output signal u sing Transient Sweep mode. In this case, there is DC offset in output then, its value gradually decreases. What's the reason?
B. actual circuit design Now, let us design actual audio amp circuit with power supply in earlier experime
nt. This audio amp circuit operates connected to cassette or mp3 player. Following each step, you can attach additional functions like sound tuning besides understandin g its mechanism.
Power Supply We need to adjust this device as shown in fig 6-15. Then add LED to the circu it. LED shows on/off state, and it must be off when controlling the circuit. It also s hows on/off state of power.
fig 6-15. AC/DC Converter in experiment 5
Amplifier System Block Diagram
6-16. Amplifier block diagram
Audio Amp. Circuit 1) Connect Male headphone jack to input node, Female headphone jack
to output node. These two headphone jack have ground wire each. Co nnect it to the reference ground of circuit.
fig 6-17. Audio power amplifier circuit
6-18. AD822 power amplifier chip
6-19. OP284
The circuit diagram is shown above, and for op-amp, AD822 is used. Using variable resistor 10k, adjust the whole gain of audio amp circ uit.
Connect pin 6,7 each other, pin 5 to ground to minimize oscillating and noise . When it's done, double check if the circuit is connected properly. Especially, it's important to check the connection to ground. If there is no mistake, connect it to actual cassette or mp3 player, and see it runs properly.
2) questions - Is there any difference when the variable resistor changes? If so, how does the circuit react to its change?
Tone Control Circuit 1) With fig 6-20, analyze its mechanism. This circuit utilize the characteristic that capacitor gets short or open according to input frequency. That is, 22nF capacitor gets open in low frequency, short in high frequency. Therefore, the variable resistor co nnected with 22nF capacitor in parallel is meaningless in high frequenc y. Also, 560pF capacitor gets open in low frequency blocking signal fe edback to input, short in high frequency causing signal feedback to inp
ut. Using this principle, we can control the tone by adjusting gain of si gnal, which has both low and high frequency, with varying resistor. OP284 amp is used in tone control whose interfase is the same as that of AD822. If you're sure of your circuit. Try connecting it to act ual cassette or mp3 player. Check if it works porperly. 2) questions - Which one of variable resistors causes low frequency gain to chang e? How it behaves according to the location of variable resistor?
- Which one of variable resistors causes high frequency gain to chan ge? How it behaves according to the location of variable resistor?
22nF 5V Male Headphone jack 1uF 22k 22k 100k 22k 5V
10k + _
OP284
560pF
10uF
10k
11k
100k
11k
220uF AD822 10k + _
5V Female Headphone jack
220uF
fig 6-20. The complete audio amplifier
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7. Result Audio Amplifier Circuit Design

Power Supply for an Audio Amplifier

Record the data and answer to the questions according to each step.
Compare PSIPCE simulation and actual result, and analyze them. Compare the result of circuit and estimation, and explain those differen ces. Discuss the method of getting better efficiency on AC/DC converter.
Audio Amplifier
Answer to the questions for each procedure. In PSPICE simulation, analyze Vout/Vin wit h Bode Plot in frequency d
omain according to following steps and graph its data. 1) Referring fig 6-14, change the input voltage AC source. 2) Choose advanced db magnitude of Voltage probe as shown in fig 621 to display voltage probe. It makes it possible to analyze volatge in frequency domain. 3) Record condition as shown in fig 6-22 before setting AC Sweep in Edit Simulation Setting Menu. 4) Start Simulation from Vsin source to V
fig 6-21. probe setting for Bode Plot
fig 6-22. AC Sweep simulation setting
Graph bode plot as controlling the switch of variable resistor in questio n 2, then verify if it matches with the result of qustion 1.(We can get different bode plot according to frequency as gain changes due to varia ble resistor switching.)
Logic Circuit
Chapter 7. Basic Logic Circuit Design
1. Objective
Understand the behavior of basic logic gate, and learn boolean algebra and DeMorgan's theorem. Also, understand the principle of half/full adder with T TL chip, and measure its wave.
2. Key Words
basic logic gate boolean algebra and DeMorgan's theorem half/full adder Setting half/full adder circuit with TTL chip
3. Theory
3-1. basic logic gate
Any kinds of combinational logic gate can be designed with basic logic gate such as AND, OR, NAND, NOR, NOT and so on. The followings are descriptions of bas ic logic gates
AND gate AND gate ouputs 1 when all inputs are 1. As shown in fig 7-1, output C turns 1 when both input A and B are 1.
(a) diagram for AND gate
(b) AND gate T/F Table
fig 7-1. AND gate
AND gate's boolean expression is 3 inputs.
. Likewise,
for
OR gate OR ouputs 1 when either of inputs is 1. OR gate's boolean expression is . Its True/False table is shown in fig 8-2.
(a) diagram for OR gate
(b) OR gate T/F table
fig 7-2. OR gate
NOT gate NOT gate is also called inverter which switches its input value. Different from AND/OR gate, it has one output/input each.
(a) diagram for NOT gate
(b) NOT T/F table
fig 7-3. NOT table
NAND gate NAND gate consists of AND gate and NOT gate. Thus, boolean expression of N AND gate is .
(a) diagram for NAND gate
(b) NAND T/F table
fig 7-4. NAND gate
NOR NOR NAND OR NOT . . . 7-5 OR
(a) diagram for NOR gate
(b) NOR gate T/F table
fig 7-5. NOR gate
3-2. boolean algebra and DeMorgan's theorem

commutative law
i. A+B = B+A ii. AB = BA associative law i. A+(B+C) = (A+B)+C ii. A(BC) = (AB)C distributive law i. A(B+C) = AB+AC ii. (A+B)(C+D) = AC+AD+BC+BD calculation with 1 or 0
i. A0 = 0 ii. A+0 = A iii. A1 = A iv. A+1 = 1 calculation with single-variable and complement i. AA = A ii. A+A = A iii. AA' = 0 iv. A+A' = 1
calculation with multi-variable and complement i. A'' = A ii. A+A'B = A+B iii. A'+AB = A'+B DeMorgan's theorem i. ii.
3-3. half adder and full adder

There are half adder and full adder for binary adder circuit. Half adder can calcu late the summation of two bits, and moreover, full adder refers carry bit from half ad der. Half adder is the simplest circuit in digital circuit. This circuit has 2 input bits a nd 2 output bits. the output bits are called carry bit and sum bit each. Binary number has only 0 and 1, so we can get some principles for this. 0 + 0 = 0
0 + 1 = 0 1 + 1 = 0 : generates carry and is similar to usual summation, but generates higher order bit. This is called carry bit. Applying this principle, we can set T/F table as shown in table 7-1.
table 7-1. T/F table for half adder input output
X 0 0 1 1
Y 0 1 0 1
Cout(carry) 0 0 0 1
S(sum) 0 1 1 0
With boolean algebra equation, it can be written as follows.
= X xor Y = (X and Y') or (X' and Y)
Cout = X and Y
In other words, sum is equivalent to XOR calculation, and its output is equivalen t to AND calculation. Fig 7-6 shows this.
fig 7-6. half adder
For 2 bit summation, put half adder for each digit and send the generated carry bit to its adjacent left-side adder. Therefore, an additional block is needed to proces
s carry bit besides sum bit calculation which is called full adder. Full adder has addit ional input bit for calculating carry bit from lower order adder. For example, let us c ompute 1001 and 0101.
0 1 + 0
0 0 1
1 0 0 1 1 9 + 5
1 14
1 0
1 0
0 1
S carry bit
The lowest bit summation is 1+1=0, which generates carry bit. This is sent to t he next calculation which needs full adder. In this case, 1+0+0=1, so no more carry bit is generated, that is, the next carry bit is '0'. True/False table for full adder is shown in table 7-2.
table 7-2. T/F table of full adder input output
Cin(input carry bit) 0 0 0 0 1 1
X 0 0 1 1 0 0
Y 0 1 0 1 0 1
Cout(output carry bit) 0 0 0 1 0 1
S(sum) 0 1 1 0 1 0
1 1
1 1
0 1
1 1
0 1
Using boolean algebra equation,
= X xor Y xor Cin = (X and Y' and Cin) or (X' and Y and Cin') or (X' and Y' and Cin) or (X and Y and Cin)
Cout
= (X and Y) or (X and Cin) or (Y and Cin)
Fig 7-7 shows the diagram for this equation. Fig 7-7. full adder
4. Pre-report Basic Logic Circuit Design

Explain how to design logic gates with transistors.
Design XOR gate with 2 input AND, OR, NAND, NOR, NOT gates. Describe the followings : TTL(Transistor Transistor Logic), ECL(Emitter Coupled Logic), MOS(Metal Oxide Semiconductor), CMOS(Complement ary Metal Oxide Semiconductor) Using Karnaugh map, express boolean algebra equation from T/F table.
Build boolean algebra equation of full/half adder.
5. Arrangements
LED 3EA power supply 5Vdc 1EA resistor 47 1EA, 330 3EA 74LS00, 74LS02, 74LS32, 74LS08, 74LS04 1EA toggle switch 2EA
oscilloscope
6. Procedure
Set AND gate circuit as shown in fig 7 -8. fig 7-8. AND gate experiment.
Fill out the following table from the experiment. table 7-3. AND gate experiment result A 0 0 1 1 B 0 1 0 1 AB
Set OR gate circuit as shown in fig 7 -9. fig 7-9. OR gate experiment
Fill out the following table from the experiment. 7-4. OR gate experiment result A 0 0 1 1 B 0 1 0 1 A+B
Set NOT gate circuit as shown in fig 7 -10. fig 7-10. NOT gate experiment
Fill out the following table from the experiment. table 7-5. NOT gate experiment result
0 1
Set NAND gate circuit as shown in fig 7 -11.
fig 7-11. NAND gate experiment
Fill out the following table from the experiment. table 7-6. NAND gate experiment result A 0 0 1 1 B 0 1 0 1
Set NOR gate circuit as shown in fig 7 -12.
fig 7-12. NOR gate experiment
Fill out the following table from the experiment. table 7-7. NOR gate experiment result A 0 0 1 1 B 0 1 0 1
Design NOT, AND, OR, NOR gate only with NAND gate, and verify it with oscilloscope. Then, compare this with single gate. Design NOT, AND, OR, NOR gate only with NOR gate, and verify it with oscilloscope. Then. compare this with single gate. Set half adder circuit as shown in fig 7-6, then record the result on ta ble 7-1. Set full adder circuit as shown in fig 7 -7, then record the result on ta ble 7-2.
7. Result Basic Logic Circuit Design

Survey power consumption and switching frequency of many kinds of IC (TTL, CMOS, etc.) When connecting many gates, examine its current and amplitude for th
e case of 1 or 0. Explain the reason why NAND, NOR gate is more commonly used than AND, OR gate. What is fan-in/fan-out of gate? Design full adder with two half adders and one OR gate.
Chapter 8. Combination Logic Circuit Design
1. Objective
Understand the mechanism of typical combination circuit such as multiplexe r/demultiplexer, encoder/decoder. Conducting verilog simulation, and verify its result with FPGA Kit. Also, understand the mechanism of 7-segment controll
er used to display number, and conduct verilog simulation, verify it.
2. Key points
the structure of multiplexer/demultiplexer the structure of encoder/decoder verilog simulation for multiplexer/demultiplexer, encoder/decoder and F PGA Kit experiment the structure of 7-segment controller
verilog simulation for 7-segment controller, and FPGA Kit experiment.
3. Theory
3-1. multiplexer/demultiplexer
multiplexing is the device that transmits many information through a small num ber of channel/line. Digital multiplexer is one of the combination circuits that selects one among man y inputs, and connects it to output. A particular input is chosen according to select
ed value. Generally, multiplexer has
input values and n selecting values. And the
multiplexer choose one input value according to the combination of n selecting valu es. Fig 8-1 shows 41 multiplexer. and four input values( to ) become one of i
nput for AND gate. Selecting values are used for selecting particular gate, which is s et depending on the bit combination of selecting values. For this circuit, the multiplexer has 4(= ) input values, so it needs two selectin g values. Therefore, 41 multiplexer which has 6 different input takes (=64) cases
of different values, and it's difficult to follow usual combination circuit design metho d. Because we choose one case among many different input values, we can use AND gate for filtering which is called switching process. If to input =10, AND gate connected . The other th
has two inputs of S set to "1", and the other input of
ree AND gates output "0" because either of their inputs is "0". Consequently, OR gate output is equal to . That is, OR gate is called data selector since it conveys
input binary information to output-side.
S0 S1 0 0 1 1 0 1 0 1
Y I0 I1 I2 I3 (a) T/F table (b) block diagram
fig 8-1. multiplexer fig 8-2. diagram for multiplexer
Demultiplexer, opposite to multiplexer, is the data dividing circuit that connects one input to multiple outputs. As depicted in fig 8-3, similar to multiplexer, it has s electing node. If it has n selecting nodes, we can choose one among es. output valu
Output Input S0 S1 D0 D1 D2 D3
I I I I
0 0 1 1
0 1 0 1
I 0 0 0
0 I 0 0
0 0 I 0
0 0 0 I
(a) T/F table
(b) block diagram
fig 8-3. Demultiplexer
fig 8-4. diagram for demultiplexer
As for 14 demultiplexer, it has 4 output values which needs 2 selecting nodes, 3 input variables. Like previous multiplexer design, it's easy to design the circuit co nceptually rather than to follow usual combination circuit design method. 14 demul tiplexer is not so different from multiplexer, so we can design with AND gate as sho wn in fig 8-4. If we verify this circuit letting d input signal I comes out in output node . =10, 2nd AND gate is enabled an
Fig 8-5 describes the behavior of this circuit in verilog HDL based on 41 mul tiplexer, 14 demultiplexer T/F table.
fig 8-5. verilog HDL source for 4x1 MUX 1x4 DEMUX
module MUX_4_TO_1 (I0, input input [1:0] output reg
I1, I2, I3, Y, S); I0, I1, I2, I3; S; Y; Y;
always @ (I0 or I1 or I2 or I3 or S) begin case (S) 2'b00: Y=I0; 2'b01: Y=I1; 2'b10: Y=I2; default: Y=I3; endcase end endmodule
module DEMUX_1_TO_4 (I, S, D0, D1, D2, D3); input I; input [1:0] S; output D0, D1, D2, D3; reg D0, D1, D2, D3; always @ (I or S) begin case (S) 2'b00: begin
3-2. decoder and encoder

Discrete data is expressed as binary code in digital system. n-bit binary code ca n express different information. Decoder is the combination circuit that converts different information. If it doesn't use n-bit decoded inform .
n-bit binary code into
ation or has don't-care-combination, its output gets smaller than
Decoder creates m( ) minimum terms for n input variables, and it's called n m decoder. Its T/F table is shown in table 8-1. Table 8-1 shows relationship between input and output variables of 38 decoder
, and we can get the following functions.
D0 = X'Y'Z' D2 = X'YZ' D4 = XY'Z' D6 = XYZ'
D1 = X'Y'Z D3 = X'YZ D5 = XY'Z D7 = XYZ
table 8-1. T/F table for 38 decoder
input X 0 0 0 0 Y 0 0 1 1 Z 0 1 0 1 D 0 D1 D2 1 0 0 0 0 1 0 0 0 0 1 0
output D3 0 0 0 1 D4 D 5 0 0 0 0 0 0 0 0 D6 D7 0 0 0 0 0 0 0 0
1 1 1 1
0 0 1 1
0 1 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
38 decoder output function value is solely "1" for each case, so it can't be m ore minimized. Fig 8-6 depicts 38 decoder circuit, whose 3 inputs create 8 output s, and each outputs indicate either of 3-variable-input minimum terms. 3 NOT gates output complement of input. 8 AND gates shows either of minimum terms.
fig 8-6. 38 decoder Encoder is the combination circuit that is opposite to decoder. Encoder creates m( ) input variables and n output values, and it's called mn encoder. For example, as for 83 encoder, it needs 8 input variables and 3 outputs to c reate binary code matching its input. T/F table for this circuit is shown in table 8-2 .
table 8-2. 83 T/F table for encoder Input D0 D1 D2 D3 D4 D5 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 D 6 D7 0 0 0 0 0 0 0 0 X 0 0 0 0 Output Y 0 0 1 1 Z 0 1 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
1 1 1 1
0 0 1 1
0 1 0 1
Encoder consists of OR gates, and its input is determined by this table. Output X has "1" if either of input 4, 5, 6, 7 is "1". Output Y has "1" if either of input 2 , 3, 6, 7 is "1". In same manner, output Z has "1" if either of input 1, 3, 5, 7 is "
1". Note that isn't connected to any OR gate because it has to be "0" output
value for all cases. To sum up, output function can be expressed as follows.
X = Y = Z =
+ + +
+ + +
+ + +
Fig 8-7 depicts 83 encoder circuit. we assume that this encoder has only one input which "1" is available. The circuit has 8 inputs which can represent (=256)
combination. But only 8 values are meaningful, the others are don't-care-values. In t his case, we assumed the actual , input is only one However, general IC(Integrated Circuit) encoder is priority encoder.
fig 8-7. 83 encoder
This encoder interprets priority input first among multiple inputs. Based on table 8-3, for example, when both utput is "101" because and are become "1", the o
has higher priority. If we make T/F table of this priority
encoder, we can use don't-care-value. Fig 8-8 describes verilog HDL expression of 83 priority encoder.
table 8-3. T/F table of 83 priority encoder
Input D0 D1 1 0 1 D2 D 3 D4 D 5 D6 D 7 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 0
Output Y 0 0 1 1 Z 0 1 0 1
0 1
0 0 1
0 0 0 1
1 1 1 1
0 0 1 1
0 1 0 1
fig 8-8. verilog HDL expression of 83 priority encoder
module PRIORITY_ENCODER_8_TO_3 (D, XYZ); input [0:7] D; output [2:0] XYZ; reg [2:0] XYZ; always @ (D) begin if (D[7]==1'b1) XYZ=3'b111; else if (D[6]==1'b1) XYZ=3'b110; else if (D[5]==1'b1) XYZ=3'b101; else if (D[4]==1'b1) XYZ=3'b100; else if (D[3]==1'b1) XYZ=3'b011; else if (D[2]==1'b1) XYZ=3'b010; else if (D[1]==1'b1) XYZ=3'b001; else if (D[0]==1'b1) XYZ=3'b000; end endmodule
3-3. 7-segment controller

7-segment is widely used to express number in digital circuit. As you already kn ow, the combination of 7 LED displays number. Each segment is named a, b, c, d, e, f, g, and fig 8-9 shows its each location.
fig 8-9. 7-segment
7-segment has two types; common cathode and common anode which depends o n their common polarities. Fig 8-10, and fig 8-11 depicts their internal circuit diagra ms.
fig 8-10. common anode
fig 8-11. common cathode
Also, their controller differs depending on those types. The controller is usually called 7-segment display decoder whose main IC is 7446/7447. In this experiment, le t us design the decoder which interprets binary number to decimal number.
To display number with 7-segment, we need to design ON/OFF behavior of LE D. For instance, b and c have to be on to display 1 while the others are off. 7-seg ment controller lets this happen. First binary number has to be decoded to match 7 -segment. Table 8-4 shows appropriate input/output values to express number from 0 to 9. Let's set 4-bit input. When each segment is "1" output value, LED is on, of co urse, off for "0". 4 bits can express 16 different numbers, which is hexadecimal. How ever, we regret more than 10 because people commonly use decimal number.
table 8-4. decoding value for each input Input 7-segment output
0 0 0 0 0
1 0 2 0 3 0 4 0 1 1 0 1 0 0 0 1
0 5 0 6 0 7 0
0 1 0 1 1 0 1 1
1 0 0 1 1 1 1 1
0 1 1 1 0 0 0 0
8 1 9 1 0 0 0 0 0 1
We can use IC 7448 to implement this table. Using Karnaugh map in this case c an be quite complicate because input has 4 bits. But under behavioral level, we can design this circuit with simple input/output control with HDL because CAD tool com
piles the code to gate level automatically.
4. Pre-report Combination Logic Circuit Design

Survey the following multiplexer - 21 multiplexer - 41 multiplexer
Compare the differences between encoder and multiplexer. Compare the differences between decoder and multiplexer. Compare the differences between decoder and encoder. Survey other types of decoder. Survey either of 7446, 7447, 7448 elements Express 7-segment controller using verilog HDL.
5. Arrangements
PC 1EA MAX+PLUS II Digital Circuit Training Kit 1EA
6. Procedure
Type 41 MUX verilog HDL code in fig 8 -5 on text editor and name it Project.
Set Assign > Device to EPF10K10QC208-3 of FLEX10K Family. Then revise code and run compiler until it has no error. Select MAX+PLUS II > Waveform Editor, then create input pattern. Select MAX+PLUS II > Simulator, and verify its result using Waveform Editor. If it show different result, find the reason and solve the proble m. Select MAX+PLUS II > Floorplan Editor, and set input/output pin to F PGA I/O as instructed in pre-report. Then start compiling again. If err ors come out, revise and repeat this procedure until no error.
With MAX+PLUS II > Timing Analyzer, measure the time delay betwee n input and output, then record it. Run MAX+PLUS II > Programmer, and check if Configure is activated. If it is inactive, select Option > Hardware Setup, and set Hardware Ty pe to ByteBlaster. Connect ByteBlaster Port of Digital Circuit Design Training Kit and Pa rallel Port of PC using cable. Set Mode select switch to "XX0011" which is ByteBlaster Mode. Set I/O controller switch to be used
Apply power to Digital Circuit Design Training Kit Select Programmer > Configure, and download the designed circuit to Digital Circuit Design Training Kit. Apply the input of True/False table in fig 8-1(a), and verify if its outp ut is equal to that of the table. Repeat step ~ for 1x4 DEMUX verilog HDL in fig 8 -5. Apply the input of True/False table in fig 8 -3(a), and verify if its outp ut is equal to that of the table. Repeat step ~ for 83 priority encoder verilog HDL in fig 8 -5.
Apply the input in table 8-3, and verify if its output is equal to that of the table. Repeat step ~ for segment controller verilog HDL code, and get t he outputs for inputs in table 8-5. table 8-5 result of 7-segment decoder Input A 0 B 1 C 0 D 1 a b c Output d e f g
1 0 1 0
0 1 1 0
0 1 1 0
0 1 1 1
7. Report Combination Logic Circuit Design

Using 21 multiplexer and 41 multiplexer, design 81 multiplexer a nd verify its behavior Design the function which shows a+c'd+bd'+b'd+b'ce behavior with only
one multiplexer. Find the maximum delay route of 7-segment decoder, then calculate th e maximum operating frequency when this circuit is run by clock. Think of the method of displaying hexadecimal number(i.e. A to D) Get its True/False table.
Chapter 9. Arithmetic Circuit Design
1. Objective
Understand the expression of negative binary number and 4-bit adder/subt racter with verilog simulation and FPGA Kit. Based on what we've learned bef ore, make ALU(Arithmetic Logic Unit) verilog code capable of 4-bit logic and arithmetic calculation. Then verify this with simulation and FPGA Kit.
2. Key Points
expression of negative binary number mechanism of 4-bit adder/subtracter verilog simulation & FPGA Kit experiment of 4-bit adder/subtracter. structure of 4-bit ALU 4-bit ALU verilog simulation & FPGA Kit experiment
3. Theory
3-1. 4-bit adder/subtracter
The simplest adder is composed of half adder and full adder as shown in fig 9-1 .
fig 9-1. 4-bit adder
But subtracter is exceptional. If we design the circuit which subtracts number jus
t like we do, it needs extra circuit, which is undesirable. To solve this problem, add er/subtracter in digital circuit uses specific number. This is called two's complement number. With this number, we can implement bo th adder and subtracter in one circuit. Table 9-1 shows its number system for 4 bit s.
table 9-1. two's complement number for 4 bits number 2's complement number 2's complement
0 1 2 3 4 5 6
0000 0001 0010 0011 0100 0101 0110
-8 -7 -6 -5 -4 -3 -2
1000 1001 1010 1011 1100 1101 1110
0111
-1
1111
In case of positive number, we can simply change it to binary. But for negative number, we need a different method to express this. In other words, we change the number into two's complement and add 1, when there is a switch from positive to n egative or vice versa. For example, 0011 becomes 1100 for two's complement, and 1 101 with plus 1. As a result, it finally represents -3. Switching negative to positive i s the same way.
From positive to negative 3 binary 0011 1100 1101 add 1 -3
2's complement
In this case, positive represents one number less than negative; positive is 1 to 7, negative -1 to -8. It's because of "0" which has no negative value. That is, 0000 becomes 1111 for two's complement, and 0000 again when "1" is added. The reason of using two's complement is to calculate number in digital circuit. L
et us see why this method makes it simple to calculate. The followings are three cases of calculating numbers.
positive num + negative num 4 + 3 + 0100 0011
0111
It's the same as usual manner
negative num + negative num -4 + (-3) + 1100 1101
-7
1 1001
Except for the highest bit, it represents two's complement of -7.
positive num - positive num 4 - 3 0100 - 0011 = 0100 + 1101
1 0001
As for subtraction, we can simply add operand after taking minus sign. Likewise,
take plus sign when negative operand is subtracted. Then, we can get the right res ult. As we've seen before, addition is not different from that of binary, and so does subtraction when we change the sign of numbers. Using two's complement, we can d esign the circuit which can add both positive and negative numbers. Actual subtracte r uses borrow instead of carry. However, in this case, it needs double size of circuit . But with two's complement, it needs only adder and NOT gate. By the way, there is a problem with this method. If 7+7 is calculated , which ha s to be 14, it becomes -2.
7 + 7
0111 + 0111
14
1110 -2
In two's complement system, 7 is the largest value in 4-bit number. But addition can generate larger value than that. The same thing could happen for negative num ber. This state is called overflow. To prevent overflow state, we need to check the
carries of the highest 2 bits. If they are equal, it means overflow. If not, normal stat e. That is, we can prevent overflow by checking these two values. The following figure shows full adder which is capable of 4-bit adder/subtracter. Basic method is the same as previous adder. Not only that, two's complement can b e calculated in input using multiplexer in case of subtraction. But "1" has to be
added to make it negative number, which can be implemented by one full adder. It g enerates carry when changes sign of number. Identification of add/subtract can be im plemented by the input of
. If it is "1", it works as a subtracter, "0" as an adder. This input is used to selecting value of multiplexer and carry bit of first full adder as well. If it is "0", first full adder works as the half adder that input is put to. Otherwise, if
it is "1", carry bit is put to the full adder, and multiplexer inputs the reverse value of . which results in subtraction. Also, to check overflow, the highest two bits is
connected to XOR gate. fig 9-2. 4-bit adder/subtracter
fig 9-3. verilog HDL code of 4-bit adder/subtracter
module ADD_SUB(SEL, A, B, S, OVERFLOW); parameter DSIZE=4; input input output output reg reg reg reg always @ (A) AV=A; always @ (SEL of B) begin if (SEL==1'b1) begin CARRY = 1'b1; BV=~B; end else begin [DSIZE-1:0] [DSIZE-1:0] [DSIZE-1:0] [DSIZE-1:0] SEL; A, B; S; OVERFLOW; S, i; OVERFLOW; SUM, AV, BV, C; CARRY;
3-2. 4-bit ALU

All kinds of current computer operate based on CPU. In this experiment, we'll i mplement 4-bit ALU(Arithmetic Logic Unit) to help understand the mechanism of co mputer. To begin with, ALU has two types of calculation; arithmetic and logic
logical operation As shown in fig 9-1, think of logic circuit which has one output F with 2 logic i nputs(A and B). There are 16 cases of possible results with three basic logic operato
r; AND, OR, and NOT.
fig 9-4. logic circuit
If we put NOT gate to either of two inputs, it can genterate four different result s; . If it is combined with AND, OR, NOT gates, it becomes . Similarily, if one logic value and the complement of that is combined with AND, OR gates, it generates four logic values; AND, OR, NOT gates, it generates two more logic values; . All possible cases are shown in table 9-2. . Lastly, with ,
table 9-2. 16 possible case of 2-input, 1-output logic circuit number 1 2 3 4 logic value
5 6 7 8 9 10 11
12 13 14 15 16
structure of 4-bit ALU Fig 10-5 depicts the input/output of 4-bit ALU. As shown in figure, it has two 4-bit inputs(A( , , , ), B( , , , )), 4-bit input controller S, logic/arith ), carry output( ), and identifier of
metic operation controller M, carry input( .
fig 9-5. structure of 4-bit ALU
Table 10-3 shows the operation depending on controlling signals.
9-3. operation depending on controlling signals
operating signal S3 0 0 0 0 0 S2 0 0 0 0 1 S1 0 0 1 1 0 S0 0 1 0 1 0
logic operation (M=1)
arithmetic operation (M=0, CIN=0)
Logical 0
minus 1 plus
0 0 0 1 1 1 1
1 1 1 0 0 0 0
0 1 1 0 0 1 1
1 0 1 0 1 0 1
plus minus minus 1 plus plus plus minus 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
Logical 1
plus plus plus minus 1
Table 9-3 is case of operation that assumes there is no carry input(
=0). If c
arry input exists, we need to take it into account. Therefore, to calculate this case,
'0' has to be inserted in carry input(
) first. If controlling signal M is '1', it exec
utes logic operation, and is '0', executes arithmetic operation. For example, if M=1 a nd operating signal is "1101", it executes logic operation of " to identifier of . , and ouputs "1
4-bit ALU in this experiment can also implement 8-bit, 12-bit, 16-bit, ALU by combining multiple ALU simply using and .
4. Pre-report Arithmetic Circuit Design

Survey the other types of number system. (exp : sign and magnitude, ones complement) Explain why the condition of overflow can be determined by the highes
t two carry bits in 4-bit adder/subtracter. Fig 9-6 is verilog HDL code of expressing several arithmetic/logic oper ation. Referring this, design the code of 4-bit ALU used in this experi ment under behavioral level.. Allocate 4-bit ALU I/O pin to I/O of FPGA so that input/output and controlling signal may be easily observed. Then record the appropriate I/O pin number. Choose a one ALU/CPU and describe behavior according to its instru c tions.
fig 9-6. verilog HDL sample code
module ALU(alu_out, data_a, data_b, enable, opcode); input [2:0] opcode; input [3:0] data_a, data_b; input enable; output alu_out; reg [3:0] alu_reg; assign alu_out=(enable==1) ? alu_reg : 4'bz; always@(opcode or data_a or data_b) case(opcode) 3'b001 : alu_reg = data_a | data_b; 3'b010 : alu_reg = data_a ^ data_b; 3'b100 : alu_reg = ~data_b; default : alu_reg = 4'b0; endcase endmodule
5. Arrangements
PC 1EA MAX+PLUS II
Digital Circuit Training Kit 1EA
6. Procedure
Type 4-bit adder/subtracter verilog HDL code in fig 9-3 on text edito r and name it Project. Set Assign > Device to EPF10K10QC208-3 of FLEX10K Family. Then revise code and run compiler until it has no error. Select MAX+PLUS II > Waveform Editor, then create input pattern.
Select MAX+PLUS II > Simulator, and verify its result using Waveform Editor. If it show different result, find the reason and solve the proble m. Select MAX+PLUS II > Floorplan Editor, and set input/output pin to F PGA I/O as instructed in pre-report. Then start compiling again. If err ors come out, revise and repeat this procedure until no error. With MAX+PLUS II > Timing Analyzer, measure the time delay betwee n input and output, then record it.
Run MAX+PLUS II > Programmer, and check if Configure is activated. If it is inactive, select Option > Hardware Setup, and set Hardware Ty pe to ByteBlaster. Connect ByteBlaster Port of Digital Circuit Design Training Kit and Pa rallel Port of PC using cable. Set Mode select switch to "XX0011" which is ByteBlaster Mode. Set I/O controller switch to be used Apply power to Digital Circuit Design Training Kit Select Programmer > Configure, and download the designed circuit to
Digital Circuit Design Training Kit. Apply the inputs of table 9-4, get their outputs
table 9-4. T/F table of 4-bit adder/subtracter Input Ai 3 2 Bi 4 -3 Add/Subtract + S3 S2 Output S1 S0 Overflow
-4 7 -2
2 4 -3
+ + -
Type 4-bit ALU verilog HDL code of pre-report on text editor and na me it Project. Then, repeat step ~. Apply M=0, CIN=0, S=0110, A=B=0011, then record the values of , COUT, F node.
Apply M=1, CIN=0, and observe results with operating signal(S0S3) a s instructed in table 10-5, and complete blanks. Apply M=0, CIN=0, and observe results with operating signal(S0S3), arbitrary inputs(A0A3 / B0B3). Then fill out table 10-6.
table 9-5. result of 4-bit ALU A= operating signal B= B= A=
S3 0 0 0 0 0 0
S2 0 0 0 0 1 1
S1 0 0 1 1 0 0
S0 0 1 0 1 0 1
F3
F2
F1
F0
F3
F2
F1
F0
0 0 1 1 1 1 1
1 1 0 0 0 0 1
1 1 0 0 1 1 0
0 1 0 1 0 1 0
1 1 1
1 1 1
0 1 1
1 0 1
table 9-6. result of 4-bit ALU
A= operating signal B= S3 0 0 0 0 S2 0 0 0 0 S1 0 0 1 1 S0 0 1 0 1 F3 F2 F1 F0
A= B= F3 F2 F1 F0
0 0 0 0 1 1 1
1 1 1 1 0 0 0
0 0 1 1 0 0 1
0 1 0 1 0 1 0
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
7. Report Arithmetic Circuit Design

Survey the strength/weackness of carry look ahead method and compar e it with the circuit above. Find the maximum delay route of 4 -bit adder/subtracter, then calculate the maximum operating frequency when this circuit is run by clock. Survey other types of adder, then find the fastest one for 32-bit addin g operation. If you have troubled in compiling because of errors after setting input/
output pin to FPGA I/O with MAX+PLUS II > Floorplan Editor, discus s possible reasons. Discuss the reason of time delay(time from input to output) measured b y MAX+PLUS II > Timing Analyzer. If we use clock to design the circ uit, find out the maximum operating frequency, and explain why. Design 16-bit ALU with four 4-bit ALU and discuss its time delay me asured by MAX+PLUS II > Timing Analyzer
Chapter 10. Flip-flop and Counter Design
1. Objective
To understand the operating principle of various kinds of flip-flops, and design counters based on that knowledge.
2. Key Points
Understanding the operating principle of flip-flops
Understanding the operating principle of shift-registers which use flip-flops Understanding the operating principle of various counters Executing the verilog simulations of flip-flops and counters
3. Theory
3-1. Latch/Flip-Flop
S-R Latch Latch has two values, 1 and 0, for the output. In a TTL circuit, 1 represents +5V,
while 0 is assigned to 0V. Latch output has two voltage values and two stable conditions such as 0 and 1, therefore it is called a bi-stable circuit. Latch is the most commonly utilized circuit in many digital circuit processes, which include memorizing binary information, frequency partition, and counter manufacture. The structure of a simple S-R latch using two NAND gates is shown in figure 10-1(a). The input of the two NAND gates are S and R, outputs Q and . If S and R is both connected to 0V, and Q is +5V, the 7inputs of the NAND gate B are both +5V, letting be 0. Therefore, the inputs of NAND gate B remain as 5V, latch holds its value in a stable condition. If Q is 0V, there is another stable condition where is +5V. Q and always
have opposite values. To change the stable condition to another stable condition, +5V can be applied to S or R inputs. When Q=0V, =+5V, and +5V is applied to R input, +5V on R input changes the output of NAND gate B to be +5V. Therefore, the NAND gate A has +5V applied to both inputs. R input goes back to +5V, and this new stable condition will be maintained. Q Q Q
Q Q When +5V is applied to S input, Q becomes +5V. Here, 0 is applied to S and 1 to Q, we say that latch has been 'set'. When +5V is applied to R input, Q becom es 0 and we say the latch has been 'reset'. Therefore, S input of the latch is called the 'set' input, the R input is called 'reset' input. Q is the base output, and alwa
ys have the opposite value of Q. Q
(a) Realization using NAND gates

S R Q
(b) Symbol
0 0 1 1
0 1 0 1
Hold 0 1 Unstable
(c) Truth Table Figure 10-1. S-R latch
The circuit symbol for a basic S-R latch is shown in Figure 10-1(b), the truth t
Appendix D. verilog HDL 580 module SR_LATCH_nand(S, R, Q, QN); Appendix C. Internet Website regarding Digital Circuit 580
input S, R; output Q, QN;
wire w1, w2
not not1 (w1, S); not not2 (w2, R); Appendix B. MAX+plus User Guide 580
nand nand1 (Q, w1, QN); nand nand2 (QN, w2, able is in Figure 10-1(c). TheQ); first input on the truth table(S=R=1) is not used bec
ause it makes Q and both 1, making it unpredictable when S or R input has 0 appl
endmodule
ied to it afterwards. The verilog code of S-R latch is shown in Figure 10-2(a). Q
Figure 10-2. verilog HDL code of S-R latch
J-K Flip-flop The problem of S-R latch is that it is unstable when S=R=1. However, if the ou tput feedback of Q and is used as in Figure 10-3, and applied to S and R inputs with the external inputs through the AND gates, the S and R can never both be 1 at the same time. Then, a 'Toggle' occurs when J=K=1, and Q changes from 0 to 1 , and 1 to 0 repeatedly. This flip-flop is called J-K Flip-flop. Figure 10-3, 10-4 s hows circuit map, truth table and verilog HDL code for this flip-flop.
J(t) 0 0 0 0
K(t) 0 0 1 1
Q(t) 0 1 0 1 0 1 0 0
Q(t+) Hold
Reset
module JK_FF(J, K, clk, Q, QN); Chapter 11. FSM(Finite State Machine) Design 584 input J, K, clk; output Q, QN; reg Q, QN; always@(J or K or clk) 1 1 1 1 0 0 1 1 begin 0 1 Set Appendix B. MAX+plus User Guide 584
1 1 if ((J == 1'b0) && (K == 1'b1) && (clk == 1'b1)) 0 1 1'b0; Toggle Q <=
else 1 if ((J0== 1'b1) && (K == 1'b0) && (clk == 1'b1)) <= 1'b1; (a) Circuit Q map
(b) Truth table
else if ((J == 1'b1) && (K == 1'b1) && (clk == 1'b1)) Q <=Figure QN; 10-3. J-K Flip-flop else Q <= Q; QN <= ~Q; end endmodule
Figure 10-4. verilog HDL code of J-K Flip-flop
Master/Slave J-K Flip-flop J-K Flip-flop has a problem when it is kept in Toggle mode, the output keeps changing unless J or K is 0. Master/Slave J-K filp-flop is used to solve this problem .
Figure 10-5 shows two J-K Flip-flops connected together. Master part is on the input side, creating outputs P and when it receives the input when clk changes to 1. Slave part is on the output side and creates outputs based on inputs P and wh en clk changes from 1 to 0. P and goes into Slave flip-flop's inputs when clock ch
anges from 1 to 0, and the output Q and cannot go in to the inputs of the Master flip-flop's inputs until the clock changes from 0 to 1 again, therefore it does not ha ve the problem of always being toggled like in J-K flip-flop. P P P Q
Figure 10-5. Circuit map for
J-K Master/Slave Flip-Flop
Edge Triggered D Flip-flop D Flip-flop, unlike J-K Master/Slave flip-flop, receives input when clk changes f rom 0 to 1, or 1 to 0, not when the clk is 1. The former is called positive edge tri
ggered, the latter negative edge triggered. D flip-flop's symbol and waveform is show n in Figure 10-6. D Flip-flop has the characteristics of inputs being delivered straigh t to the output. Positive edge triggered D Flip-flop's verilog HDL code is sho in Figure 10-7.
(a) Symbol
module D_FF(Q, D, Clk);
input D, Clk; output Q;
reg Q; (b) Waveform of edge-triggered D Flip-flop always@(posedge Clk) Q=D; endmodule
Figure 10-6. Positive edge-triggered D Flip-flop
Figure 10-7. Verilog HDL code of the positive edge-triggered D Flip-flop
3-2. Shift Register

Shift Register
Shift register saves binary information in blocks that is used to save and send da ta of computer systems. In the register, one bit of data is saved in one flip-flop. Shi ft register operates to shift the binary information sequentially to the adjacent flip-flo ps when the clock input is received, and to let the output come out at an appropria te time. Serial shift register lets information be shifted one at a time to the adjacent flip-flop.
module SHIFT_REG_d(D, Clk, Q);Chapter 11. FSM(Finite State Machine) Design 595
input D, Clk; Appendix B. MAX+plus User Guide 595 output Q;
wire D1, D2, D3, D4, D5; wire Q1, Q2, Q3, Q4, Q5;
Figure 10-8. Circuit map for 6-bit serial shift register
D_FF D_FF1(Q1, D, Clk); D_FF D_FF2(Q2, Q1, Clk); D_FF D_FF3(Q3, Q2, Clk); D_FF D_FF4(Q4, Q3, Clk); D_FF D_FF5(Q5, Q4, Clk); D_FF D_FF6(Q, Q5, Clk);
endmodule
Figure 10-9. Verilog HDL code for 6-it serial shift register
Figure 10-9 shows a 6-bit serial shift register, structured with positive edge-trig gered d flip-flop. It can save 6-bit binary information and takes one clock period to enter one bit of information, therefore 6 clock period is needed to fill this serial shift register. Figure 10-9 used positive edge-triggered flip-flop to express serial shift re gister in verilog HDL code.
Generally n flip-flop is used to save n bit of information, and n bit of clock peri od of time is needed for each sequence in the shifting of information in the register,
to save n bit of information.
Bi-directional Shift Register Shift register normally receives input in one side, and create outputs on the othe r side. To receive and create inputs and outputs on both sides, Mux can be used to decide whether the input from the left side or the right side is saved. Also, if the clock input is maintained at 0, the value of shift register can be held. Figure 10-10
is designed to accomplish this. S1 and S2 is the signal to set modes. Figure 10-11 is the truth table for S1 and S2. As the truth table shows when S1 and S2 are bot h zero, AND gate is connected to ensure there is no clock input, and to set Shift L eft mode, Mux signals can be selected as in the figure. Figure 10-10. Circuit map for 4-bit bi-directional shift register
S1 0 0 S2 0 1 Mode Hold Shift Right
1 1
0 1
Shift Left Now Allowed
Figure 10-11. Truth table of 4-bit bi-directional shift register
3-3. Counter
Johnson counter Like in Figure 10-12, by using serial shift registers, the outputs of the last flip-fl op can be cross-connected to the inputs of the first flip-flop, J and K, to design shi
ft-counter form of Johnson counter. The n flipflops connected can be the counters of mod-2N. The connection can be modified to create mod-[2n-1] counter. For examp le, 4 flip-flops connected create a mod-8 Johnson counter. These counters can some times be at an illegal state with some inputs, constantly repeating the same outputs, so caution is required to avoid these states.
mod-8 Johnson counter Figure 10-12 shows four flip-flops connected together to create mod-8 shift cou nter. Output D should be connected to flip-flop A's input K, and to input J. The s
ix states in which the counter progresses is shown in Figure 10-12(b). This counter only goes through 8 states in the 16 possible states. States like 0101, and 1010 are illegal states and therefore not included in the calculation sequence. If these states occur, counter repeats only 0101 and 1010 as an output. For this counter to perfor m correctly, counter has to be forced in to legal state when illegal state is found. A ppropriate utilization of preset gate can change the counter's output from 0101(illegal state) to 0111(legal state). Figure 10-13 writes the verilog HDL code for mod-8 shi ft counter circuit which has the preset function to prevent any illegal states from ha ppening.
(a) Circuit map
D 0 0 0 0 1 1
C 0 0 1 1 1 1
B 0 1 1 1 1 0
A 1 1 1 1 0 0
State 1 2 3 4 5 6
1 1 0
0 0 0
0 0 0
0 0 0
7 8 1
(b) Truth table
Figure 10-12. mod-8 shift counter
module John_CNT_Mod_8(Clk, A, B, C, D, AN, BN, CN, DN);
input Clk; output A, B, C, D, AN, BN, CN, DN;
JK_FF JK_FF1(DN, D, Clk, A, AN); JK_FF JK_FF2(A, AN, Clk, B, BN); JK_FF JK_FF3(B, BN, Clk, C, CN); JK_FF JK_FF4(C, CN, Clk, D, DN);
begin if ((B==1'b1) && (C==1'b0) && (D==1'b1)) begin A <= 1'b1; AN <= 1'b0; end
Figure 10-13. Verilog HDL code for 8-bit mod-8 shift counter
mod-7 Johnson Counter mod-7 Johnson Counter can be designed by just changing one connection from t he mod-8 counter in Figue 10-12(a). Like in Figure 10-14(a), it is easily accomplish ed by changing the input K of Flip-flop A from D to C. Filp-flop A will be reset on e clock period quicker this way, and will correspond to the truth table in Figure 1014(b).
Mod-7 shift counter will progress from illegal state 1111 to legal state 1110, fro m 1010 to 0101 and 0011. In other words, this counter cannot maintain an illegal st ate. Therefore, unlike mod-8 counter, it does need preset gate to coerce it out of il
legal state, and has the merit of maintaining legal state at all times. (a) Circuit map
D 0 0 0 0 1 1
C 0 0 0 1 1 1
B 0 0 1 1 1 0
A 0 1 1 1 0 0
State 1 2 3 4 5 6
1 0
0 0
0 0
0 0
7 1
(b) Truth table
Figure 10-14. mod-7 shift counter Decoding Johnson Counter Advantage of Johnson counter is that each state can be decoded easily. In the t ruth table in Figure 10-12(b), state 1 is uniquely defined by A being one and B zer
o. Also, state 2 is defined when B is one and C is zero. Other six states also can be defined similarly. Such signal can be decoded with AND gates to realize counter decoding, like in Figure 10-15.
Figure 10-15. Decoding signals of mod-8 counter Synchronous Counter
Synchronous counter has very little delay time because all the flip-flops are trigg ered by the same clock pulse simultaneously. However, the circuit map tends to be a little complicated. These counters are used in applications as digital clocks, frequen cy counters, digital voltmeter, and digital computers.
Synchronous mod-10 counter Decimal counters are called BCD counter or mod-10 counters and expresses the decimals used in real life. It needs 10 states, 0 to 9, requiring at least 4 flip-flops, and also needs to reset when 10 clock pulse has passed. Figure 10-16 is a circuit
map for mod-10 counter, and Figure 10-17 is the truth table. Like in Figure 10-16, only the output of first and the fourth flip-flop needs to be changed to make the st ate reset to 0000.
Figure 10-16. Synchronous mod-10 counter
D 0 0 0 0 0
C 0 0 0 0 1
B 0 0 1 1 0
A 0 1 0 1 0
State 0 1 2 3 4
0 0 0 1 1 0
1 1 1 0 0 0
0 1 1 0 0 0
1 0 1 0 1 0
5 6 7 8 9 0
Figure 10-17. The truth table of Synchronous mod-10 counter
3-4. Up/Down/Preset Counter

Counter is a circuit utilizing basic flip-flop devices to count numbers every clock period. There are asynchronous method in which only the LSB part is triggered by the clock, and the other flip-flops are triggered by its previous flip-flop, and the syn chronous method where all the flip-flops are triggered by the clock and the next val ue is decided by each logic circuit. In experiment, synchronous method is used. Counter can be divided into up counters and down counters by its counting dire ction. In up-counter, the number increases with the clock, and in down-counter, it d
ecreases. Presettable counter can let the user decide the starting value in up-counte r and operate accordingly. In Figure 10-18. the counter has been synchronized by cl ock signals, while up/down inputs are placed so that up-down counter operations ca n be performed, and when PL is '0', counter resets to the value of P0, P1, P2, and P3. Counter operation starts from the reset values, P0, P1, P2, P3.
Figure 10-18. Presettable counter
When UP/ input value is 1, it acts as an up-counter to the value of '1111', and instaed of resetting to '0000', it resets to P0, P1, P2, P3 to continue up-counter operation. If UP/ input is '0', it will operate as a down-counter to the value '0000' and it will go to P0, P1, P2, P3 instead of '1111' to continue downward count. DOWN DOWN
For this operation, the signals have to be defiend accordin to the four outputs
, OUT_1, OUT_2, OUT_3, OUT_4, to receive P0, P1, P2, P3 values. Therefore, the se outputs are connected to NAND gates, which is again connected to input. P L P L
4. Pre-report Flip-flop and Counter Design Experiment

Use verilog HDL code to express Master/Slave J -K Flip-flop Do some research on Parallel Shift Register. Use verilog HDL code to express 4-bit bi-directional shift register. Use verilog HDL code to express synchronous mod -10 counter. Use verilog HDL code to express 4 -bit up/down preset counter.
5. Tools for Experiment

PC
A copy of MAX+PLUS II software Digital Circuit Training Kit
6. Experiment procedure and Measuring results

6-1. Designing and verifying of JK flip-flop and D flip-flop
Set Project in the software and type and save the verilog HDL code in Figure 10-4 and 11-4 in the Text Editor. Go to Assign > Device, and assign the appropriate device. Complie unt
il there is no error shown in Complier. Go to MAX+PLUS II > Waveform E ditor and mark the input/ output nodes. Assign appropriate input values. Run MAX+PLUS II > Simulator to execute Timing Simulation, and chec k the result in Waveform Editor. If the result is not appropriate, find t he reason for the problem and solve. Run MAX+PLUS II > Floorplan Editor and allocate each input and outp ut pins to FPGA's I/O. Compile the code, and keep allocating it to ot her I/Os until there's no error.
Run MAX+PLUS II > Timing Analyzer and check the time delay from i nput to output. Run MAX+PLUS II > Programmer and check if Configure is active. If n ot, go to Option > Hardware Setup to set Hardware Type to ByteBlast er. Connect the PC Parallel Port to Digital Circuit Design Training Kit's ByteBlaster Port with the cable provided. Set Mode select switch to XX0011', ByteBlaster Mode. Select the I/O control switch to use.
Turn on Digital Circuit Design Training Kit. Click Programmer > Configure to download the designed circuit to Digi tal Circuit Design Training Kit. Enter the va lue with the control switch and check the operation. Refer to the experiment results and write a report that has the truth table and waveform clearly shown.
6-2. Designing and verifying various Flip-flops and Counters
A. Using the verilog HDL code written in the preliminary report to repea t the above procedure to verify the operation. Design and verify JK Master/Slave Flip -flop Design and verify 4-bit bi-directional shift register Design and verify synchronous mod -10 counter circuit Design and verify 4-bit Up/down preset counter
7. Report Flip-flop and Counter Design Experiment

Refer to the table and waveform written during the experiment and exp lain the operation of JK Master/Slave Flip-flop, 4-bit bi-directional shif t register, synchronous mod-10 counter circuit, and 4-bit Up/down pre
set counter. Explain the setup time, hold time in D Flip-Flop. Find out the application of flip -flops.
Chapter 11. FSM(Finite State Machine) Design
1. Objective
Understanding the structural logic of FSM, and designing a simple FSM cir cuit using verilog HDL, based on the basic knowledge of FSM.
2. Key Points
Understanding the structural logic of FSM Understanding the state transition of FSM Understanding the designing of FSM using verilog HDL Simulating FSM with verilog code of FSM
3. Theory
FSM is a circuit that has finite states and changes states sequentially. FSM has two basic models, Mealy model and Moore model.
Mealy model is a state machine whose output relies on the current state and the input, where as Moore model only relies on the current state. For example, to cho ose a product in a vending machine, it needs to consider the amount of money and the price simultaneously, but the money indicator operates unaffected by the order t hat coin is put in.
In the two models, the states are expressed by binary signals called the state co efficients. States coefficients are saved in the flip-flops, called state registers, which i
s activated by outer clock input. Figure 11-1 and 11-2 shows the three parts of the state machine; State register to save the current state, Combinational circuit to tra nsit the state sequentially, and another combinational circuit to achieve the appropria te output values. Figure 11-1 shows the output of Mealy machine decided by two co nditions. The input and output of current state register is inputted into the output l ogic circuit to decide the output and is maintained for a clock period. The next stat e combination happens when the input signal and the current state register is saved. The output of the logic circuit is saved in the current state register during the cloc k edge. Moore state machine does not consider the sequence the input and output i
s put in. Figure 11-2 shows the difference between two machines. Therefore the stat e symbol is different from that of Mealy machine. Moore state machine has the curre nt state shown in the circle with the output to emphasize that it is restricted by the current state. It shows that input creates transition between finite states, but does not decided the output entirely.
Figure 11-1. Structure of Mealy Machine and its state symbol
Figure 11-2. Moore machine structure and its state symbol
State transition table and state map. In the state map, circle represents states and the arrows shows the state transi tion. State map in Figure 11-3 is showing graphically the Mealy machine in Table 11 -3. If state 0 is the initial state, the state transits every clock cycle depending on t he input and the current state. The input 1 puts it out of its initial state in Figure 11-3, when input 0 is applied, it goes back to its initial state. The transition that ch anges output is when 1 is received in state 1, or 3 and changes to state 4. Table 11-1. State transition table
0 1 0 1 0 1 0
state0 state0 state1 state1 state2 state2 state3
state0 state1 state0 state2 state0 state3 state3
0 0 0 1 0 0 0
1 X
state3 state4
state4 state0
1 0
Figure 11-3. State map according to the state transition table
Chocolate Vending machine Let's design a chocolate vending machine using FSM. One chocolate bag is 150 won. The vending machine only can receive 100 won and 50 won coins. To lower th e cost of production, changes are not returned. To buy a chocolate, the reset butto n has to be pressed and the money put in afterwards. If more than 200 won is recei ved, only one chocolate bag is given. Special circumstances as 'sold out' are not co nsidered.
Specification 1. Price: 150 won 2. Useable Coin: 50 won and 100 won 3. Change is not returend 4. Valid combinations of prices: (50 won, 100 won) (100 won, 50 won) (50 won , 50 won, 50 won) (100 won, 100 won) 5. Input signal: coin[1:0] = 2'b00 2b01 no coin 50 won
2b10 6. Ouput singal: chocolate = 1'b1
100 won Chocolate sold
7. State: 4 state: S0=no coin, S50=50 won, S100=100 won, S150=150won
In the state map in Figure 11-4, the machine starts to operate from state 0. If t here are no coins inserted, the machine maintains its state and naturally no chocolat e comes out.
The controller state changes when 50 won or 100 won is put into the vending m
achine. S50 and S100 are states when 50 or 100 won coin is put into the machine, and it also maintains its state when no more coin is inserted and only progresses wh en more coin is inserted..
Figure 11-4. Controller of Chocolate vending machine If the money is over 150 won, the specification there are no changes and chocol ate comes out. Therefore the transition happens from S100 to S150, regardless of in put, and returns to initial state, one chocolate bag as an output.
Vehicle speed controller Vehicle speed has four states, stop, slow, medium and fast. Stop is the initial sta te where there is no key input and the car is not moving. Key input is the signal th
at can change the vehicle speed. Slow, medium fast represents the vehicle's speed. I nput accelerate is the signal for acceleration that accelerates the vehicle speed and i nput brake does the opposite. Vehicle speed controller FSM outputs the current spe ed state of the vehicle. The FSM for car speed controller is shown below.
Figure 11-5. Vehicle speed controller
Specification 1. Input Key: Unsynchronous Reset signal, and goes back to initial state whe n '0'. Accelerate: Increases speed state when '1' Brake: Decreases speed state when '1'. Clock: Inputs clk in speed controller
2. Brake input has more priority than Accelerate input.
3. It prints the current speed state
Designing traffic light controller Consider the traffic light controller to relieve the traffic in intersections in expres s highways and principal roads. This machine can sense the vehicles entering highwa ys from roads by special sensors buried in the road. The sensor outputs signal C wh en the car is waiting at the intersection and the signal C changes the traffic light an d maintains it for the vehicle to pass.
Vehicles are always going in highways, therefore the traffic light has to be mainta ined at green light as long as possible. It needs to maintain green light unless there is a vehicle trying to enter from a principal road. If there are no vehicles in the roa d, the light in the road remains red.
Table 11-2 has 5 states. Initial state is set at when the highway light is green a nd changes when the sensor signal C is inputted. It is a three color light like the re al one, so the yellow light to warn the drivers is S1. When it reaches S2, the vehicl es in highway has to stop. During the transition from S0 to S2, the light in the prin
cipal road is red. State S3 has to be reached before the vehicles can pass the inters ection, and if there is no more signal C from the sensor, after appropriate time, the state transition from S3 to S4 occurs, allowing vehicles in highways to move again. To simplify the design, the circumstances in which the vehicles in highway enters the principal road or the converse are ignored.
Figure 11-6. Traffic light controller
Table 11-2. State of Traffic light controller

State S0 S1 S2 S3 S4 Description Highway GREEN Highway YELLOW Highway RED Highway RED Highway RED Farm RED Farm RED Farm RED Farm GREEN Farm YELLOW
4. Pre-report FSM Design Experiement

Realize the FSM in Figure 11-3 in its Behavioral model using verilog HDL. Realize the FSM in Figure 11 -4 in its Behavioral model using verilog
HDL. Realize the FSM in Figure 11 -5 in its Behavioral model using verilog HDL. Refer to the instructions about traffic light controller to write a state t able and realize the FSM in its Behavioral model using verilog HDL.
5. Tools for Experiment

PC 1 copy of MAX+PLUS II software Digital Circuit Training Kit
6. Experiment procedure and Measuring Results

6-1. Designing and verifying FSM
Set Project in the software and type and save the veriolg HDL code in
Figure 11-3 in the Text Editor. Go to Assign > Device, and assign the appropriate device. Complie unt il there is no error shown in Complier. Go to MAX+PLUS II > Waveform Editor and mark the input/ output nodes. Assign appropriate input values. Run MAX+PLUS II > Simulator to execute Timing Simulation, and chec k the result in Waveform Editor. If the result is not appropriate, find t he reason for the problem and solve. Run MAX+PLUS II > Floorplan Editor and allocate each input and outp
ut pins to FPGA's I/O. Compile the code, and keep allocating it to ot her I/Os until there's no error. Run MAX+PLUS II > Timing Analyzer and chec k the time delay from i nput to output. Run MAX+PLUS II > Programmer and check if Configure is active. If n ot, go to Option > Hardware Setup to set Hardware Type to ByteBlast er. Connect the PC Parallel Port to Digital Circuit Design Training Kit's ByteBlaster Port with the cable provided.
Set Mode select switch to XX0011', ByteBlaster Mode. Select the I/O control switch to use. Turn on Digital Circuit Design Training Kit. Click Programmer > Configure to download the designed circuit to Digi tal Circuit Design Training Kit. Enter the value with the control switch and check the operation. Refer to the experiment results and write a report that has the truth table and waveform clearly shown.
6-1. Designing and Verifying various FSM

A. Using the verilog HDL code written in the preliminary report to repea t the above procedure to verify the operation FSM in Figure 11-4, and 11-5 realized using verilog HDL code Verilog HDL code of Traffic light controller
7. Report FSM (Finite State Machine) Design

Do some research on the circuits using Mealy machien and Moore mac hine.
Optimize the FSM in Figure 11 -3 by designing it differently. Write a table that differs in the waiting time of traffic light. Design the chocolate vending machine so that when 200 won is inserte d, change will be returned.
12. Design Project I
1. Title
Designing Digital clock training
2. Objective
Practice design application of 1 MHz crystal oscillator and 7-segment displ
ay equipment provided in the training kit, and comparing its operation with th e theoretical results.
3. Design Conditions
Express it in units of AM/PM, hours, minutes, seconds. Display it with 7 screens of 7-segments in the kit as in the picture. - A means morning, afternoon has to be P' - Express hour between numbers 1~12
- Express 'minute' between numbers 00~59 - Express 'second' between numbers 00~59
Use 1 MHz crystal oscillator provided in the training kit. Make it possible to enter AM/PM, hour, minutes, seconds from outer i
nputs. Use the buttons in the training kit, sw1~sw5, for input switches - Allow AM/PM conversion by pressing the input switches - Allow hours, minutes to increase sequentially by pressing the input switch es - Allow seconds to reset to 00 when the switch is pressed - To set the initial state as same as the picture Let the error be below 2 seconds every 10 minutes. To have 12:00 as the basis for distinguishing AM/PM.
4. Pre-Report Designing Digital Clocks

Research on the below factors, as they are needed for the project
- 1 MHz crystal oscillator in the training kit - The input/output characteristics of 7-segment display - Components of combinational and sequential circuits needed to design a digital clock Think about problems that cause the errors in digital clocks and find w ays to solve them.
5. Report Designing Digital Clocks

Analyze the designing options given in the project, and explain the obj ectives concerning realization.
Draw a block diagram of the designed circuit and define the inputs/out puts(I/O) and explain them. Explain in detail about the code and the realization of the circuit and attach the procedures and results for verification.
13. Design Project II
1. Title
4-floor elevator controller design training
2. Objective
Practicing the knowledge of circuits that has been studied previously by d esigning a elevator controller, and verifying its input/output operation accordin g to the given conditions.
3. Designing Conditions
Design a 4-floor building's elevator. In the hall, there is only Up input on the 1st floor, and Down in the
4th floor, where 2nd and 3rd floor has both Up/Down inputs. Inside the elevator, 4 inputs exist, 1st ,2nd, 3rd and 4th floor. Design a elevator with total 10 inputs,(4 inside, 6 outside) - Use the switches in the training kit - The opening/closing of the doors are not taken into consideration. Output should be expressed in the current floor and the state of the e levator. - The floors should be expressed using 7-segment display. - The state of the elevator, U(Up), D(Down), S(Stop), should be expresse
d in 7-segment display. Multiple selection Hall/Elevator inputs should be allowed. - Pressing more than one button is not taken into consideration. The options for multiple inputs should be set independently. - For example, the elevator can be set to operate as a normal elevator, or the elevator can carry out the operation for the first input, and go on to the next input. The designer - The exact designing specification and the FSM should be shown. Compare the results and the state table of FSM.
4. Pre-report Designing Elevator Controller

Research the elevator operation combination that is needed to design a n elevator controller.. Find the combinational or sequential circuits needed to design the cont
roller and do some research on them. Explain the difference between the controller f or one elevator and the controller for two elevators.
5. Report Designing Elevator Controller

Analyze the designing conditions given in the project, and explain the desirable specification related to realization. Explain and show the block diagram of the designed circuit and define its inputs/outputs. Explain in detail about the code and the r ealization of the circuit and attach the procedures and results for verification.
Appendix A TTL Chip
7400(Quadruple 2-Input Positive-NAND Gates) Positive logic :
General Description: This device contains four independent gates each of whic h performs the logic NAND function. Features: Alternate Military/Aerospace device (54LS00)
Inputs A L L H B L H L Outputs Y H H H
Function Table (
) H=High Logic Level / L=Low Logic Level
7402(Quadruple 2-Input Positive-NOR Gates) Positive logic :
General Description: This device contains four independent gates each of whic h performs the logic NOR function. Features: Alternate Military/Aerospace device (54LS02)
Inputs A L L B L H Outputs Y H L
H H
L H
L L
Function Table (
7404(Hex Inverters) Positive logic :
General Description: This device contains six independent inverters.

Input A H L Output Y L H
Function Table (
7408(Quadruple 2-Input Positive-AND Gates) Positive logic :
General Description: This device contains four independent gates each of whic h performs the logic AND function. Features: Alternate Military/Aerospace device (54LS08)
Inputs A L L B L H Outputs Y L L
H H
L H
L H
Function Table (
7411(Triple 3-Input Positive-AND Gates)
Positive logic :
General Description: This device contains three independent gates each of whi ch performs the logic AND function. Features: Alternate Military/Aerospace device (54LS11)
Inputs A X X B X L C L X Outputs Y L L
L H
X H
X H
L H
Function Table (
H=High Logic Level L=Low Logic Level X=Either Low or High Logic Level
7432(Quadruple 2-Input Positive-OR Gates)
Positive logic :
General Description: This device contains four independent gates each of whic h performs the logic OR function. Features: Alternate Military/Aerospace device (54LS32)
Inputs A L L B L H Outputs Y L H
H H
L H
H H
Function Table (
7445(BCD-To-Decimal Decoder / Driver)
General Description: This device consists of eight inverters and ten, four-inpu t NAND gates. The inverters are connected in pairs to make BCD input d ata available for decoding by the NAND gates. Full decoding of BCD input logic ensures that all outputs remain OFF for all invalid (10-15) binary in put conditions. These decoders feature high-performance, NPN output tran sistors designed for use as indicator/relay drivers, or as open-collector logi c-circuit drivers. The high-breakdown output transistors are compatible for interfacing with most MOS integrated circuits. Features: Full decoding of input logic 80 mA sink-current capability All outputs are off for invalid BCD input conditions
Function Table
N o. 0 1 D L L Inputs C L L B L L A L H 0 L H 1 H L 2 H H 3 H H Outputs 4 H H 5 H H 6 H H 7 H H 8 H H 9 H H
2 3 4 5 6 7 8
L L L L L L H
L L H H H H L
H H L L H H L
L H L H L H L
H H H H H H H
H H H H H H H
L H H H H H H
H L H H H H H
H H L H H H H
H H H L H H H
H H H H L H H
H H H H H L H
H H H H H H L
H H H H H H H
9 I N V A L I
H H H H H H H
L L L H H H H
L H H L L H H
H L H L H L H
H H H H H H H
H H H H H H H
H H H H H H H
H H H H H H H
H H H H H H H
H H H H H H H
H H H H H H H
H H H H H H H
H H H H H H H
L H H H H H H
7476(Dual J-K Flip-flops with PRESET and CLEAR)
General Description: This device contain two independent negative-edge-trigge red flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predicable operation. The preset and cl ear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table.
Inputs PRE L CLR H CLK X J X K X Q H Outputs Q L
H L H H H H
L L H H H H
X X
X X L H L H
X X L L H H
L H Q0 H L TOGGLE
H H Q0 L H
Function Table
74138(3-To 8-Line Decoders / Demultiplexers)
General Description: This device decodes one-of-eight lines, based upon the
conditions at the three binary select inputs and the three enable input. Tw o active-loe and one active-high enable inputs reduce the need for externa l gates or inverters when expanding. A 24-line decoder can be implemente d with no external inverters, and a 32-line decoder requires only one inver ter. An enable input can be used as a data input for demultiplexing applica tions. Function Table
Inputs Outputs Enable Select
G 1 X L H H H
G C 2* H X L L L X X L L L X X L L H X X L H L B A 0
Y 1 H H L H H
Y 2 H H H L H
Y 3 H H H H L
Y 4 H H H H H
Y 5 H H H H H
Y 6 H H H H H
Y 7 H H H H H
H H H H H
H H H H H
L L L L L
L H H H H
H L L H H
H L H L H
H H H H H
H H H H H
H H H H H
L H H H H
H L H H H
H H L H H
H H H L H
H H H H L
* G2 = G2A + G2B / H=High Logic Level / L=Low Logic Level 74147(10-Line Decimal To 4-Line BCD Priority Encoders)
General Description: This device encodes nine data lines to four-line (8,4,2,1)
BCD. The implied decimal zero condition requires no input condition as z ero is encoded when all nine data lines are at a high logic level.
Inputs 1 H X X X 2 H X X X 3 H X X X 4 H X X X 5 H X X X 6 H X X X 7 H X X L 8 H X L H 9 H L H H D H L L H Outputs C H H H L B H H H L A H L H L
X X X X X L
X X X X L H
X X X L H H
X X L H H H
X L H H H H
L H H H H H
H H H H H H
H H H H H H
H H H H H H
H H H H H H
L L L H H H
L H H L L H
H L H L H L
Function Table
H=High Logic Level / L=Low Logic Level / X=irrelevant LM555 Timer
General Description: This device is a highly stable device for generating accur ate time delays or oscillation. Additional terminals are provided for triggeri ng or resetting if desired. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable op eration as an oscillator, the free running frequency and duty cycle are acc urately controlled with two external resistors and one capacitor. The circui t may be triggered and reset on falling waveforms, and the output circuit c an source or sink up to 200mA or drive TTL circuits. Features: Timing from microseconds through hours Operates in both astable and monostable modes Adjustable duty cycle
Output can source or sink 200 mA Output and supply TTL compatible Temperature stability better than 0.005% per Normally on and normally off output Available in 8-pin MSOP package
Appendix B MAX+plus II User Guide
1. Creating a Project
Run MAX+plus II. Go to Menu, select File > New(Figure B -1) . In the menu shown, select Text Editor file and click OK.
Figure B-1. Select File > New
Text Editor opens as in Figure B -2.
Figure B-2. Opening Text Editor
As in Figure B-3, Select File > Save to save the file in the folder and na me the Text Editor appropriately. The name should be identical to the mo dule of verilog HDL. Select .v for Automatic Extension.
Figure B-3. Saving Text
Select File > Project > Name, and name the project, identical to the text. (Set Project to Current File will also suffice.)
Figure B-4. Saving Project
Figure B-5. After saving project and text
2. Text Editor: verilog HDL

Figure B-6 shows the veriolog HDL code for BCD_to_Decimal Decoder. Co py the code in the Text Editor and save.
Figure B-6. Verilog HDL code for BCD_to_Decimal Decoder
Figure B-7. The code
3. Assigning Device
Select Assign > Device to assign the appropriate device. (For example, Design Family: FLEX10K, EPF10K10QC208-3)
Figure B-8. Assigning Device
4. Compiler
Select MAX+plus II > Compiler(Figure B -9)
Figure B-9. Compiler
Click on Start to start compiling and fix the errors shown.
Figure B-10. Successful Compiling
5. Waveform Editor
Select MAX+plus II > Waveform Editor(Figure B -11)
Figure B-11. Waveform Editor
Select Node > Enter Nodes from SNF(Simulator Netlist File), and the Ente r Nodes from SNF window will pop up. The desired inputs and outputs ca n be expressed in this window. Click List and click => to select the I/O nodes for BCD_to_Decimal Decoder.
Figure B-12. Selecting Nodes
Click OK, and the Waveform Editor will show the selected nodes.(Figure B-13)
Figure B-13. Waveform Editor
Waveform Editor in MAX plus II can assign values to the inputs directly. Select the desired section and right-click to see the menu. Click on inser t to assign the desired value to the section. Assign values to the inputs and save, with the same name as the project and the extension being scf.
Figure B-4. Saving Waveform Editor
6. Simulator
Select MAX+plus II > Simulator, and the Timing Simulation window will po p up. Set the appropriate Simulation time, and click on start to simulate. If Simulation finishes without any error, the outputs will change according to the inputs assigned in the Waveform Editor. Analyze the results in Waveform Editor. If the results are undesirable, find the reason and fix the error.
B-15. Simulation
Figure B-16. Results in Waveform Editor
FPGA User Guide

Use Max+plus II to simulate and express the results in Waveform Editor, and download the verilog HDL code in FPGA to verify.
Run MAX+PLUS II > Floorplan Editor to assign the input/output pins to FPG A's I/O(input/output), and complie accordingly. If there is errors shown, modi
fy the code until there is none. Run MAX+PLUS II > Timing Analyzer to identify the delay time from inputs t o outputs. Run MAX+PLUS II > Programmer to check if Configure button is activated. If it is not, go to Option > Hardware Setup and set Hardware Type to ByteBl aster. Connect the Parallel Port in PC and the ByteBlaster Port in Digital Circuit Design Training Kit with a cable. Set Mode Select switch to XX0011' to set the kit at the ByteBlaster Mode.
Assign the I/O control switch to the inputs and outputs. Turn on Digital Circuit Design Training Kit. Click on Programmer > Configure to download the designed circ uit to Digital Circuit Design Training Kit. Insert the values with the assigned control switch and verify the operation.
Appendix C
Internet Website regarding Digital Circuit
Newsgroup
comp.lang.vhdl comp.lsi.cad sci.electronics.cad
Web Site http://www.acc-eda.com/ Homepage of Accolade Design Automation. Offers information ab out On-line VHDL tutorial, and the product of Accolade compa
ny, PeakVHDL and PeakFPGA. http://www.actel.com/ Homepage of Actel Company. Offers information about FPGA eq uipment and software regarding VHDL. http://www.altera.com/ Homepage of Altera Company. Offers information about FPGA eq uipment and MAX+PLUS software. http://www.amd.com/ Homepage of AMD(Advanced Micro Devices) Company. Offers inf
ormation about Complex PLD and VHDL logic combinational equ ipment. http://www.atmel.com/ Homepage of ATMEL company. Offers information about Comple x PLD and VHDL logic combinational equipment.
http://www.attme.com/ Hompage of AT&T Microelectronics(current Lucent Technologies) . Offers information about FPGA equipment and design tools.
http://www.cadence.com/ Homepage of Cadence Design Systems. Offers information about VHDL and producst regarding verilog. http://www.capilano.com/ Homepage of Capilano Computing Company. Offers information a bout DesignWorks schematic, simulation tools and products regar ding VHDL. http://www.chrysalis.com/ Homepage of Chrysalis Comapny. Offers information about VHDL
and formal verification tools regarding verilog. http://www.cypress.com/ Homepage of Cypress Semiconductor Company. Offers informatio n about complex PLD, FPGA equipment and cheap VHDL logic combinational package. http://www.data-io.com/ Homepage of Data I/O Corporation Company. Offers information about FPGA and design tools regarding complex PLD. http://www.escalade.com/
Homepage of Escalade Company. Offers information about design tools regarding VHDL. http://www.exemplar.com/ Homepage of Exemplar Logic Company. Offers information about 0 FPGA and VHDL or verilog logic combinational tools for gate array. http://www.ikos.com/ Homepage of IKOS Company. Offers information about simulator s using hardware accelerator.
http://www.latticesemi.com/ Hompage of Lattice Semiconductor Corporation Company. Offers information about FPGA and design tools for complex PL D. http://www.libtech.com/ Homepage of Library Technologies Company. Offers information a bout simluation and logic combination library. http://www.mentor.com/ Homepage of Mentor Graphics company. Offers information abou
t designing, simulation and design combinational tools using VHD L. http://www.model.com/ Homepage of Model Technology Company. Offers information abo ut V-system simulator for VHDL and verilog. http://www.orcad.com/ Hompage of OrCAD. Offers information about design tools for P C and simulation, logic combinational tools for VHDL. http://www.quicklogic.com/
Homepage of Quicklogic Company. Offers information about FPG A equipment and simulation, logic combinational tools for VHDL . http://www.synopsys.com/ Homepage of Synopsys Company. Offers information about simula tion and logic combinational tools for VHDL and verilog. http://www.synplicity.com/ Hompage of Synplicity Company. Offers information about A logic combinational tools for VHDL and verilog. FPG
http://www.syncad.com/ Homepage of SynaptiCAD Company. Offers information about W aveformer which can create VHDL or veriolog form of testbench from a waveform, and timing analyzer. http://www.veribest.com/ Homepage of Veribest(Intergraph Electronics) Company. Offers in formation about varioius automated design tools. http://www.viewlogic.com/ Homepage of Viewlogic company. Offers information about simula
tion, logic combinational tools for VHDL and verilog that operat es on PC and workstations. http://www.xilinx.com/ Homepage of Xilix Company. Offers information about FPGA an d complex PLD equipment and design tools for VHDL.
Appendix D
verilog HDL
1. Basics of verilog HDL

Characteristics of verilog HDL(Hardware Description Language) - Similar Syntax to C, simpler sentence than VHDL - Substantial library in development of ASIC
- First standardized in 1995, by IEEE 1364
module - verilog offers a concept called Module, which is the basic buildling block for verilog. Module itself can be a structural element, or be an assembly of
Lower Level Design Block. Frequently used elements in designs are typically grouped by Module to offer common functional abilities. Module offers function s that is needed by higher Blocks through its Port Interface(input, output), bu t its inner structure is not shown to others. This allows the designer to amen
d the inner structure of Module without affecting any other parts. Figure D-1. Design example of Half adder
- Useable : English, number, underscore(_) - Like in C, capitalization is distinguished.
- Refer to Figure D-1 module. Figure D-1 shows a half adder in two forms of module.
Instance - Module offers a template for what object can be created. When Module i s used, verilog creates an object based on its template and each objevt has i ts own Name, Variable, Parameter and I/O interface. Creating an object from Module Template is called Instantiation, and the created object is called Inst ance.
- Figure D-2 is an example of Instantiation, which instantiated the two half adders in Figure D-1.
Figure D-2. Example of Designing Ful adder using Figure D-1
Data type - All the signals(variables) used in program should declare a form - Register form : declared as reg, and is similar to the concept of variable in typical programming language - Net form : declared as wire and shows the actual connections between ci rcuits - Multitude bit signal: Declare bit width, range in the form of [MSB:LSB] - ex) wire [3:0] temp; wire MSB, LSB; //Declare 4bit wire temp //Declare 1bit wire MSB, LSB
assign MSB = temp[3]; MSB assign LSB = temp[0]; LSB
//Enter the highest bit value of temp to
//Enter the lowest bit value of temp to
Number Specification - Sized Number is written as <size>'<base format><number>. - ex) 4'b1111 12'habc //4bit binary number //12bit hexadecimal number
16'd255
//16bit decimal numb
- <size> can only use decimal numbers and states the number of Bit - <base format> uses <'d or 'D> to show decimal values,<'h or 'H> for hex adecimal values, <'b or 'B> for binary values, and <'o or 'O> for octal values . - <number> uses the form selected in the base format.
Operators - Binary Operator
- Relational Operator
- Logic Operator
- Bitwise Operator
- Equality Operator
- Etc
Initial and Always - Basically initial and always are used in the same way, but always block is
operated every time the sensitive lists transits, and initial block is operated only once.
Statement Looks like initial begin initial ... Starts when simulation end starts always always begin ... Continually loop while (power on) do statements Used in synthesis Execute one and stop synthesis Not used in Starts How it works Use in Synthesis ?
end
- Each always or initial are operated in parallel, but is executed sequentiall y if it's in one always block. - left-hand variable in initial and always must always be reg type. - If clock is inserted in always's sensitive lists, it combines to be a sequen tial circuit - posedge or negedge : can come in front of sensitive lists' varia
ble. Posedge only operates when signal transits from 0 to 1, negedge only wh en signal transits from 1 to 0.
Blocking and nonblocking assignment - blocking assign uses '=' , nonblocking assign uses '<='
- Combinational circuit normally use blocking, sequential cuircit nonblocking
Using Primitive function
- One Logic Circuit can be realized using Logic Gate. verilog offers a Logi c Gate already defined by Primitive. This Primitive can be instantiated like ot her Modules except for the fact that it is already defined in veriolog and doe s not need Module Definition. All Logic Circuits can be designed using Logic Gates that are already given, and there are various kinds of Logic Gates su ch as and/or and but/not. - Output is placed in the front of all others and input follows inside the p ort.
Simulation program(Test bench) - Simulation program is also called Test bench and it is a program that tes ts the realized hardware
Figure D-3. Example of Test bench
- Declaring input/output variables : In test bench, the input of realized mo
dule is declared as reg, and output as wire - Calling the realized hardware - Input and verification using system task
2. Design Example
4 : 1 multiplexer
// 4-to-1 multiplexer module mux4_to_1 (out, i0, i1, i2, i3, s1, s0) ; //module declaration
output out ;
//output declaration
input input reg
i0, i1, i2, i3 ; s1, s0 ; out ;
//4-bit input declaration //select input declaration //Declaration of output in reg
always @(s1 or s0 or i0 or i1 or i2 or i3) begin case ( {s0, s1 }) 2'b00: 2'b01: 2'b10: 2'b11: out = i0 ; out = i1 ; out = i2 ; out = i3 ; //select when input is 2'b00 //select when input is 2'b01 //select when input is 2'b10 //select when input is 2'b11
default: out = 1'bx ; endcase end endmodule
4-bit counter
// 4-bit Binary Counter module counter (Q, clock, clear) ; //module declaration
output [3:0] Q ; input reg clock, clear ; [3:0] Q ;
//4-bit output declaration //input declaration //output declaration in reg
always @(posedge clear or negedge clock)
begin if (clear) Q = 4'd0 ; else Q = (Q + 1) % 16 ; end endmodule //run when clear != 1 //run when clear == 1
Appendix E Digital Circuit Kit of Han Baek Electronics

1. Key Points
Understand the functions and instructions of Digital Circuit Kit of Han Baek Electronics used in the textbook. This product uses MAX+plus II of ALTERA company to let users master the designing of digital circuits.
2. Specific Parts
The picture below shows the digital circuit design kit used in the text book. The specific parts are as follows.
Logic Design Block This part uses ALTERA's MAX+plus II to receive the circuit that the user de signed and realize the circuit such as TTL or logic circuit. It is able to realiz e 10,000 gates(FLEX10K10). Control Block This part allows the user to select clock and regulate download. Download he re means using ways shown in to send the designed circuit to block 1 . The control over this download is done by (S/ W). The crystal oscillator's output, 1 MHz can be selected in 4 modes, 1, 1/100, 1/10,000 and outer c
lock, and this is also controlled by (S/W)
I/O Control S/W Block The user designed circuit's I/O in is connected to display blcok, input swi tch block or DATA and address lines by using this part.
RAM 's inner RAM also can be used but this part is normally used to control t he outer RAM. It can be used when logic regarding a large database or looku
p table is realized.
RS232C This part allows the mutual communication and interface between PC and the logic design part.
ByteBlaster This part is the sending format in which the user sends his/her designed circ uit from PC to block 11.
EPROM A typical Parallel ROM that can be used when user circuit is sent to block n umber 1. It is used when the test board is controlled without a PC. However , this ROM can be only used when a ROM writer that can write this ROM is available.
PROM(EPC1) A way to use the ROM for ALTERA. To use this ROM, other sepcific writin
g equipments are needed.
Download Control & Clock Generate Control Mode S/W A control mode for , and is used by setting the appropriate S/W for e ach function when they are used. It also contains the part to select the clock mode for frequency oscillator. The specific S/W can select the own frequenc y, 1/100, 1/10000 and outer frequency mode, and the table below can be ref erred to for wanted settings.
1 BYTE PPS ROM 1MHz 10KHz 100Hz CLK_E OFF OFF ON ON
2 OFF ON OFF ON
3 OFF ON OFF -
4 OFF ON ON -
5 ON OFF ON -
6 ON OFF OFF -
XT
Display Block This part expresses the circuit designed by the user, and the user should sel ect the output equipment beforehand. There are LCD, 7-segment and LED o utputs, and the characteristics of these outputs should be taken into consider ation when designing the circuit. INPUT Switch Block This part can be used as input and has S/W in the form of Key Pad and Bu
s. The selection can be done by the user, but the selection have to be contr olled by Control S/W in number 3.
Expansion Port 1, 2 The part can be used when the designed circuit clashes with 10, 11, or a diff erent interface board has been manufactured.
3. The composition of I/O Pin of the board

EPF 10K 10QC208-4 comprises of total 134 I/O Pins, but only about a
hundred pins are useable. The following pins should be used to utililze each p art's equipment. INPUT Pin Signal INPUT
CLOCK = 79
SWITCH INPUT
SW1 = 122 SW4 = 116 SW2 = 121 SW5 = 115 SW3 = 120 SW6 = 112 SWA = 119 SWB = 111
SW7 = 38 SW0 = 44
SW8 = 39 SWF = 45
SW9 = 40 SWE = 46
SWC = 41 SWD = 47
BUS_SWITCH INPUT BUS_SW1-1 = 10 BUS_SW1-2 = 11 BUS_SW1-3 = 12 BUS_SW1-4 = 13 BUS_SW1-5 = 16 BUS_SW1-6 = 17 BUS_SW1-7 = 18 BUS_SW1-8 = 19 BUS_SW2-1 = 24 BUS_SW2-2 = 25 BUS_SW2-3 = 26 BUS_SW2-4 = 27 BUS_SW2-5 = 28 BUS_SW2-6 = 29 BUS_SW2-7 = 30 BUS_SW2-8 = 31
OUTPUT PIN
LED OUTPUT
LED1 = 53 LED2 = 54 LED3 = 55 LED4 = 56 LED5 = 57 LED6 = 58 LED7 = 60 LED8 = 61 LED9 = 62 LED10 = 63 LED11 = 64 LED12 = 65 LED13 = 67 LED14 = 68 LED15 = 69 LED16 = 208
LCD OUTPUT
LCD_DATA00 = 150 LCD_DATA01 = 149 LCD_DATA02 = 148 LCD_RS = 136 LCD_RW = 135 LCD_E = 134
LCD_DATA03 = 147 LCD_DATA04 = 144 LCD_DATA05 = 143 LCD_DATA06 = 142 LCD_DATA07 = 141
SEGMENT OUTPUT
SEG_1a = 207 SEG_1b = 206 SEG_1c = 205 SEG_2a = 198 SEG_2b = 197 SEG_2c = 196 SEG_3a = 189 SEG_3b = 187 SEG_3c = 186 SEG_4a = 174 SEG_4b = 173 SEG_4c = 172
SEG_1d = 204 SEG_1e = 203 SEG_1f = 202 SEG_1g = 200 SEG_1h = 199 SEG_5a = 164 SEG_5b = 163 SEG_5c = 162 SEG_5d = 161 SEG_5e = 160
SEG_5f = 159 SEG_5g = 158 SEG_5h = 157
SEG_6f = 99 SEG_6g = 97 SEG_6h = 96
SEG_7f = 89 SEG_7g = 88 SEG_7h = 87
SEG_8f = 73 SEG_8g = 71 SEG_8h = 70

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Appendix E.

Digital Circuit Kit of Han Baek Electronics 1

Chapter 11. FSM(Finite State Machine) Design 1

Appendix D. verilog HDL 1

Appendix C. Internet Website regarding Digital Circuit 1

Chapter 11. FSM(Finite State Machine) Design 1

Appendix B. MAX+plus User Guide 1

Electric Circuit Experiment

Appendix E. Digital Circuit Kit of Han Baek Electronics 2

Chapter 11. FSM(Finite State Machine) Design 2

Appendix D. verilog HDL 2

Appendix C. Internet Website regarding Digital Circuit 2

Chapter 11. FSM(Finite State Machine) Design 2

Appendix B. MAX+plus User Guide 2

Appendix E. Digital Circuit Kit of Han Baek Electronics 3

Chapter 11. FSM(Finite State Machine) Design 3

Appendix D. verilog HDL 3

Appendix C. Internet Website regarding Digital Circuit 3

Chapter 11. FSM(Finite State Machine) Design 3

Appendix B. MAX+plus User Guide 3

Appendix E. Digital Circuit Kit of Han Baek Electronics 4

Chapter 11. FSM(Finite State Machine) Design 4

Appendix D. verilog HDL 4

Appendix C. Internet Website regarding Digital Circuit 4

Chapter 11. FSM(Finite State Machine) Design 4

Appendix B. MAX+plus User Guide 4

Appendix E. Digital Circuit Kit of Han Baek Electronics 5

Chapter 11. FSM(Finite State Machine) Design 5

Appendix D. verilog HDL 5

Appendix C. Internet Website regarding Digital Circuit 5

Chapter 11. FSM(Finite State Machine) Design 5

Appendix B. MAX+plus User Guide 5

Chapter 1. Basic Circuit Backgrounds

Chapter 2. Basic Circuit Backgrounds

Chapter 3. Oscilloscope and Resonance Circuit

Chapter 4. Various Diodes and its Properties

Chapter 5. Battery Tester and Charging Circuit analysis

Appendix E. Digital Circuit Kit of Han Baek Electronics 6

Chapter 11. FSM(Finite State Machine) Design 6

Appendix D. verilog HDL 6

Appendix C. Internet Website regarding Digital Circuit 6

Chapter 11. FSM(Finite State Machine) Design 6

Appendix B. MAX+plus User Guide 6

Chapter 6. Audio Amplifier Circuit Design Logic Circuits

Chapter 7. Basic Logic Gate Design

Chapter 8. Combination Logic Circuit Design

Chapter 9. Calculation Circuit Design

Chapter 10. Flip-Flop and Counter Design

Chapter 11. FSM(Finite State Machine) Design

Chapter 12. Design Project

Appendix E. Digital Circuit Kit of Han Baek Electronics 7

Chapter 11. FSM(Finite State Machine) Design 7

Appendix D. verilog HDL 7

Appendix C. Internet Website regarding Digital Circuit 7

Chapter 11. FSM(Finite State Machine) Design 7

Appendix B. MAX+plus User Guide 7

Chapter 13. Design Project

Appendix A. TTL Chip

Appendix B. MAX+plus User Guide

Appendix C. Internet Website Regarding Digital Circuit

Appendix D. verilog HDL

Appendix E. Digital Circuit Kit of Han Baek Electronics