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zbanjac@vets.edu.yu

Me (interrupt)


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8086 256
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8086
: INTR (Interrupt Request - pin 18) NMI
(Non Maskable Interrupt pin 17).
INTR
(Intel 8259).

.
,

( )
INTR

.

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8086

Intel 8086

m1

Data

m2
m3

256/8

INTR
INTA

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mn

1
2
3

INTR,
Interrupt Enable ,
. ,
.
,
!!!

INTA (pin 24) (Interrupt Acknowledge).
INTA, ,
8- (
)
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INTR
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3/9/2009


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. mi.
NMI
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NMI

INTR .
,
NMI .

( )

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10

()

( INT).


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RET
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Interrupt Pointer Table

Interrupt Pointer

. ,
Interrupt Pointer
(
) .
256 ,
.
Interrupt Pointer
.
,
4 .

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Interrupt Pointer Table


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:

0 0
4 1
8 2
12 3

1020 . 255

1024

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,
.
PSW
Instruction Pointer-,


ALU .
,
PSW , , ,
PSW


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PSW IP
(Stack).
IP-
.

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() .
, PSW-a
IP-a, ,
(
),
,
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PSW

IP

PSW
IP
PSW
IP
PSW

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IP

16

(o)

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: , , ,
, - ()...

:
()


(ISA, EISA, PCI, PCI Express AGP)
Disk interfejs ( SATA, SCSI, floppy disk)
( ,
PS/2, USB...)
BIOS CMOS
CMOS

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. PC
8MHz ( ),
133, 166 200MHz.

PC
. ,
( )

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Pentijum 4 ,
5 :
Socket 478 Intel ,
Socket 775 64- Intel
Socket A (462), AMD ,
Socket 754, 939 64- AMD .
2, 3, 4
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:
DMA
-

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EIDE S-ATA -
Enhanced IDE Serial ATA

(CD-ROM, DVD)
PCI Express, PCI ISA
PCI ISA

AGP - AGP
USB - USB
FireWire kontroler (IEEE 1394)
IrDA -
PS/2 - PS/2
, ( )
LPT COM -

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RTC (real-time clock) -


north bridge south bridge.
North bridge ( )
,
AGP .

.
South bridge ( )
( ,
), .

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, ,

. VIA KT600
600MHz,
.
,
: VIA, nForce, Intel, SiS, ALI, Opti...

95% .

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ROM (Read Only Memory)



RAM (Random Access Memory)

RAM :

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DRAM (Dynamic RAM)


SRAM (Static RAM)
RAM

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DRAM SRAM

DRAM

.

(512MB).

(70ns)

SRAM -

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(10ns)
M (256 B)

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RAM



(volatile storage)

Random access:

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:
RAM Static RAM - SRAM
Dinamic RAM - DRAM

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SRAM

flipflop

( flip-flop )

.

:
4 6 ,

SRAM

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SRAM



("0", "1").


128 512B

L1 L2 cash

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(cache)

.

. Intel
level 1 (L1) level 2 (L2) .


,
cash

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(L1 L2)
CPU.
CPU ,
L1.

L2.

RAM-.

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L1 : L2 cash

L1 cache: CPU

2KB 64KB.
Intel Celeron

L2 cache:
, CPU.

CPU.
L2 controller, l2 cache
CPU.
256 KB 2MB.

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DRAM



.



~ms,
(refreshing)

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DRAMa

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DRAM : SRAM

SRAM

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DRAM

10

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DRAM
SRAM .
DRAM

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memory controller

.


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