The 8051 MicroController

In this module, we will be discussing the MCS-51 family of microcontroller, in particular the 8051, which is the generic IC representative of this family.

Important 8051 Features

4K bytes ROM 128 bytes RAM Four 8-bit I/O ports Two 16-bit timers Serial interface 64K external code memory space 64K data memory space

FIGURE 21

8051 block diagram

Pin Layout
The 8051 is a 40 pin device, but out of these 40 pins, 32 are used for I/O. 24 of these are dual purpose, i.e. they can operate as I/O or a control line or as part of address or date bus.

FIGURE 22

8051 pinouts

Port 0 and Port 1

Port 0 is a dual purpose port, it is located from pin 32 to pin 39 (8 pins) and is labeled in the fig.2-2 as AD0 to AD7. Port 1 is a dedicated I/O port from pin 1 to pin 8. It is generally used for interfacing to external device thus if you need to connect to switches or LEDs, you could make use of these 8 pins.

Port 2 and Port 3

Like port 0, port 2 is a dual-purpose port. It can be used for general I/O or as the high byte of the address bus for designs with external code memory. Port 3 is also dual purpose but designers generally avoid using this port unnecessarily for I/O because the pins have alternate functions which are related to special features of the 8051. Indiscriminate use of these pins may interfere with the normal operation of the 8051.

_____ PSEN (Program Store Enable)

This is a dedicated control line on pin 29 and is used to enable external program (code) memory. This pin usually connects to an EPROMs Output Enable (OE) pin. This is a logic low pin as represented by the bar above the word PSEN, this means that during a fetch stage involving an instruction stored in external memory, the pin will be pulsed LOW.

 ALE ( Address Latch Enable)

This pin is used to demultiplex the address and data lines. Remember that port 0 has 2 functions. As the low byte of the address bus and as the data bus. In designs with external memory, port 0 is connected to both the address and data lines of the external RAM thus during the part of the fetch cycle where the address is supplied, the ALE is pulsed to enable the G (gate) control pin of the latch IC thus the data goes to RAM and is interpreted as an address. (see fig 2-10 and 211).

___ EA (External Access)

If you need to connect to external ROM then this pin must be tied LOW (0V). This pin must be tied high (+5V) if the programs executes from internal ROM.

RST (Reset) This is pin 9 of the IC and is used as the master reset for the 8051. In order for the 8051 to recognise that a reset has occurred, this pin must be brought HIGH for at least two machine cycles. During normal operation, this pin must be at logic LOW. This will be discussed in more detail later.

Oscillator ( clock) Input The 8051 is typically driven by a crystal oscillator connected to pin 18 and 19 as shown in fig.2-3. The words XTAL is short for crysTAL.

FIGURE 23

Driving the 8051 from a TTL oscillator

 Power Connections
The 8051 requires a +5V input on its Vcc input (pin 40) and Vss connection is on page 20.

I/O Port Structure

The internal circuitry for the I/O port is shown in fig 2-4. If you want to read in from a pin, you must first give a logic 1 to the port latch to turn off the FET otherwise the data read in will always be logic 0. When you write to the port you are actually writing to the latch e.g. a logic 0 given to the latch will be inverted and turn on the FET which cause the port pin to be connected to gnd (logic 0).

FIGURE 24

Circuitry for I/O ports

Machine Cycle and Clock Cycle

12 clock cycles make one machine cycle as shown in fig 2-5. E.g. if we use a 12 MHz oscillator, each clock cycle will have a time period of 1/12MHz. Twelve of these make one machine cycle so 12 x (1/12 MHz) = 1 microsecond. Thats the time of 1 machine cycle.

FIGURE 25

Relationship between oscillator clock cycles, states, and the machine cycle

Memory Structure
While most microprocessors implement a shared memory space for data and code (programs), microcontrollers has limited memory and the program is usually stored in ROM. In the 8051, both code and data may be internal but they are stored in separate memories, namely the internal ROM and RAM. Expandable to a max of 64K using external memory. The next page shows the 8031 which has no internal ROM.

FIGURE 26

Summary of the 8031 memory spaces

FIGURE 27

Summary of the 8051 on chip data memory

Register Banks
4 Register Banks Bank0, Bank1, Bank2 and Bank3 Each Bank consists of R0, R1, R2, R3, R4, R5, R6, R7 Bank 0 is the default upon power up of the microcontroller Other banks can be selected by programming PSW register.

General Purpose RAM

The general purpose RAM area is from address 30H to 7FH. The locations from address 20H to 2FH can also be used as general purpose RAM although these addresses have very specific role given in the next section.

Bit-Addressable RAM
The 8051 contains 210 bit-addressable locations of which 128 are at byte address 20H through 2FH as shown in fig 2-7. This is the powerful feature of most microcontroller because individual bits can be set, cleared, ANDed, ORed etc. with a single instruction instead of having to read a byte and modify

 Example
we could issue a simple instruction
SETB 67H This would set the bit at address 67H to logic HIGH. Bit 67H is bit 7(most significant bit) of byte location 2CH In order to achieve the same result, a microprocessor would need to do this: MOV A, 2CH ORL A,#10000000B MOV 2CH,A

Special Function Registers

Above 7FH, there is another block of memory 80H to 0FFH in all the version of MCS51 uP this 128 bytes of memory are reserved for Special Function Register (SFR). There are 21 SFRs. Refer to fig 2-7.

SFRs
SFR are usually addressed by name Memory location 0F0H is given a name called Register B, similarly 80H is called P0. Not all memory location has a name
memory location 35H has no name

Some locations between the SFRs have no names as well e.g. 91H. Such locations should not be used to store any data. If you do it then your data may be lost. Some important or commonly used SFRs will be discussed while others will be explained when you need to use them in your projects.

Program Status Word (PSW)

This is a very important register because it contains status bits which indicates the current state of the cpu. PSW.7 CarrY (CY) PSW.6 Aux Carry (AC) PSW.5 Flag 0 (F0) PSW.4 Register Bank Select 1 PSW.3 Register Bank Select 0 PSW.2 Overflow(OV) PSW.1 reserved PSW.0 Even Parity Flag (P)

Commonly used SFRs

Accumulator, it has two names, A and ACC. Many instruction make use of the accumulator, eg: mov A,R0, push acc SP, always pointing to the top of the stack, increasing by 1 before write to stack, decreasing by 1 after read from stack

Fig 3-0 B Pin Configuration

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0 RXD P3.1 TXD P3.2 INT0 P3.3 INT1 P3.4 T0 P3.5 T1 P3.6 WR P3.7 RD XTAL2 XTAL1 VSS VCC AD0 P0.0 AD1 P0.1 AD2 P0.2 AD3 P0.3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Input/Output (I/O) Ports

In the SFR, register P0, P1, P2, P3 are connected to the physical pin on the uP Some of 0 the Port pin PORT 2 1 3 serve an alternative by name addressed function P2, P1, individual P3, PO, individualpin pin P2.0 P1.0 to P2.7 P3.0 P1.7 P3.7 P0.0 P0.7

80C31

AD4 P0.4 AD5 P0.5 AD6 P0.6 AD7 P0.7 EA/VPP

ALE/PROG PSE N A15 P2.7 A14 P2.6 A13 P2.5 A12 P2.4 A11 P2.3 A10 P2.2 A9 P2.1 A8 P2.0

Accessing External Code Memory

If the design involves external code memory, both P0 and P2 should not be used as general purpose I/O since P2 is now the Higher address bus while P0 is the multiplexed Lower address bus and the data bus. _____ As stated earlier, the PSEN pin must be used. See fig 2-9

FIGURE 28

Multiplexing the address bus (low-byte) and data bus

FIGURE 29

Accessing external code memory

An opcode fetch for 2-byte instruction

Fig.2-10 shows what happens during an opcode fetch for a 2 byte instruction that has a time of 1 machine cycle.

FIGURE 210

Read timing for external code memory

Accessing External RAM

For designs with external RAM, a typical connection is shown in fig.2-12. Note the control lines that must be used. MOVX instruction is used to indicate that the external RAM is involved. e.g. MOVX A, @dptr ( a read operation) e.g. MOVX @dptr, A (a write operation)

 The timing diagram for a read operation is shown in fig 2-11.

FIGURE 211

Timing for MOVX instruction

FIGURE 212

Interface to 1K RAM

Reset Operation
To reset the 8051, the RST pin must be held high for at least 2 machine cycles. This can be achieved upon powerup using an RC network. Fig.2-16 shows 2 circuits for achieving this, one is a manual reset, the other is a poweron reset. How does the 2 circuit works?
Try to remember capacitor is open during steady-state.

FIGURE 216

Two circuits for system reset. (a) Manual reset (b) Power-on reset.