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Chapter 3 : Combinational Logic Circuits (Part 1) | Digital Electronics

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Home Topics Chapter 1 : Number System and Binary Code (Part 1) Chapter 1 : Part 2 Chapter 2 : Minimization of Logic Function (Part 1) Chapter 2 : Part 2 Chapter 3 : Combinational Logic Circuits (Part 1) Chapter 3 : Part 2 Chapter 4 : Sequential Circuits (Part 1) Chapter 4 : Part 2 Chapter 5 : D/A and A/D Converters (Part 1) Chapter 5 : Part 2 Chapter 6 : Semiconductor Memories Chapter 7 : Logic Families

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Chapter 3 : Combinational Logic Circuits (Part 1)

Remember These:

C o mb i n a t i o n a l c i r c u i t sa r ea d d e r ss u b t r a c t o r smu l t i p l e x e r sd e mu l t i p l e x e r , ma g n i t u d e c o mp a r a t o r , p a r i t yg e n e r a t o r / c h e c k e r e t c . A r i t h me t i cc i r c u i t sa r eu s e df o r a d d i t i o n , s u b t r a c t i o nmu l t i p l i c a t i o nd i v i s i o n H a l f a d d e r i su s e df o r a d d i t i o no f t wob i n a r yn u mb e r s . F u l l a d d e r i su s e dt op e r f o r ma d d i t i o no f mo r et h a r r 2b i t s S e r i a l a d d e rr e q u i r eo n ef u l l a d d e r f o r o n ea d d i t i o n a l b i t wh i l ep a r a l l e l a d d e r sr e q u i r e sN f u l l a d d e r sf o r nb i t a d d i t i o n . T womo r ea d d e r sa r el o o ka h e a dc a r r ya d d e r a n dB C Da d d e r . H a l fs u b t r a c t o rs u b t r a c t st wo n u mb e r s we g e t2 o u t p u tv a r i a b l e s ie d i f f e r e n c ea n d b o r r o w F u l l s u b t r a c t o r i ss u b t r a c t i o no f 3b i t s . E n c o d e r c o n v e r t sh u ma nl a n g u a g ei n t oma c h i n el a n g u a g e . D e c o d e r i su s e dt oc o n v e r t ma c h i n el a n g u a g et oh u ma nl a n g u a g e . Mu l t i p l e x e r sa r eu n i v e r s a l c i r c u i t swh i c hs e l e c t so n ei n p u t o u t o f mu l t i p l ei n p u t sa n dg i v e i t a sar e s u l t D e mu l t i p l e x e r r e c e i v e si n f o r ma t i o no ns i n g l el i n ea n dd i s t r i b u t et ot h e2l i n e swh e r en a r es e l e c t i o nl i n e s . Ma g n i t u d ec o mp a r a t o r i su s e dt oc o mp a r e2b i n a r yn u mb e r s C o d ec o n v e r t e r sa r et h o s e wh i c hc o n v e r t sa g i v e nc o d et os o me o t h e rc o d eE x a mp l e s a r e : ( a ) G r a yt oB i n a r yc o d ec o n v e r t e r ( b ) B i n a r yt oG r a yc o d ec o n v e r t e r ( c ) B i n a r yt oE x c e s s3c o d ec o n v e r t e r e t c . P a r i t yg e n e r a t o r i sal o g i cc i r c u i t wh i c hg e n e r a t e st h ep a r i t yb i t sf o r e v e no r o d dp a r i t y P a r i t yg e n e r a t o r i su s e da t t h et r a n s mi t t e r . P a r i t yc h e c k e r i su s e da t t h er e c e i v e r . B C Dd i s p l a yd r i v ei sb a s i c a l l yt h eB C Dt os e v e ns e g me n t d i s p l a yc o d ec o n v e r t e rI nt h i s b i n a r yc o d e dd e c i ma l i sd i s p l a y e do nt h es e v e ns e g me n t d i s p l a y s

Q 1. List the applications of decoders. Ans. 1D e c o d e r sa r eu s e di nc o u n t e r s y s t e ms 2 . D e c o d e r sa r eu s e df o r A / Dc o n v e r s i o n . 3D e c o d e r sa r eu s e df o r D / Ac o n v e r s i o n 4 . D e c o d e r sa r eu s e di ns e v e ns e g me n t d i g i t a l d i s p l a y s .

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Q 2 Give functional block diagram of 2 1 MUX Ans.

Q 3 Explain half subtractor with the help of its internal circuit Ans. T os u b t r a c t t won u mb e r si et woI n p u t v a r i a b l e sAa n dB weg e t t woo u t p u t v a r i a b l ei ed i f f e r e n c e D a n db o r r o w B o I t i sk n o wna sh a l f s u b t r a c t o r F u n c t i o n a l d i a g r a mi ss h o wn :

Its truth table is as shown:

T h u s , t h emi n i mi z e dl o g i cf u n c t i o n sa r e :

T h ec i r c u i t d i a g r a mi sa ss h o wn :

Q 4. Implement half adder circuit using 4 : 1 MUX or multiplexers only. Ans. T r u t ht a b l eo f h a l f a d d e r i sa ss h o wn :

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Q 5. Implement using 4: 1 MUX Ans. T h ei mp l e me n t a t i o nt a b l ei sa ss h o wn :

Implementation:

Q 6. Design 3 bit Gray Code to binary converters Ans. T h et r u t ht a b l ef o r 3b i t G r a yC o d et ob i n a r yc o n v e r s i o ni sa ss h o wn :

K-Maps: For 82:

For B1:

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For Bo:

C i r c u i t I mp l e me n t a t i o ni sa ss h o wn :

Q 7. Design BCD to Excess-3 code converter. Ans. BCD to Excess-3 Code Converter: T h ei n p u t v a r i a b l e sa r eB C D s( A , B , Ca n dD )a n do u t p u t v a r i a b l e sa r ee x c e s s 3c o d e( E 3 , E 2 , E 1a n dE 0 )

Truth Table

A f t e r 9 i . e . 1 0 0 1B C D , ma r kd o n t c a r ei . e . X . Mi n i mi z a t i o nU s i n gK ma p : F o r E 3

E 3= A+ B D+ B S
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F o r E 2

F o r E 1

F o r E 0

Implementation of Excess-3 Code Converter:

Q 8. Draw the logic circuit for the expression Ans.

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L o g i cc i r c u i t r e p r e s e n t a t i o n .

Q 9 Draw the logic circuit for 3 line to 8 line decoder Ans. 3l i n et o8l i n ed e c o d e r c i r c u i t i sa ss h o wn :

I t h a st h r e ei n p u t l i n e si . e . A , Ba n dC a n dh a se i g h t o u t p u t l i n e s i . e . D 0 , D 1 , D 2 , D 3 , D 4 , D 5 , D 6a n dD 7

Q 10 Draw the logic circuit for the expression Ans Logic Circuit:

Q 11. Give significance of priority encoder. Ans. P r i o r i t ye n c o d e r i nas p e c i a l t y p eo f e n c o d e r . I t h a sp r i o r i t i e sg i v e nt ot h ei n p u t l i n e s f r o mh i g h e s tp r i o r i t yi n p u tl i n et ol o we s tp r i o r i t yi n p u t l i n e ,I f t wo o rmo r ei n p u tl i n e sa r e a c t i v ei . e . 1 o rh i g ha tt h es a me t i me ,t h e nt h ei n p u tl i n e wi t hh i g h e s tp r i o r i t y wi l l b e c o n s i d e r e df i r s t .

Q 12. How many select lines are there for a 30 to 1 MUX? Ans. F o r 3 0 : 1MU X , 5s e l e c t l i n e sa r er e q u i r e d . 4s e l e c t l i n e sa r ef o r 1 6: 1MU X sa n d
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1s e l e c t l i n ef o r2 : 1MU X .

=M f o r mu l ai su s e d . Wh e r en= n u mb e r o f s e l e c t l i n e sa n dM

a r et h en u mb e r o f i n p u t sf o r aMU X . =3 2 . T h u s , 5s e l e c t l i n e sa r en e e d e d .

Q 13. What are the various type of parity checkers and where do we use them? Ans. P a r i t yc h e c k e r sa r eu s e da t t h er e c e i v e r p a r t . T h e yc h e c kt h ep a r i t yo f t h er e c e i v e d wo r da n dp r o d u c e si t so u t p u t . B r o a d l yp a r i t yc h e c k e r sa r eo f t wot y p e s . ( i ) O d dp a r i t yc h e c k e r ( i i ) E v e np a r i t yc h e c k e r .

Q 14. Design full subtractor using NAND gates. Ans. F u l l s u b t r a c t o r i su s e dt os u b t r a c t t h r e eb i t sa n dg e n e r a t ed i f f e r e n c ea n db o r r o w. T r u t h t a b l eo f f u l l s u b t r a c t o r i s :

Q 15. Construct 16-bit comparator using 4-bit comparator as a building block. Ans. 4b i t c o mp a r a t o r I Ci n7 4 8 5 . I t i su s e df o r 1 6b i t c o mp a r a t o r . T h u s , 4I C Sa r eu s e d , wh i c hi sa ss h o wn :

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Q 16. How can a DEMUX be used as a decoder? Ans. T h es e l e c t i o nl i n e so f t h eD E MU Xc a nb eu s e da si n p u t l i n e so f d e c o d e r a n di f t h e d a t ai n p u t o f t h ed e mu l t i p l e x e r i su s e da st h ee n a b l ei n p u t o f t h ed e c o d e rt h e nwec a nu s e t h ed e mu l t i p l e x e r a sad e c o d e r . Q 17. What is a parity checker? Ans. P a r i t yc h e c k e r i sal o g i cc i r c u i t t h a t c h e c k st h ep a r i t yb i n a r ywo r d . Ap a r i t yb i t i sa n a d d i t i o n a l b i t wh i c hi sa d d e dt oab i n a r ywo r di no r d e rt oma k et h en u mb e ro f o n e si nt h e n e w wo r df o r ma t a se v e nf o r e v e np a r i t ya n do d df o r o d dp a r i t y . Q 18. Obtain the truth table for a combinational circuit that accepts a three bit number and generates an output binary number equal to the square of the input number. Ans. T r u t ht a b l ei sa ss h o wnf o r i n p u t sa n dt h ec o r r e s p o n d i n gs q u a r eo u t p u t s .

Q 19. Implement using 4 x 1 MUX

Ans.

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Q 20 Describe the operations performed by an encoder and a decoder. Ans. Operations Performed by Encoder: 1E n c o d e ri sa c o mb i n a t i o n a l c i r c u i twh i c he n c o d e so n ed i g i t a l i n p u tc o d et ot h e m d i g i t a l o u t p u t c o d el i k eo c t a l t ob i n a r ye n c o d e r D e c i ma l t oB C De n c o d e r e t c 2I t p r o v i d e st h es e c u r i t yf o r t h ed a t ab ye n c o d i n gi t 3I t s a v e st h eb a n d wi d t ho v e r t h ec h a n n e l s Operations Performed by Decoder 1Ad e c o d e ri sac o mb i n a t i o n a l c i r c u i t , t h a t c o n v e r t sni n p u t b i n a r yi n f o r ma t i o nt o2o u t p u t l i n e seg2t o4l i n ed e c o d e r 3t o8l i n ed e c o d e r e t c 2I t i su s e da t t h er e c e i v e r p a r t t od e c o d et h ei n f o r ma t i o n Q 21. Implement the following function using 3 to 8 decoder

Ans. I mp l e me n t a t i o nu s i n g3t o8d e c o d e r :

Q 22 Define a demultiplexer Show how to convert a decoder into a demultiplexer indicate how to add a strobe to this system OR What is demultiplexer Explain the difference between DMIJX and MUX Ans. Demultiplexer:D e mu l t i p l e x e ri sad e v i c ewh i c hh a ss i n g l ei n p u t l i n ea n d ma n yi e o u t p u tl i n e sT h er e l a t i o no f s p e c i f i co u t p u t l i n ei sc o n t r o l l e db yt h ev a l u eo f n s e l e c t i o n l i n e sI t p e r f o r mst h ei n v e r s eo p e r a t i o no f mu l t i p l e x e r I nc a s eo f d e c o d e r , i t h a sni n p u t l i n e sa n d u n i q u eo u t p u t l i n e sL e t u st a k ea ne x a mp l eo f 2t o4l i n ed e c o d e r t oc o n v e r t t h ed e c o d e r i n t oad e mu l t i p l e x e r . 2t o4l i n eD e c o d e r :

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I t c a nb ec o n v e r t e di n t od e mu l t i p l e x e ri f D 1i ed a t aI n p u t l i n ei sc o n v e r t e dt oa l l t h eA N D g a t e ss i mu l t a n e o u s l y . S t r o k es i g n a l i sa l s oa d d e dt oa l l t h eA N Dg a t e ss i mu l t a n e o u s l ya ss h o wni nf i g .

S t r o b es i g n a l i ss i mi l a rt oe n a b l es i g n a l f o rc h i ps e l e c t i o n . I t i sa na c t i v el o ws i g n a l . I f h i g h s i g n a l i sa p p l i e dt os t r o k et h ec h i pwi l l b ed i s a b l eb e c a u s ei = 0g o e st oa l l t h eA N Dg a t e s A n dwer e c e i v en oo u t p u t a t D 0 , D 1 , D 2a n dD 3 Difference between DMUX and MUX:

Q 23 Design a Gray-to Excess-3 Code converter using NAND gates Ans. G r a yt oE x c e s s 3c o d ec o n v e r t e r :

K-maps for Excess 3-codes are

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Circuit Diagram:

Q 24. Design a 3-bit carry-look-ahead adder. Ans. 3-bit look ahead adder : T h eb i t l o o ka h e a dc a r r ya d d e r s p e e d su pT h ep r o c e s sb y e l i mi n a t i n gr i p p l ec a r r yd e l a y . I t e x a mi n e sa l l t h ei n p u t b i t ss i mu l t a n e o u s l ya n dg e n e r a t e s c a r r y i n b i t sf o ra l l s t a g e ss i mu l t a n e o u s l y .I ti sd o n e wi t ht wo a d d i t i o n a l f u n c t i o n sc a r r y g e n e r a t ea n dc a r r yp r o p a g a t ef u n c t i o n . T h ec a r r yg e n e r a t ef u n c t i o ni n d i c a t e sa st owh e nac a r r y o u two u l db eg e n e r a t e db yf u l l a d d e r .A c a r r y o u ti sg e n e r a t e do n l y wh e nb o t ht h ei n p u t sb i t sa r e1 .T h i sc o n d i t i o ni s e x p r e s s e da st h eA N Df u n c t i o no f t h et wob i t sAa n dB . C a r r yg e n e r a t e( C G ) = A. B C a r r yp r o p a g a t e( G P ) =A B

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