Ee101 Basics 1

EE101: Basics KCL, KVL, power, Thevenins theorem
M. B. Patil
mbpatil@ee.iitb.ac.in Department of Electrical Engineering Indian Institute of Technology Bombay
M. B. Patil, IIT Bombay
Kirchhos laws
A i2 v2
v4
v3 R2 i3 v6 R1 v1 i1
B i6 V0
v4 R3 i4 v5
C i5 I0
Kirchhos laws
A i2 v2
v4
v3 R2 i3 v6 R1 v1 i1
B i6 V0
v4 R3 i4 v5
C i5 I0
* Kirchhos current law (KCL): P ik = 0 at each node.
Kirchhos laws
A i2 v2
v4
v3 R2 i3 v6 R1 v1 i1
B i6 V0
v4 R3 i4 v5
C i5 I0
* Kirchhos current law (KCL): P ik = 0 at each node. e.g., at node B, i3 + i6 + i4 = 0.
Kirchhos laws
A i2 v2
v4
v3 R2 i3 v6 R1 v1 i1
B i6 V0
v4 R3 i4 v5
C i5 I0
* Kirchhos current law (KCL): P ik = 0 at each node. e.g., at node B, i3 + i6 + i4 = 0. (We have followed the convention that current leaving a node is positive.)
Kirchhos laws
A i2 v2
v4
v3 R2 i3 v6 R1 v1 i1
B i6 V0
v4 R3 i4 v5
C i5 I0
* Kirchhos current law (KCL): P ik = 0 at each node. e.g., at node B, i3 + i6 + i4 = 0. (We have followed the convention that current leaving a node is positive.) * Kirchhos voltage law (KVL): P vk = 0 for each loop.
Kirchhos laws
A i2 v2
v4
v3 R2 i3 v6 R1 v1 i1
B i6 V0
v4 R3 i4 v5
C i5 I0
* Kirchhos current law (KCL): P ik = 0 at each node. e.g., at node B, i3 + i6 + i4 = 0. (We have followed the convention that current leaving a node is positive.) * Kirchhos voltage law (KVL): P vk = 0 for each loop. e.g., v3 + v6 v1 v2 = 0.
Kirchhos laws
A i2 v2
v4
v3 R2 i3 v6 R1 v1 i1
B i6 V0
v4 R3 i4 v5
C i5 I0
* Kirchhos current law (KCL): P ik = 0 at each node. e.g., at node B, i3 + i6 + i4 = 0. (We have followed the convention that current leaving a node is positive.) * Kirchhos voltage law (KVL): P vk = 0 for each loop. e.g., v3 + v6 v1 v2 = 0. (We have followed the convention that voltage drop across a branch is positive.)
Circuit elements
Element Resistor
Symbol
v i
Equation v =Ri v =L di dt dv dt
Inductor
i
Capacitor
i
i =C
v i
C
Diode BJT
to be discussed to be discussed
E
Sources
Element Independent Voltage source Current source Dependent VCVS VCCS CCVS CCCS
Symbol
v i v i v i v i v i v i
Equation v (t ) = vs (t ) i (t ) = is (t ) v (t ) = vc (t ) i (t ) = g vc (t ) v (t ) = r ic (t ) i (t ) = ic (t )
* , : dimensionless, r : , g : 1 or
(mho)
* The subscript c denotes the controlling voltage or current.

Instantaneous power absorbed by an element
i1 V1 VN iN
i2 V2 V3 i3
P (t ) = V 1 (t ) i 1 (t ) + V 2 (t ) i 2 (t ) + + V N (t ) i N (t ) , where V1 , V2 , etc. are node voltages (measured with respect to a reference node).
i1 V1 VN iN
i2 V2 V3 i3
* two-terminal element:
v V1 i1 i2 V2
P = V1 i 1 + V2 i 2 = V 1 i 1 + V 2 ( i 1 ) = [V 1 V 2 ] i 1 = v i 1
i1 V1 VN iN
i2 V2 V3 i3
* two-terminal element:
v V1 i1 i2 V2
P = V1 i 1 + V2 i 2 = V 1 i 1 + V 2 ( i 1 ) = [V 1 V 2 ] i 1 = v i 1 P = V B i B + V C i C + V E ( i E )
iC iE
* three-terminal element:
VC VB iB VE
= V B i B + V C i C V E (i B + i C ) = (VB VE ) iB + (VC VE ) iC = VBE iB + VCE iE
Instantaneous power
* A resistor can only absorb power (from the circuit) since v and i have the same sign, making P > 0. The energy absorbed by a resistor goes in heating the resistor and the rest of the world.
Instantaneous power
* A resistor can only absorb power (from the circuit) since v and i have the same sign, making P > 0. The energy absorbed by a resistor goes in heating the resistor and the rest of the world. * Often, a heat sink is provided to dissipate the thermal energy eectively so that the device temperature does not become too high.
Instantaneous power
* A resistor can only absorb power (from the circuit) since v and i have the same sign, making P > 0. The energy absorbed by a resistor goes in heating the resistor and the rest of the world. * Often, a heat sink is provided to dissipate the thermal energy eectively so that the device temperature does not become too high. * A source (e.g., a DC voltage source) can absorb or deliver power since the signs of v and i are independent. For example, when a battery is charged, it absorbs energy which gets stored within.
Instantaneous power
* A resistor can only absorb power (from the circuit) since v and i have the same sign, making P > 0. The energy absorbed by a resistor goes in heating the resistor and the rest of the world. * Often, a heat sink is provided to dissipate the thermal energy eectively so that the device temperature does not become too high. * A source (e.g., a DC voltage source) can absorb or deliver power since the signs of v and i are independent. For example, when a battery is charged, it absorbs energy which gets stored within. * A capacitor can absorb or deliver power. When it is absorbing power, its charge builds up. Similarly, an inductor can store energy (in the form of magnetic ux).
Resistors in series
v1
A
v2 R2
v3
B A
v i
B
R1
R3
Resistors in series
v1
A
v2 R2
v3
B A
v i
B
R1
R3
v1 = i R1 , v2 = i R2 , v3 = i R3 , v = v1 + v2 + v3 = i (R1 + R2 + R3 )
Resistors in series
v1
A
v2 R2
v3
B A
v i
B
R1
R3
v1 = i R1 , v2 = i R2 , v3 = i R3 , v = v1 + v2 + v3 = i (R1 + R2 + R3 ) * The equivalent resistance is Req = R1 + R2 + R3 .
Resistors in series
v1
A
v2 R2
v3
B A
v i
B
R1
R3
v1 = i R1 , v2 = i R2 , v3 = i R3 , v = v1 + v2 + v3 = i (R1 + R2 + R3 ) * The equivalent resistance is Req = R1 + R2 + R3 . * The voltage drop across Rk is v Rk . Req
Resistors in parallel
v i1
A
R1
B A
v i
B
i2 i3
R2 R3
v i1
A
R1
B A
v i
B
i2 i3
R2 R3
i1 = G1 v , i2 = G2 v , i3 = G3 v , where G1 = 1/R1 , etc. i = i1 + i2 + i3 = (G1 + G2 + G3 ) v .
v i1
A
R1
B A
v i
B
i2 i3
R2 R3
i1 = G1 v , i2 = G2 v , i3 = G3 v , where G1 = 1/R1 , etc. i = i1 + i2 + i3 = (G1 + G2 + G3 ) v . * The equivalent conductance is Geq = G1 + G2 + G3 , and the equivalent resistance is Req = 1/Geq .
v i1
A
R1
B A
v i
B
i2 i3
R2 R3
i1 = G1 v , i2 = G2 v , i3 = G3 v , where G1 = 1/R1 , etc. i = i1 + i2 + i3 = (G1 + G2 + G3 ) v . * The equivalent conductance is Geq = G1 + G2 + G3 , and the equivalent resistance is Req = 1/Geq . * The current through Rk is i Gk . Geq
v i1
A
R1
B A
v i
B
i2 i3
R2 R3
* If N = 2, we have R1 R2 R2 R1 Req = , i1 = i , i2 = i . R1 + R2 R1 + R2 R1 + R2
v i1
A
R1
B A
v i
B
i2 i3
R2 R3
* If N = 2, we have R1 R2 R2 R1 Req = , i1 = i , i2 = i . R1 + R2 R1 + R2 R1 + R2 * If Rk = 0, all of the current will go through Rk .

Example
i1 4 3 6V i2
5
(a)
2.5
2.5
Example
i1 4 3 6V i2
5
(a)
2.5
2.5
Example
i1 4 3 6V i2
i1 4 i2 3 5 2.5 2.5
(b)
2 1 3
6V
(a)
Example
i1 4 3 6V i2
i1 4 i2 3 5 2.5 2.5
(b)
2 1 3
6V
(a)
Example
i1 4 3 6V i2
i1 4 i2 3 5 2.5 2.5
(b)
2 1 3
6V
(a)
i1 4 6V
(c)
i2 6 3
Example
i1 4 3 6V i2
i1 4 i2 3 5 2.5 2.5
(b)
2 1 3
6V
(a)
i1 4 6V
(c)
i2 6 3
Example
i1 4 3 6V i2
i1 4 i2 3 5 2.5 2.5
(b)
2 1 3
6V
(a)
3 i1 4 6V i2 6 3
(d)
i1
4 2 6V
(c)
Example
i1 4 3 6V i2
i1 4 i2 3 5 2.5 2.5
(b)
2 1 3
6V
(a)
3 i1 4 6V i2 6 3
(d)
i1
4 2 6V
i1 =
6V = 1A. 4+2
(c)
Example
i1 4 3 6V i2
i1 4 i2 3 5 2.5 2.5
(b)
2 1 3
6V
(a)
3 i1 4 6V i2 6 3
(d)
i1
4 2 6V
i1 =
6V = 1A. 4+2
2 6 = A. i2 = i1 6+3 3
(c)
Example
i1 4 3 6V i2
i1 4 i2 3 5 2.5 2.5
(b)
2 1 3
6V
(a)
3 i1 4 6V i2 6 3
(d)
i1
4 2 6V
i1 =
6V = 1A. 4+2
2 6 = A. i2 = i1 6+3 3
(c)
Home work: * Verify that KCL and KVL are satised for each node/loop.
Example
i1 4 3 6V i2
i1 4 i2 3 5 2.5 2.5
(b)
2 1 3
6V
(a)
3 i1 4 6V i2 6 3
(d)
i1
4 2 6V
i1 =
6V = 1A. 4+2
2 6 = A. i2 = i1 6+3 3
(c)
Home work: * Verify that KCL and KVL are satised for each node/loop. * Verify that the total power absorbed by the resistors is equal to the power supplied by the source.
Nodal analysis
V1
R1 R2
V2 R3 v3 k v3
I0
0
R4
V3
Nodal analysis
* Take some node as the reference node and denote the node voltages of the remaining nodes by V1 , V2 , etc.
V1
R1 R2
V2 R3 v3 k v3
I0
0
R4
V3
Nodal analysis
* Take some node as the reference node and denote the node voltages of the remaining nodes by V1 , V2 , etc. * Write KCL at each node in terms of the node voltages. Follow a xed convention, e.g., current leaving a node is positive.
V2 R3 v3 k v3 0 R4 V3
V1
R1 R2
I0
Nodal analysis
V2 R3 v3 k v3 0 R4 V3
V1
R1 R2
I0
1 ( V 1 V 2 ) I0 k ( V 2 V 3 ) = 0 , R1 1 1 1 (V 2 V 1 ) + (V 2 V 3 ) + (V 2 ) = 0 , R1 R3 R2 1 1 k (V 2 V 3 ) + (V 3 V 2 ) + (V 3 ) = 0 . R3 R4
Nodal analysis
V2 R3 v3 k v3 0 R4 V3
V1
R1 R2
I0
1 ( V 1 V 2 ) I0 k ( V 2 V 3 ) = 0 , R1 1 1 1 (V 2 V 1 ) + (V 2 V 3 ) + (V 2 ) = 0 , R1 R3 R2 1 1 k (V 2 V 3 ) + (V 3 V 2 ) + (V 3 ) = 0 . R3 R4 * Solve for the node voltages branch voltages and currents.
Nodal analysis
V2 R3 v3 k v3 0 R4 V3
V1
R1 R2
I0
1 ( V 1 V 2 ) I0 k ( V 2 V 3 ) = 0 , R1 1 1 1 (V 2 V 1 ) + (V 2 V 3 ) + (V 2 ) = 0 , R1 R3 R2 1 1 k (V 2 V 3 ) + (V 3 V 2 ) + (V 3 ) = 0 . R3 R4 * Solve for the node voltages branch voltages and currents. * Remark: Nodal analysis needs to be modied if there are voltage sources.
Mesh analysis
R1
R2
Vs i1 is
R3 i2
r1 is
Mesh analysis
R1
R2
Vs i1 is
R3 i2
r1 is
* Write KVL for each loop in terms of the mesh currents i1 and i2 . Use a xed convention, e.g., voltage drop is positive. (Note that is = i1 i2 .)
Mesh analysis
R1
R2
Vs i1 is
R3 i2
r1 is
* Write KVL for each loop in terms of the mesh currents i1 and i2 . Use a xed convention, e.g., voltage drop is positive. (Note that is = i1 i2 .) Vs + i1 R1 + (i1 i2 ) R3 = 0 , R2 i2 + r1 (i1 i2 ) + (i2 i1 ) R3 = 0 .
Mesh analysis
R1
R2
Vs i1 is
R3 i2
r1 is
* Write KVL for each loop in terms of the mesh currents i1 and i2 . Use a xed convention, e.g., voltage drop is positive. (Note that is = i1 i2 .) Vs + i1 R1 + (i1 i2 ) R3 = 0 , R2 i2 + r1 (i1 i2 ) + (i2 i1 ) R3 = 0 . * Solve for i1 and i2 compute other quantities of interest (branch currents and branch voltages).
Linearity and superposition
* A circuit containing independent sources, dependent sources, and resistors is linear, i.e., the system of equations describing the circuit is linear.
* A circuit containing independent sources, dependent sources, and resistors is linear, i.e., the system of equations describing the circuit is linear. * The dependent sources are assumed to be linear, e.g., if we have a CCVS with 2 + b , the resulting system will be no longer linear. v = a ic
* A circuit containing independent sources, dependent sources, and resistors is linear, i.e., the system of equations describing the circuit is linear. * The dependent sources are assumed to be linear, e.g., if we have a CCVS with 2 + b , the resulting system will be no longer linear. v = a ic * For a linear system, we can apply the principle of superposition.
* A circuit containing independent sources, dependent sources, and resistors is linear, i.e., the system of equations describing the circuit is linear. * The dependent sources are assumed to be linear, e.g., if we have a CCVS with 2 + b , the resulting system will be no longer linear. v = a ic * For a linear system, we can apply the principle of superposition. * In the context of circuits, superposition enables us to consider the independent sources one at a time, compute the desired quantity of interest in each case, and get the net result by adding the individual contributions.
* A circuit containing independent sources, dependent sources, and resistors is linear, i.e., the system of equations describing the circuit is linear. * The dependent sources are assumed to be linear, e.g., if we have a CCVS with 2 + b , the resulting system will be no longer linear. v = a ic * For a linear system, we can apply the principle of superposition. * In the context of circuits, superposition enables us to consider the independent sources one at a time, compute the desired quantity of interest in each case, and get the net result by adding the individual contributions. * Caution: Superposition cannot be applied to dependent sources.
Superposition
* Superposition refers to superposition of response due to independent sources.
Superposition
* Superposition refers to superposition of response due to independent sources. * We can consider one independent source at a time, deactivate all other independent sources.
Superposition
* Superposition refers to superposition of response due to independent sources. * We can consider one independent source at a time, deactivate all other independent sources. * Deactivating a current source is = 0, i.e., replace the current source with an open circuit.
Superposition
* Superposition refers to superposition of response due to independent sources. * We can consider one independent source at a time, deactivate all other independent sources. * Deactivating a current source is = 0, i.e., replace the current source with an open circuit. * Deactivating a voltage source vs = 0, i.e., replace the voltage source with a short circuit.
Example
2 i1 18 V 4 3A
Example
Case 1: Keep Vs , deactivate Is . 2 2 i1 18 V 4 3A 4 18 V i1
Example
Case 1: Keep Vs , deactivate Is . 2 2 i1 18 V 4 3A 4 18 V i1 (1) i1 = 3 A
Example
Case 1: Keep Vs , deactivate Is . 2 2 i1 18 V 4 3A Case 2: Keep Is , deactivate Vs . 2 i1 4 3A 4 18 V i1 (1) i1 = 3 A
Example
Case 1: Keep Vs , deactivate Is . 2 2 i1 18 V 4 3A Case 2: Keep Is , deactivate Vs . 2 i1 4 3A (2) i1 = 3 A 2 = 1A 2+4 4 18 V i1 (1) i1 = 3 A
Example
Case 1: Keep Vs , deactivate Is . 2 2 i1 18 V 4 3A Case 2: Keep Is , deactivate Vs . 2 (1) (2) inet 1 = i1 + i1 = 3 + 1 = 4 A i1 4 3A (2) i1 = 3 A 2 = 1A 2+4 4 18 V i1 (1) i1 = 3 A
Example
i 1
12 V
6A 2i
Example
Case 1: Keep Vs , deactivate Is .
i 1 i 1 6A 2i 12 V v 3
12 V
2i
Example
i 1 i 1 6A 2i 12 V v 3
12 V
3 KVL: 12 + 3 i + 2 i + i = 0 i = 2 A , v(1) = 6 V .
2i
Example
i 1 i 1 6A 2i 12 V v 3
12 V
3 KVL: 12 + 3 i + 2 i + i = 0 i = 2 A , v(1) = 6 V .
2i
Case 2: Keep Is , deactivate Vs .
i 1
6A 2i
Example
i 1 i 1 6A 2i 12 V v 3
12 V
3 KVL: 12 + 3 i + 2 i + i = 0 i = 2 A , v(1) = 6 V .
2i
i 1
3 KVL: i + (6 + i) 3 + 2 i = 0 6A i = 3 A , v(2) = (3 + 6) 3 = 9 V .
2i
Example
i 1 i 1 6A 2i 12 V v 3
12 V
3 KVL: 12 + 3 i + 2 i + i = 0 i = 2 A , v(1) = 6 V .
2i
vnet = v(1) + v(2) = 6 + 9 = 15 V
i 1
3 KVL: i + (6 + i) 3 + 2 i = 0 6A i = 3 A , v(2) = (3 + 6) 3 = 9 V .
2i
Superposition: Why does it work?
V1 R1 Vs 0 A R2 R3
V2 B Is
V1 R1 Vs 0 A R2 R3
V2 B Is
KCL at nodes A and B: 1 1 1 (V 1 V s ) + V1 + (V 1 V 2 ) = 0 , R1 R2 R3 1 (V 2 V 1 ) = 0 . Is + R3
V1 R1 Vs 0 A R2 R3
V2 B Is
KCL at nodes A and B: 1 1 1 (V 1 V s ) + V1 + (V 1 V 2 ) = 0 , R1 R2 R3 1 (V 2 V 1 ) = 0 . Is + R3 Writing in a matrix form, we get (using G1 = 1/R1 , etc.), G1 + G2 + G3 G3 G3 G3 V1 V2 = G1 Vs Is
V1 R1 Vs 0 A R2 R3
V2 B Is
KCL at nodes A and B: 1 1 1 (V 1 V s ) + V1 + (V 1 V 2 ) = 0 , R1 R2 R3 1 (V 2 V 1 ) = 0 . Is + R3 Writing in a matrix form, we get (using G1 = 1/R1 , etc.), G1 + G2 + G3 G3 i.e., A V1 V2 = G3 G3 G1 Vs Is V1 V2 V1 V2 = G1 Vs Is
1
=A
G1 Vs Is
V1 R1 Vs 0 A R2 R3
V2 B Is
V1 V2
=A
G1 Vs Is
m11 m21
m12 m22
G1 Vs Is
V1 R1 Vs 0 A R2 R3
V2 B Is
V1 V2
=A
G1 Vs Is
m11 m21
m12 m22
G1 Vs Is
We are now in a position to see why superposition works. V1 V2 = m11 G1 m21 G1 m12 m22 Vs 0 m11 G1 + m21 G1 m12 m22 0 Is " V1 V2
(1) (1)
# " +
V1 V2
(2) (2)
# .
V1 R1 Vs 0 A R2 R3
V2 B Is
V1 V2
=A
G1 Vs Is
m11 m21
m12 m22
G1 Vs Is
(1) (1)
# " +
V1 V2
(2) (2)
# .
The rst vector is the response due to Vs alone (and Is deactivated). The second vector is the response due to Is alone (and Vs deactivated).
V1 R1 Vs 0 A R2 R3
V2 B Is
V1 V2
=A
G1 Vs Is
m11 m21
m12 m22
G1 Vs Is
(1) (1)
# " +
V1 V2
(2) (2)
# .
The rst vector is the response due to Vs alone (and Is deactivated). The second vector is the response due to Is alone (and Vs deactivated). All other currents and voltages are linearly related to V1 and V2 Any voltage (node voltage or branch voltage) or current can also be computed using superposition.
Thevenins theorem
Circuit
(resistors, voltage sources, current sources, CCVS, CCCS, VCVS, VCCS)
Thevenins theorem
RTh
Circuit
VTh
B B
Thevenins theorem
RTh
Circuit
VTh
B B
* VTh is simply VAB when nothing is connected on the other side, i.e., VTh = Voc .
Thevenins theorem
RTh
Circuit
VTh
B B
* VTh is simply VAB when nothing is connected on the other side, i.e., VTh = Voc . * RTh can be found by dierent methods.
Thevenins theorem: RTh
Method 1:
Circuit
RTh
A A
VTh
B B
* Deactivate all independent sources.
Method 1:
Circuit
RTh
A A
VTh
B B
Circuit
RTh
A A
* Deactivate all independent sources.
Method 1:
Circuit
RTh
A A
VTh
B B
Circuit
RTh
A A
* Deactivate all independent sources. * RTh can often be found by inspection.
Method 1:
Circuit
RTh
A A
A Is
VTh Vs
B B B
Circuit
RTh
A A
* Deactivate all independent sources. * RTh can often be found by inspection. * RTh may be found by connecting a test source.
Method 1:
Circuit
RTh
A A
A Is
VTh Vs
B B B
Circuit
RTh
A A
Vs Is
B B B
Method 1:
Circuit
RTh
A A
A Is
VTh Vs
B B B
Circuit
RTh
A A
Vs Is
B B B
Method 2:
A
Voc
* Find Voc .
Method 2:
A A
Voc
Isc
* Find Voc . * Find Isc .
Method 2:
A A
Voc
Isc
* Find Voc . * Find Isc . Voc * RTh = . Isc
Method 2:
A A
Voc
Isc
* Find Voc . * Find Isc . Voc * RTh = . Isc * Note: Sources are not deactivated.
Thevenins theorem: example
6 R1 3 9V R2 R3
2
A
RL
B
6 R1 3 9V R2 R3
2
A
RTh
RL
B
VTh
RL
B
6 R1 3 9V R2 R3
2
A
RTh
RL
B
VTh
RL
B
VTh :
2
A
3 9V
Voc
B
6 R1 3 9V R2 R3
2
A
RTh
RL
B
VTh
RL
B
VTh :
2
A
3 9V
Voc
B
Voc = 9 V = 9V
3 6+3 1 = 3V 3
6 R1 3 9V R2 R3
2
A
RTh
RL
B
VTh
RL
B
VTh :
2
A
RTh :
2
A
3 9V
Voc
B
3
B
Voc = 9 V = 9V
3 6+3 1 = 3V 3
6 R1 3 9V R2 R3
2
A
RTh
RL
B
VTh
RL
B
VTh :
2
A
RTh :
2
A
3 9V
Voc
B
3
B
Voc = 9 V
3 6+3
RTh = (R1
R2 ) + R3 = (3
6) + 2
1 = 9V = 3V 3
12 =3 +2 = 4 1+2
6 R1 3 9V R2 R3
2
A
RTh
RL
B
VTh
RL R L
B
3V
RL
VTh :
2
A
RTh :
2
A
3 9V
Voc
B
3
B
Voc = 9 V
3 6+3
RTh = (R1
R2 ) + R3 = (3
6) + 2
1 = 9V = 3V 3
12 =3 +2 = 4 1+2
Maximum power transfer
Circuit
iL RL
Circuit
iL RL
* Power transferred to load is, 2R . PL = iL L
Circuit
iL RL
* Power transferred to load is, 2R . PL = iL L * For a given black box, what is the value of RL for which PL is maximum?
Circuit
iL RL
* Power transferred to load is, 2R . PL = iL L * For a given black box, what is the value of RL for which PL is maximum? * Replace the black box with its Thevenin equivalent.
Circuit
iL RL
RTh
iL VTh RL
B
Circuit
iL RL
RTh
iL VTh RL
* iL =
B
VTh , RTh + RL
2 PL = VTh
RL . (RTh + RL )2
Circuit
iL RL
RTh
iL VTh RL
* iL =
B
VTh , RTh + RL
2 PL = VTh
RL . (RTh + RL )2
* For
dPL = 0 , we need dRL
(RTh + RL )2 RL 2 (RTh + RL ) = 0, (RTh + RL )4 i.e., RTh + RL = 2 RL RL = RTh .
Circuit
iL RL
RTh
iL VTh RL
* iL =
B
VTh , RTh + RL
PL Pmax L
2 PL = VTh
RL . (RTh + RL )2
* For
dPL = 0 , we need dRL
(RTh + RL )2 RL 2 (RTh + RL ) = 0, (RTh + RL )4 i.e., RTh + RL = 2 RL RL = RTh .

RL RL = RTh
Maximum power transfer: example
Find RL for which PL is maximum. 3 2 R1 R3 6 12 V R2 2A
RL
B
Find RL for which PL is maximum. 3 2 R1 R3 6 12 V R2 3 R1 2 2A
RL
B
RTh :
R3 6 R2
B
RL
B
RTh :
R3 6 R2
B
RTh = (R1 =3
R2 ) + R3 = (3 12 +2 = 4 1+2
6) + 2
Voc : R1
2
A
R3 6
RL 12 V
B
R2
2A
B
RTh :
R3 6 R2
B
RTh = (R1 =3
R2 ) + R3 = (3 12 +2 = 4 1+2
6) + 2
Voc : R1
2
A
R3 6
RL 12 V
B
R2
2A
B
RTh :
R3 6 R2
B
Use superposition to nd Voc : 3 2

A
3 R1 R2
B
2
A
R1 12 V R2
R3 6
R3 6 2A
B
RTh = (R1
R2 ) + R3 = (3
6) + 2
12 =3 +2 = 4 1+2
Voc : R1
2
A
R3 6
RL 12 V
B
R2
2A
B
RTh :
R3 6 R2
B

A
3 R1 R2
B
2
A
R1 12 V R2
R3 6
R3 6 2A
B
RTh = (R1
R2 ) + R3 = (3
6) + 2
12 =3 +2 = 4 1+2
6 (1) Voc = 12 = 8 V 9
Voc : R1
2
A
R3 6
RL 12 V
B
R2
2A
B
RTh :
R3 6 R2
B

A
3 R1 R2
B
2
A
R1 12 V R2
R3 6
R3 6 2A
B
RTh = (R1
R2 ) + R3 = (3
6) + 2
12 =3 +2 = 4 1+2
6 (1) Voc = 12 = 8 V 9
(2) Voc = 4 2 A = 8 V
Voc : R1
2
A
R3 6
RL 12 V
B
R2
2A
B
RTh :
R3 6 R2
B

A
3 R1 R2
B
2
A
R1 12 V R2
R3 6
R3 6 2A
B
RTh = (R1
R2 ) + R3 = (3
6) + 2
12 =3 +2 = 4 1+2
6 (1) (2) Voc = 12 = 8 V Voc = 4 2 A = 8 V 9 (1) (2) Voc = Voc + Voc = 8 + 8 = 16 V
Voc : R1
2
A
R3 6
RL 12 V
B
R2
2A
B
RTh :
R3 6 R2
B

A
3 R1 R2
B
2
A
R1 12 V R2
R3 6
R3 6 2A
B
RTh = (R1
R2 ) + R3 = (3
6) + 2
12 =3 +2 = 4 1+2 RTh
A
6 (1) (2) Voc = 12 = 8 V Voc = 4 2 A = 8 V 9 (1) (2) Voc = Voc + Voc = 8 + 8 = 16 V
iL VTh RL
PL is maximum when RL = RTh = 4 iL = VTh /(2 RTh ) = 2 A 2 Pmax L = 2 4 = 16 W .
4 6A 2
4 48 V
12
12
4 6A 2 RTh : 4
4 48 V
12
12
12
12
4 6A 2 RTh : 4
4 48 V
12
12
2
A B
12
12
4
C
4 6A 2 RTh : 4
4 48 V
12
12
2
A B
12
12
4
C
RTh = 7
4 6A 2 RTh : 4
4 48 V
Voc :
4 12
4 48 V 12
Voc
12
12 2 6A
C i
2
A B
12
12
4
C
RTh = 7
4 6A 2 RTh : 4
4 48 V
Voc :
4 12
4 48 V 12
Voc
12
12 2 6A
C i
Note: i = 0 (since there is no return path). VAB = VA VB = (VA VC ) + (VC VB ) = VAC + VCB = 24 V + 36 V = 60 V
2
A B
12
12
4
C
RTh = 7
4 6A 2 RTh : 4
4 48 V
Voc :
4 12
4 48 V 12
Voc
12
12 2 6A
C i
2
A B
12
12
4
C
RTh = 7
VTh = 60 V RTh = 7
4 6A 2 RTh : 4
4 48 V
Voc :
4 12
4 48 V 12
Voc
12
12 2 6A
C i
A B
2
A B
12
12
4
C
RTh = 7
VTh = 60 V RTh = 7
7 60 V
Graphical method for nding VTh and RTh

SEQUEL le: ee101 thevenin 1.sqproj
4 6A 2
4 48 V
12
12

4 6A 2
4 48 V
12
12
Connect a voltage source between A and B. Plot i versus v. 4 6A 2

i v A B
4 48 V 12
12
Voc = intercept on the v-axis. Isc = intercept on the i-axis.

4 6A 2
4 48 V
i (Amp)
10 8 6 4 2
12
12

i v A B
0 0 20 40 v (Volt) 60
4 48 V 12
12

4 6A 2
4 48 V
i (Amp)
10 8 6 4 2
12
12

i v A B
0 0 20 40 v (Volt) 60
4 48 V 12
Voc = 60 V, Isc = 8.5714 A RTh = Vsc /Isc = 7
12

4 6A 2
4 48 V
i (Amp)
10 8 6 4 2
12
12

i v A B
0 0 20 40 v (Volt) 60
4 48 V 12
Voc = 60 V, Isc = 8.5714 A RTh = Vsc /Isc = 7

A B
12
VTh = 60 V RTh = 7
7 60 V
Norton equivalent circuit
RTh
A
VTh
B
RTh
A A
VTh
B
IN
RN
B
RTh
A A
VTh
B
IN
RN
B
* Consider the open circuit case.
RTh
A A
VTh
B
IN
RN
B
* Consider the open circuit case. Thevenin circuit: VAB = VTh .
RTh
A A
VTh
B
IN
RN
B
* Consider the open circuit case. Thevenin circuit: VAB = VTh . Norton circuit: VAB = IN RN .
RTh
A A
VTh
B
IN
RN
B
* Consider the open circuit case. Thevenin circuit: VAB = VTh . Norton circuit: VAB = IN RN . VTh = IN RN .
RTh
A A
RTh
A A
RN VTh
B
IN
RN
B
VTh
Isc IN
B
Isc
B
* Consider the open circuit case. Thevenin circuit: VAB = VTh . Norton circuit: VAB = IN RN . VTh = IN RN . * Consider the short circuit case.
RTh
A A
RTh
A A
RN VTh
B
IN
RN
B
VTh
Isc IN
B
Isc
B
* Consider the open circuit case. Thevenin circuit: VAB = VTh . Norton circuit: VAB = IN RN . VTh = IN RN . * Consider the short circuit case. Thevenin circuit: Isc = VTh /RTh .
RTh
A A
RTh
A A
RN VTh
B
IN
RN
B
VTh
Isc IN
B
Isc
B
* Consider the open circuit case. Thevenin circuit: VAB = VTh . Norton circuit: VAB = IN RN . VTh = IN RN . * Consider the short circuit case. Thevenin circuit: Isc = VTh /RTh . Norton circuit: Isc = IN .
RTh
A A
RTh
A A
RN VTh
B
IN
RN
B
VTh
Isc IN
B
Isc
B
* Consider the open circuit case. Thevenin circuit: VAB = VTh . Norton circuit: VAB = IN RN . VTh = IN RN . * Consider the short circuit case. Thevenin circuit: Isc = VTh /RTh . Norton circuit: Isc = IN . RTh = RN .
Example
5 20 V
1A
10
Example
5 20 V
B
1A
10
Example
5 20 V
B
1A
RN = 5 IN = 20 V = 4A 5
10
Example
5 20 V
B A
1A
RN = 5 IN = 20 V = 4A 5
10
4A 5
B
1A
10
Example
5 20 V
B A
1A
RN = 5 IN = 20 V = 4A 5
3A 5
10
10
4A 5
B
1A
10
Example
5 20 V
B A
1A
RN = 5 IN = 20 V = 4A 5
3A 5
10
10
4A 5
B
1A
i = 3A = 1A
5 5 + 10
10
Example
5 20 V
B A
1A
RN = 5 IN = 20 V = 4A 5
3A 5
10
10
4A 5
B
1A
i = 3A = 1A
5 5 + 10
10
Home work: * Find i by superposition and compare.
Example
5 20 V
B A
1A
RN = 5 IN = 20 V = 4A 5
3A 5
10
10
4A 5
B
1A
i = 3A = 1A
5 5 + 10
10
Home work: * Find i by superposition and compare. * Compute the power absorbed by each element and verify that P Pi = 0 .

Ee101 Basics 1

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Ee101 Basics 1

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EE101: Basics KCL, KVL, power, Thevenins theorem

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* Kirchhos current law (KCL): P ik = 0 at each node.

M. B. Patil, IIT Bombay

* Kirchhos current law (KCL): P ik = 0 at each node. e.g., at node B, i3 + i6 + i4 = 0.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* The subscript c denotes the controlling voltage or current.

Instantaneous power absorbed by an element

M. B. Patil, IIT Bombay

Instantaneous power absorbed by an element

M. B. Patil, IIT Bombay

Instantaneous power absorbed by an element

= V B i B + V C i C V E (i B + i C ) = (VB VE ) iB + (VC VE ) iC = VBE iB + VCE iE

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

v1 = i R1 , v2 = i R2 , v3 = i R3 , v = v1 + v2 + v3 = i (R1 + R2 + R3 ) * The equivalent resistance is Req = R1 + R2 + R3 .

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

i1 = G1 v , i2 = G2 v , i3 = G3 v , where G1 = 1/R1 , etc. i = i1 + i2 + i3 = (G1 + G2 + G3 ) v .

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

* If N = 2, we have R1 R2 R2 R1 Req = , i1 = i , i2 = i . R1 + R2 R1 + R2 R1 + R2 * If Rk = 0, all of the current will go through Rk .

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

1 ( V 1 V 2 ) I0 k ( V 2 V 3 ) = 0 , R1 1 1 1 (V 2 V 1 ) + (V 2 V 3 ) + (V 2 ) = 0 , R1 R3 R2 1 1 k (V 2 V 3 ) + (V 3 V 2 ) + (V 3 ) = 0 . R3 R4 * Solve for the node voltages branch voltages and currents.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay

Linearity and superposition

M. B. Patil, IIT Bombay

Linearity and superposition

M. B. Patil, IIT Bombay

Linearity and superposition

M. B. Patil, IIT Bombay

Linearity and superposition

M. B. Patil, IIT Bombay

Linearity and superposition

M. B. Patil, IIT Bombay

* Superposition refers to superposition of response due to independent sources.

M. B. Patil, IIT Bombay

M. B. Patil, IIT Bombay