INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT595 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state
Product specication Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Jun 04

Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

FEATURES 8-bit serial input 8-bit serial or parallel output Storage register with 3-state outputs Shift register with direct clear 100 MHz (typ) shift out frequency Output capability: parallel outputs; bus driver serial output; standard ICC category: MSI. APPLICATIONS Serial-to-parallel data conversion Remote control holding register. DESCRIPTION

74HC/HCT595

The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks. Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.

QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. TYP. SYMBOL PARAMETER tPHL/tPLH propagation delay SHCP to Q7 STCP to Qn MR to Q7 fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL VCC2 fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC 1.5 V. maximum clock frequency SHCP, STCP input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 16 17 14 100 3.5 115 21 20 19 57 3.5 130 ns ns ns MHz pF pF HCT UNIT

1998 Jun 04

Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

ORDERING INFORMATION PACKAGE TYPE NUMBER NAME 74HC595N 74HC595D 74HC595DB 74HC595PW 74HCT595N 74HCT595D PINNING SYMBOL Q0 to Q7 GND Q7 MR SHCP STCP OE DS VCC PIN 15, 1 to 7 8 9 10 11 12 13 14 16 DIP16 SO16 SSOP16 TSSOP16 DIP16 SO16 DESCRIPTION plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 3.9 mm

74HC/HCT595

VERSION SOT38-1 SOT109-1 SOT338-1 SOT403-1 SOT38-1 SOT109-1

plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 3.9 mm

DESCRIPTION parallel data output ground (0 V) serial data output master reset (active LOW) shift register clock input storage register clock input output enable (active LOW) serial data input positive supply voltage

handbook, halfpage

11

12 9 15 1 2 3 4 5 6 7

handbook, halfpage

Q1 1 Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 GND 8
MLA001

16 VCC 15 Q0 14 DS 13 OE

SHCP STCP Q7' Q0 Q1 Q2 14 DS Q3 Q4 Q5 Q6 Q7 MR 10 OE 13

MLA002

595
12 STCP 11 SHCP 10 MR 9 Q7'

Fig.1 Pin configuration.

Fig.2 Logic symbol.

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

74HC/HCT595

handbook, halfpage 13

OE

EN3 C2 R SRG8 C1/ 1D 2D 3 15 1 2 3 4 5 6 7 9

MSA698

STCP MR SHCP DS

12 10 11 14

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7'

Fig.3 IEC logic symbol.

handbook, full pagewidth

14 11 10

DS SHCP MR Q7 ' 9 8-STAGE SHIFT REGISTER

12 STCP

8-BIT STORAGE REGISTER

Q0 Q1 Q2 Q3 13 OE 3-STATE OUTPUTS Q4 Q5 Q6 Q7

15 1 2 3 4 5 6 7

MLA003

Fig.4 Functional diagram.

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

74HC/HCT595

handbook, full pagewidth

STAGE 0 D FF0 CP R Q D

STAGES 1 TO 6 Q

STAGE 7 D FF7 CP R Q Q7'

DS

SHCP MR

D CP

D CP

LATCH

LATCH

STCP OE

Q0

Q1 Q2 Q3 Q4 Q5 Q6

Q7

MLA010

Fig.5 Logic diagram.

1998 Jun 04

Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

FUNCTION TABLE INPUTS SHCP X X X STCP X X X OE L L H L MR L L L H DS X X X H OUTPUTS

74HC/HCT595

FUNCTON Q7 L L L Q6 QN NC L Z NC a LOW level on MR only affects the shift registers empty shift register loaded into storage register shift register clear. Parallel outputs in high-impedance OFF-state logic high level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6) appears on the serial output (Q7) contents of shift register stages (internal Qn) are transferred to the storage register and parallel output stages contents of shift register shifted through. Previous contents of the shift register is transferred to the storage register and the parallel output stages.

NC

Qn

Q6

Qn

Notes 1. H = HIGH voltage level; L = LOW voltage level = LOW-to-HIGH transition; = HIGH-to-LOW transition Z = high-impedance OFF-state; NC = no change X = dont care.

1998 Jun 04

Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

74HC/HCT595

handbook, full pagewidth SH CP

DS

STCP

MR

OE

Q0 high-impedance OFF-state Q1

Q6

Q7

Q 7'
MLA005 - 1

Fig.6 Timing diagram.

1998 Jun 04

Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DC CHARACTERISTICS FOR 74HC

74HC/HCT595

For the DC characteristics see chapter 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: parallel outputs, bus driver, serial output, standard ICC category: MSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER min tPHL/tPLH propagation delay SHCP to Q7 propagation delay STCP to Qn propagation delay MR to Q7 3-state output enable time OE to Qn 3-state output disable time OE to Qn shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW tPHL/tPLH tPHL tPZH/tPZL 75 15 13 75 15 13 75 15 13 tsu set-up time DS to SHCP set-up time SHCP to STCP 50 10 9.0 tsu 75 15 13 +25 typ 52 19 15 55 20 16 47 17 14 47 17 14 41 15 12 17 6 5 11 4 3 17 6.0 5.0 11 4.0 3.0 22 8 7 max 160 32 27 175 35 30 175 35 30 150 30 26 150 30 26 40 to +85 min 95 19 16 95 19 16 95 19 16 65 13 11 95 19 16 max 200 40 34 220 44 37 220 44 37 190 38 33 190 38 33 40 to +125 min 110 22 19 110 22 19 110 22 19 75 15 13 110 22 19 max 240 48 41 265 53 45 265 53 45 225 45 38 225 45 38 ns ns ns ns ns ns ns ns ns TEST CONDITION UNIT V CC WAVEFORMS (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.8 Fig.9 Fig.10 Fig.8 Fig.7 Fig.11 Fig.11 Fig.10 Fig.8 Fig.7

tPHZ/tPLZ

tW

tW

tW

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

Tamb (C) SYMBOL PARAMETER min th hold time DS to SHCP removal time MR to SHCP maximum clock pulse frequency SHCP or STCP 3 3 3 trem 50 10 9 fmax 9 30 35 +25 typ 6 2 2 19 7 6 30 91 108 max 40 to +85 min 3 3 3 65 13 11 4.8 24 28 max 40 to +125 min 3 3 3 75 15 13 4 20 24 max MHz ns

74HC/HCT595

TEST CONDITION UNIT V CC WAVEFORMS (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Figs 7 and 8 Fig.10 Fig.9

1998 Jun 04

Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

DC CHARACTERISTICS FOR 74HCT

74HC/HCT595

For the DC characteristics see chapter 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI. Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. GND = 0 V; tr = tf = 6 ns; CL = 50 pF. INPUT DS MR SHCP STCP OE UNIT LOAD COEFFICIENT 0.25 1.50 1.50 1.50 1.50

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER min tPHL/ tPLH tPHL/ tPLH tPHL tPZH/ tPZL tPHZ/ tPLZ tW tW tW tsu tsu th trem fmax propagation delay SHCP to Q7 propagation delay STCP to Qn propagation delay MR to Q7 3-state output enable time OE to Qn 3-state output disable time OE to Qn shift clock pulse width HIGH or LOW storage clock pulse width HIGH or LOW master reset pulse width LOW set-up time DS to SHSP set-up time SHCP to STCP hold time DS to SHCP removal time MR to SHCP maximum clock pulse frequency SHCP or STCP 16 16 20 16 16 3 10 30 +25 typ 25 24 23 21 18 6 5 8 5 8 2 7 52 max 42 40 40 35 30 40 to +85 min 20 20 25 20 20 3 13 24 max 53 50 50 44 38

74HC/HCT595

TEST CONDITION 40 to +125 UNIT V CC WAVEFORMS (V) min max 24 24 30 24 24 3 15 20 63 60 60 53 45 ns ns ns ns ns ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.8 Fig.10 Fig.11 Fig.11 Fig.7 Fig.8 Fig.10 Fig.9 Fig.8 Fig.9 Fig.10 Figs 7 and 8

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

AC WAVEFORMS

74HC/HCT595

handbook, full pagewidth

1/fmax

SHCP INPUT

VM(1)

tW tPLH

tPHL 90%

Q7' OUTPUT 10% tTLH

VM(1)

tTHL

MSA699

(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.7

Waveforms showing the clock (SHCP) to output (Q7) propagation delays, the shift clock pulse width and maximum shift clock frequency.

handbook, full pagewidth

SHCP INPUT

VM(1)

tsu VM(1)

1/fmax

STCP INPUT

tW tPLH

tPHL

Qn OUTPUT

VM(1)
MSA700

(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.8

Waveforms showing the storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time.

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

74HC/HCT595

handbook, full pagewidth

SHCP INPUT

VM(1)

tsu th

tsu th

DS INPUT

VM(1)

Q7' OUTPUT

VM(1)
MLB196

(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.9 Waveforms showing the data set-up and hold times for the DS input.

handbook, full pagewidth

MR INPUT

VM(1)

tW

trem

SHCP INPUT

VM(1)

tPHL

Q7' OUTPUT

VM(1)
MLB197

(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7) propagation delay and the master reset to shift clock (SHCP) removal time.

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

74HC/HCT595

handbook, full pagewidth

tr 90% OE INPUT 10% tPLZ Qn OUTPUT LOW-to-OFF OFF-to-LOW tPHZ Qn OUTPUT HIGH-to-OFF OFF-to-HIGH outputs enabled 90% VM(1)

tf

tPZL

VM(1) 10% tPZH

VM(1) outputs enabled

MSA697

outputs disabled

(1) HC: VM = 50%; VI = GND to VCC HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.11 Waveforms showing the 3-state enable and disable times for input OE.

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body

74HC/HCT595

SOT38-1

D seating plane

ME

A2

A1

c Z e b1 b 16 9 MH w M (e 1)

pin 1 index E

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001AE EIAJ EUROPEAN PROJECTION

ISSUE DATE 92-10-02 95-01-19

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

SO16: plastic small outline package; 16 leads; body width 3.9 mm

74HC/HCT595

SOT109-1

A X

c y HE v M A

Z 16 9

Q A2 A1 pin 1 index Lp 1 e bp 8 w M L detail X (A 3) A

2.5 scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3

0.010 0.057 0.069 0.004 0.049

0.019 0.0100 0.39 0.014 0.0075 0.38

0.244 0.050 0.041 0.228

0.028 0.004 0.012

8 0o

Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION

ISSUE DATE 95-01-23 97-05-22

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

74HC/HCT595

SOT338-1

A X

c y HE v M A

Z 16 9

Q A2 pin 1 index Lp L 1 bp 8 w M detail X A1 (A 3) A

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 0o
o

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150AC EIAJ EUROPEAN PROJECTION

ISSUE DATE 94-01-14 95-02-04

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

74HC/HCT595

SOT403-1

c y HE v M A

16

Q A2 pin 1 index A1 Lp L (A 3) A

1
e bp

8
w M detail X

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 0o
o

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO, SSOP and TSSOP REFLOW SOLDERING

74HC/HCT595

Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end.

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Philips Semiconductors

Product specication

8-bit serial-in/serial or parallel-out shift register with output latches; 3-state

Even with these conditions: Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. DEFINITIONS Data sheet status Objective specication Preliminary specication Product specication Limiting values REPAIRING SOLDERED JOINTS

74HC/HCT595

Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.

This data sheet contains target or goal specications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains nal product specications.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specication is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specication. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

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