Synchronous up/down counter(8bit) module up_dn(out,in,pl,ud,clk); input[7:0]in; input pl,ud,clk; output[7:0]out; reg[7:0]out; always@(posedge clk) begin if(pl) out=in;

else if(ud) out=out+1; else out=out-1; end endmodule module stimulus; reg[7:0]in; reg pl,ud,clk; wire[7:0]out; up_dn count(out,in,pl,ud,clk); initial begin pl=1;in=8'd5; #10 pl=0;ud=1; #30pl=0;ud=0; #100$stop; end initial begin $monitor($time,"out=%b,in=%b,pl=%b,ad=%b",out,in,pl,ud); end initial clk=0; always #5clk=~clk; endmodule

Asynchronous up/down counter(8 bit) module up_dn(out,in,pl,ud,clk); input[7:0]in; input pl,ud,clk; output[7:0]out; reg[7:0]out; always@(posedge pl or posedge clk) begin if(pl) begin out=in; end else if(ud) out= out +1 ; else if(ud==0) out=out-1; end endmodule module stimulus; reg[7:0]in; reg pl,ud,clk; wire[7:0]out; up_dn count(out,in,pl,ud,clk); initial begin pl=1;in=8'd7; #10 pl=0;ud=1; #30 pl=0;ud=0; #50 pl=1;ud=1;in=8'd8; #1 pl=0; #400 $stop; end initial begin $monitor($time,"out=%b,in=%b,pl=%b,ud=%b",out,in,pl,ud); end initial clk=0; always #5clk=~clk; endmodule