DATAFLOW MODELING

Task 1: Implement a Dual 4:1 Multiplexer (IC74F153)using data flow modeling

Implement an 8:1 multiplexer using 74F153

Task 2: Implement a single bit Full carry adder using data flow modeling in zero delay Model Add delay of 10 for the sum and 7 for carry bit in the full one bit adder and observe the results Implement a 4-bit full carry adder using the above single bit full carry adder in zero delay model Implement a 4-bit full carry adder using the above single bit full carry adder as per the delays mentioned in the step 2 in task 2 and observe the maximum delay that can occur by applying the worst case inputs. Hint : In these cases, Testbench will help better than forcing one input at a time.

Task 3: Implement 4 Bit adder subtractor using the zero delay 1-bit full adder modules designed in task 2.