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Chapter 5: BSIM3v3 Characterization

The BSIM3 model (BSIM = Berkeley Short channel Insulated gate field effect transistor Model) was published by the University of California at Berkeley in July 1993. BSIM3 is a public model and is intended to simulate analog and digital circuits that consist of deep submicron MOS devices down to channel lengths of 0.15 micron. BSIM3 is a physical model with built-in dependencies of important device dimensions and process parameters like the channel length and width, the gate oxide thickness, substrate doping concentration and LDD structures. Due to its physical nature and its built-in geometry dependence, the prediction of device behavior of advanced devices based on the parameters of the existing process is possible. As a further improvement, one set of model parameters covers the whole range of channel lengths and channel widths of a certain process which can be used in circuit designs. Due to the physical meaning of many model parameters, the BSIM3 model is the ideal basis for the statistical analysis of process fluctuations. BSIM3 can model the following physical effects of modern submicron MOS transistors:
Threshold Voltage
Vertical and lateral non-uniform doping Short channel effects Narrow channel effects
Mobility
Mobility reduction due to vertical fields

Carrier Velocity Saturation Drain Current
Bulk charge effect Subthreshold conduction Source/drain parasitic resistance

Bulk Current
Output Resistance Drain induced barrier lowering (DIBL) Channel length modulation (CLM) Substrate current induced body effect (SCBE)
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Short channel capacitance model Temperature dependence of the device behavior
For a detailed description of these features please refer to the BSIM3 manual of Berkeley University. You can order this manual from Berkeley or you can get it over the Internet. Please see the last chapter of this manual for details. The BSIM3v3 Modeling Package provides the user with a complete extraction strategy for the model parameters of the BSIM3v3.2.2 model. The extraction routines are based on the BSIM3v3.2.2 device equations to ensure that the extracted model parameters represent as good as possible the original physical meaning. Therefore, no or only a minimum of optimization is needed to get a good fit between measured and simulated device behavior. The routines of this release refer to version 3.2 of the BSIM3 model which was released by University of California at Berkeley in June 1998.
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Versions of the BSIM3 Model

University of California at Berkeley released three versions of its BSIM3 model. All three versions have differences in some model parameters, and the model parameter sets are not compatible. The following example of the parameter UC, which is a part of the mobility reduction, demonstrates the problem: In BSIM3v2 the effective mobility eff was calculated according to the following formula: o eff = ------------------------------------------------------------------------------------------------------------------------------------------------------2 1 + U a ( ( V gs + V th ) T ox ) + U b ( ( V gs + V th ) T ox ) + U c V bs In BSIM3v3.2.2, the formula changed to: o eff = ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 1 + ( U a + U c V bseff ) ( ( V gsteff + 2V th ) T ox ) + U b ( ( V gsteff + 2V th ) T ox ) It can easily be recognized, that UC has quite different values in both equations. That means, if BSIM3v2 is implemented in the simulator, and the parameter is extracted for BSIM3v3.2.2, the simulation will give catastrophic results (in the case of UC). Therefore, you must be sure that you use the same version of BSIM3 in both your simulator and your extraction tool.
Versions of the BSIM3 Model
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The Unified I-V Model of BSIM3v3

For a complete summary of all equations of the BSIM3v3.2 model please refer to the original documentation from University of California at Berkeley (see the notes at the end of this document on how to order this paper). The main equations of the BSIM3v3.2 model are shown together with a graphical representation for a better understanding of the model. Please use the model bsim3_tutor_dc.mdl provided with the BSIM3v3 Modeling Package to visualize most of the model parameters. Load the file into IC-CAP and run the different macros to see how certain parameters affect the device behavior of a deep submicron MOS transistor.
Threshold Voltage
The threshold voltage is one of the most important parameters of deep submicron MOS transistors and is affected by many different effects when the devices are scaled down into the region of 0.1 microns. The complete equation of the threshold voltage in BSIM3v3.2 is given below. V th = V Tideal + V th ( 1 ) + V th ( 2 ) V th ( 3 ) V th ( 4 ) + V th ( 5 ) V th ( 6 ) (1)
The Unified I-V Model of BSIM3v3 5-4
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The different parts of this complex equation are expressed by the following sub-equations in more detail: V th = V th0 K 1 s T ox % T ox & +K 1 ------------ s V bseff K 2 # ------------V bseff$ T oxm ! T oxm " T ox Nlx & +K 1 ------------ % % 1 + --------- 1& s " T oxm ! ! L eff" D VT0 e
L eff& % D -------VT1 ! 2l t "
+ 2e
eff& % D L ! VT1 -------lt "
( V bi s )
(2) ( V bi s )
D VT0w e
W eff L eff& % D ------------------! VT1w 2l tw "
+ 2e
W eff L eff& % D ------------------! VT1w l tw "
T ox + ( K 3 + K 3b V bseff ) ------------------------------- s ( W eff + W 0 ) e

eff& % D L ! sub -------2l t0"
+ 2e
eff& % D L ! sub -------l t0 "
( E ta0 + E tab V bseff ) V ds
Ideal Threshold Voltage

The basic equation of the threshold voltage is: V Tideal = V th0 = V FB + s + K 1 s % N ch& s = 2V tm0 ln # --------$ at T = T nom ! n i0 " k B T nom V tm0 = ------------------q (3) (4)
(5)
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where:
Vthideal VFB s ni Eg0 = ideal threshold voltage = flatband voltage = surface potential = 1.45 1010 (Tnom/300.15)1.5 (21.5566 Eg0/2Vtmo) = 1.16 7.02 10-4 Tnom2/(Tnom + 1108)
This equation had been implemented into the first MOS simulation models assuming long and wide channels and uniform substrate doping. The following sections describe the effects which overlay this basic equation.
Non-Uniform Vertical Channel Doping

The substrate doping concentration N is not constant in the vertical direction of the channel, as shown in Figure 5-1.
Figure 5-1. Vertical Doping Profile in the Channel It is usually higher near the silicon to silicon dioxide interface than deeper in the substrate. This higher doping concentration is used to adjust the threshold voltage of the device. The distribution of impurity atoms inside the substrate is approximately a half Gaussian distribution, which can be approximated by a step function with NCH for the peak concentration in the channel near the SiSiO2 interface and Nsub in the deep bulk. XT is the depth where the approximation of the implant profile switches from NCH to NSUB. The non-uniform vertical channel doping affects the threshold voltage when a bulk source voltage is applied to the device and is represented here as the part Vth(1) of the overall threshold voltage.
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T ox T ox V th ( 1 ) = K 1 ------------ s V bseff K 2 ------------V T oxm T oxm bseff K 1 = 2 2K 2 s V bm ( 1 2 ) ( s V bx s ) K 2 = ------------------------------------------------------------------------------2 s ( s V bx s ) + V bx 2q si N ch 1 = -------------------------C ox 2q si N sub 2 = ----------------------------C ox where:
Vbx = substrate bias voltage when the depletion width equals
(6) (7) (8)
(9)
(10)
qN ch X t2 X t = s -------------------2 si
Vbm Toxm Tox = maximum substrate bias voltage = gate oxide thickness at which parameters are extracted = default value of Toxm
Vbseff = V bc + 0,5 V bs V bc 1 +
( V bs V bc 1 ) 4 1 V bc
1
Vbc
= 0.001V
2 % K1 & = 0,9 # s ---------$ # 2$ 4K 2" !
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In BSIM3, either the model parameters K1 and K2 or NCH, NSUB, VBM or XT can be used to model this effect. Figure 5-2 shows the threshold voltage Vth as a function of the applied bulk voltage for a transistor with a large channel length and a wide channel width (LARGE).
Figure 5-2. Threshold Voltage Vth as a Function of Vbs
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Non-Uniform Lateral Channel Doping

The doping concentration Nds near the drain and the source is higher than the concentration Na in the middle of the channel. This is referred to as lateral non-uniform doping concentration and is shown in Figure 5-3.
Figure 5-3. Lateral Doping Profile in the Channel As the channel length becomes shorter, the lateral non-uniform doping will cause the threshold voltage to increase strongly because the average doping concentration in the channel becomes higher. This part of the threshold voltage is modeled with the parameter Nlx and is represented by Vth(2) as a part of the overall threshold voltage. T ox % % Nl x & & V th ( 2 ) = K 1 ------------ # # 1 + ---------$ 1$ s T oxm ! ! L eff" " where: Nlx = 2Lx(Nds Na)/Na (11)
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Figure 5-4 shows the influence of the non-uniform lateral doping on the threshold voltage as a function of gate length.
Figure 5-4. Threshold Voltage as a Function of Gate Length Due to Lateral Non-Uniform Doping You can distinguish between the theoretical trace following equation (11) and the real world ones with the short channel effect described in the next chapter.
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Short Channel Effect

The threshold voltage of a long channel device is independent of the channel length and the drain voltage as it is shown in the equation of the ideal threshold voltage. The decreasing of device dimensions causes the so-called short-channel effects: threshold voltage roll-off and degradation of the subthreshold slope, that in turn increases the off-current level and power dissipation. The threshold voltage then depends on geometrical parameters like the effective channel length and the shape of the source-bulk and drain-bulk junctions. These device dimensions have a strong influence on the surface potential along the channel. A shallow junction with a weak lateral spread is desirable for the control of short-channel effects while the source and drain resistance must be kept as low as possible. However, a trade-off between the search for very shallow junctions and the degradation of the maximum achievable current through the parasitic resistance of low doped drain regions must be found. Those effects can be shown in device simulators, where the drift and diffusion and additionally the hot electron behavior can be simulated. The following equations are responsible for the modeling of the short channel effect part Vth(3) in the BSIM3 model: V th ( 3 ) = D VT0 e
L eff& % D ! VT1 -------2l t "
eff& % D L ! VT1 -------lt "
+ 2e
( V bi s )
(12)
lr =
si T ox X dep ---------------------------- ( 1 + D VT2 V bseff ) sio2 2 si ( s V bseff ) ------------------------------------------qN ch
(13)
X dep = where:
Vbi
(14)
built-in voltage of the PN junction between the source/drain and the substrate
K B T % N ch N d& - ln # ---------------= -----------$ q ! n2 " i

Nd = source/drain doping concentration (or in the LDD regions) if they exist DVT0, are parameters used to make the model fit different technologies DVT1, DVT2
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Figure 5-5. Influence of Short Channel Effects on the Threshold Voltage For short channel lengths together with small channel widths, the following additional expression Vth(4) is needed to formulate the threshold voltage: V th ( 4 ) = D VT0w e where: l tw = si T ox X dep ---------------------------- ( 1 + D VT2W V bseff ) sio2
W eff L eff& % D ! VT1w ------------------2l tw " W eff L eff& % D ! VT1w ------------------l tw "
+ 2e
( V bi s )
(15)
Narrow Channel Effect

All the effects on the threshold voltage are based on the non-uniformity along the channel length. Regarding the channel width, the depletion region is always larger due to the existence of fringing fields at the side of the channel. This effect becomes very substantial as the channel width decreases and the depletion region underneath the fringing field becomes comparable to the depletion layer formed from the vertical field. This additional depletion region results in an increase of the threshold voltage with smaller channel widths which is expressed by Vth(5).
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T ox V th ( 5 ) = ( K 3 + K 3b V bseff ) ------------------------------- s (W + W )
eff 0
(16)
Figure 5-6. Influence of Narrow Channel Effects on the Threshold Voltage
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Threshold Voltage Reduction Through DIBL

The effect of the drain induced barrier lowering (DIBL) will be explained later. BSIM3 uses the following equation to model the DIBL effect in the threshold voltage:
eff& % D L -------! sub 2l t0" eff& % D L -------! sub l t0 "
V th ( 6 ) =
+ 2e
( E ta0 + E tab V bseff ) V ds
(17)
l t0 =
si T ox X dep --------------------------- sio2
(18)
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Carrier Mobility Reduction

BSIM3v3 provides 3 different equations for the modeling of the mobility reduction. They can be selected by the flag MOBMOD. MOBMOD=1:
o eff = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 1 + ( U a + U c V bseff ) ( ( V gsteff + 2V th ) T ox ) + U b ( ( V gsteff + 2V th ) Tox )
(19)
MOBMOD=2:
0 eff = ------------------------------------------------------------------------------------------------------------------------------------2 1 + ( Ua + U c V bseff ) ( V gsteff T ox ) + U b ( V gsteff T ox )
(20)
MOBMOD=3:
0 eff = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 1 + [ U a ( V gsteff + 2V th ) Tox + U b ( ( V gsteff + 2V th ) T ox ) ] ( 1 + U c Vbseff )
(21)
The influence of the mobility reduction parameters is demonstrated in Figure 5-7 where the simulated drain current with and without mobility reduction is shown.
Figure 5-7. Influence of Mobility Reduction
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Figure 5-8 shows the effective mobility as a function of gate voltage and bulk-source voltage.
Figure 5-8. Effective Mobilityeff as a Function of Gate- and Bulk-Source-Voltage
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Effective Channel Length and Width

Effective Channel Length
Figure 5-9. Influence of Channel Length Reduction on the Drain Current The effective channel length is defined in BSIM3 as follows: L eff = L Designed 2dL (22)
The channel length reduction on one side of the channel consists of several empirical terms as shown below: Ll Lw L wl dL = L int + ------------ + --------------- + --------------------------Lln Lwn Lln Lwn L W L W (23)
The use of the model parameters LL, LLN, LWN, LW and LWL is very critical because they are only used for fitting purposes. On the other hand, they may be needed to achieve a good fit over a large area of channel lengths especially for processes with a minimum designed gate length of less
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than 0.25m. Figure 5-9 shows the influence of the geometrical channel length reduction LINT on the drain current of a short channel transistor while Figure 5-10 represents the channel length reduction according to equation (23).
Figure 5-10. Channel Length Reduction dL as a Function of Channel Length L
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Effective Channel Width

The effective channel width is defined in BSIM3 as follows: W eff = W Designed 2dW (24)
The channel width reduction on one side of the channel consists of several empirical terms as shown below: Wl Ww W wl dW = W int + -------------- + ---------------- + -----------------------------Wln Wwn Wln Wwn L W L W (25)
The use of the model parameters WL, WLN, WWN, WW and WWL is very critical because they are only used for fitting purposes. On the other hand, they may be needed to achieve a good fit over a large area of channel widths especially for processes with a minimum designed gate width of less than 0.25m. Figure 5-11 shows the influence of the geometrical channel width reduction WINT on the drain current of a narrow channel transistor while Figure 5-12 represents the channel width reduction according to equation (25).
Figure 5-11. Influence of Channel Width Reduction on the Drain Current
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Figure 5-12. Channel Width Reduction dW as a Function of Channel Width W
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Drain Current
Single Equation for Drain Current
In contrast to former implementations of the BSIM3 model, the drain current is represented through a single equation in all three areas of operation (subthreshold region, linear region and saturation region). Due to this single formula, all first order derivatives of the drain current are continuous, which is an important prerequisite for analog simulations. In the case that no parasitic drain/source resistance is given, the equation for the drain current is given below: V dseff % & V gsteff # 1 A bulk ---------------------------------------------$ V dseff 2 ( V gsteff + 2V tm )" ! W - ------------------------------------------------------------------------------------------------------------I ds0 = eff C ox ---L V dseff 1 + --------------E sat L
(26)
This equation is valid for all three regions of operation of the MOS transistor because the voltages at drain, gate and bulk are replaced by effective drain voltage Vdseff, the effective gate voltage Vgsteff and the effective bulk voltage Vbseff, which are all defined by the continuous equations below: Equation (27) shows the effective (Vgs - Vth) voltage, where the factor n is defined in equation (31). % % V gs V th& & 2n t ln # 1 + exp # -----------------------$ $ ! ! 2n t " " V gsteff = ---------------------------------------------------------------------------------------------------------------------2 s % V gs V th 2V off& 1 + 2nC ox ------------------------ exp # --------------------------------------------$ q ( si N ch ) 2n t ! "
(27)
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Figure 5-13. Effective Voltage Vgs - Vth Figure 5-13 shows Vgsteff in logarithmic scale. Vgsteff fits a linear function for values of Vgs greater than Vth while the subthreshold area is covered by the fit of an exponential function. Through this equation the first derivative is continuous between both operational regions (subthreshold and linear) of the MOS transistor. Equation (28) shows the effective drain source voltage, Vdseff:
2 1% V dseff = V dsat -- V dsat V ds + ( V dsat V ds ) + 4 V dsat& " 2!
(28)
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Figure 5-14 shows Vdseff in both the linear and the saturation region of operation of the MOS transistor. Vdseff models the transition between linear and saturation region without discontinuity in the first derivative of the drain current.
Figure 5-14. Effective Voltage Vdseff
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Drain Saturation Voltage Vdsat

The equation for the drain saturation voltage is divided into two cases, the intrinsic case with Rds = 0 and the extrinsic case with Rds > 0: E sat L eff ( V gsteff + 2V tm ) , -----------------------------------------------------------------------------------, R ds = 0 ) )A ) bulk E sat L eff + ( V gsteff + 2V tm ) ) V dsat = * + ) b b 2 4 ac ) ) ------------------------------) -, R ds 0 2a ' ( where
2 1 & a = A bulk R ds C ox W sat + % -- 1 A ! " bulk
(29)
2 & b = ( V gsteff + 2V tm ) % -- 1" + A bulk E sat L eff + 3A bulk R ds C ox W sat ( V gsteff + 2V tm ) ! c = E sat L eff ( V gsteff + 2V tm ) + 2R ds C ox W sat ( V gsteff + 2V tm )
2
The influence of the maximum carrier velocity VSAT on the drain current Ids and the conductance gds is demonstrated in Figure 5-15.
Figure 5-15. Influence of VSAT on Drain Current Ids and Conductance gds
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Bulk Charge Effect

When the drain voltage is high, combined with a long channel length, the depletion depth of the channel is not uniform along the channel length. This will cause the threshold voltage to vary along the channel length and is called bulk charge effect. Figure 5-16 shows the depletion depth as a function of channel length. For long channels, this effect causes a reduction of the drain current.
Figure 5-16. Depletion Width along the Channel Length The bulk charge effect Abulk is modeled in BSIM3 with the parameters A0, AGS, B0, B1 and KETA as shown in the following equation (30). (30) % , B0 A 0 L eff # T ox ) + ------------------------------------------------------------------# - ) K 1 -----------W eff + B 1 L + 2 X X T oxm ) eff J dep # -* A bulk = # 1 + ----------------------------------L eff 2 s V bseff ) # % &2 -$ # ) 1 AGS V gsteff # -------------------------------------------# ! L eff + 2 X J X dep" ) ! ' -& )$ )$ )$ 1 ----------------------------+$ 1 )$ + K eta V bs )$ )$ ("
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The influence on the drain current is visualized in Figure 5-17.
Figure 5-17. Influence of A0 and KETA on Ids at High Drain Voltages
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Drain Current in the Subthreshold Region

The drain current in the subthreshold region is modeled in BSIM3v3 by the effective voltage Vgsteff. The model parameters VOFF and NFACTOR describe the subthreshold current for a large transistor, while the parameters CDSC, CDSCD and CDSCB are responsible for modeling the subthreshold behavior as a function of channel length. All these parameters contribute to the factor 'n' in the formula for Vgsteff (see equation (27)).
C d ( C dsc + C dscd V ds + C dscb V bseff ) C it n = 1 + Nfactor -------- + ---------------------------------------------------------------------------------- th + -------C ox C ox C ox L eff& % D --------" VT1 ! 2l t
eff& % D L ! VT1 -------lt "
(31)
th = e
+ 2e
(32)
The influence of VOFF and NFACTOR on the drain current in the subthreshold region is shown in Figure 5-18.
Figure 5-18. Influence of VOFF and NFACTOR on Drain Current in the Subthreshold Region
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Parasitic Resistance
As MOS devices are scaled into the deep submicron region, both the conductance gm and the current of the device increase. Therefore the voltage drop across the source and drain series resistance becomes a non-negligible fraction of the applied drain source voltage. The resistance components associated with a MOSFET structure are shown in Figure 5-19. These include the contact resistance (Rcontact) between metallization and source/drain area, the diffusion sheet resistance (Rsheet) of the drain/source area, the spreading resistance (Rspread) which arises from the current spreading from the channel and the accumulation layer resistance (Raccum.).
Figure 5-19. Resistance Components of a MOS Device These components are put together to form the following equation in the BSIM3v3: R dsw [ 1 + P rwg V gsteff + P rwb ( s V bseff s ) ] R ds = -------------------------------------------------------------------------------------------------------------------------------Wr 6 ( 10 W eff ) (33)
The diagram in Figure 5-20 visualizes the equation of Rds. It should be noted that BSIM3 assumes, that the drain resistance is equal to the source resistance. This symmetrical approach may cause difficulties if a device with a nonsymmetrical drain source resistance, e.g. a DMOS power transistor, should be modeled. In this case, a scalable SPICE macro model should add the required behavior to BSIM3.
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Figure 5-20. Drain Source Resistance Rds as a Function of Vg and Vb With this enhancement, equation (26)for the drain current can be rewritten: I ds0 I ds = -----------------------------------------------1 + R ds I ds0 V dseff (34)
The influence of the parasitic resistance on the drain current is demonstrated for a SHORT and a SMALL transistor in Figure 5-21.
Figure 5-21. Influence of Drain Source Resistance on Drain Current

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Output Resistance
a) Early Voltage
The drain current in the saturation region of submicron MOSFETs is influenced by the effects of channel length modulation (CLM), drain induced barrier lowering (DIBL) and substrate current induced body effect (SCBE). These effects can be seen clearly looking at the output resistance Rout of the device, which is defined as: V ds R out = ---------- I ds (35)
In Figure 5-22, the measured drain current and the output resistance of an n-type MOS transistor with a channel length of 0.5 m are shown.
Figure 5-22. Drain Current and Output Resistance in Linear and Saturation Region The leftmost region in Figure 5-22 is the linear region, in which carrier velocity is not saturated. The output resistance is small because the drain current has a strong dependence on the drain voltage. The other three regions belong to the saturation region. The three physical effects CLM, DIBL and SCBE can be seen in the saturation region and are discussed in the following subsections.
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With the output resistance, the equation for the drain current (34) is enhanced by two additional terms and can be rewritten as: V ds V dseff& I ds0 V ds V dseff& % % I ds = ------------------------------------------------ # 1 + ------------------------------$ # 1 + ------------------------------$ VA V 1 + R ds I ds0 V dseff ! "! ASCBE " (36)
The behavior of the output resistance is modeled in BSIM3 in the same way as the Early voltage of a bipolar transistor is modeled in the Gummel-Poon model. The Early voltage is divided in two parts, VA due to DIBL and CLM and VASCBE due to SCBE. VA is given by: P vag V gsteff& 1 % 1 1 V A = V Asat + # 1 + ------------------------------$ % ------------------- + ------------------------& E sat L eff " ! V ACLM V ADIBLC" ! where VAsat is the Early voltage at Vdsat: (38) A bulk V dsat & % -$ E sat L eff + V dsat + 2R ds sat C ox W eff V gsteff # 1 --------------------------------------------2 ( V gsteff + 2V tm )" ! V Asat = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 1 + A bulk R ds sat C ox W eff (37)
b) Channel length modulation (CLM)

When the drain bias approaches the drain saturation voltage, a region of high electric field forms near the drain and the electron velocity in this region saturates. In saturation, the length L of the high-field region increases by an expansion in the direction of the source with increasing drainsource voltage Vds and the MOSFET behaves as if the effective channel length has been reduced by L. This phenomena is termed channel length modulation (CLM). CLM is not a special shortchannel phenomenon, since the effect is present if a MOSFET is short or long. However, its relative importance increases and the effect on the saturated output conductance becomes distinctly more pronounced at shorter gate lengths. The part of the Early voltage due to CLM is given by: A bulk E sat L + V gsteff 1 V ACLM = ---------------- ( V ds V dseff ) - ---------------------------------------------------A bulk E sat l PCLM (39)
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Figure 5-23. Channel Length Modulation (CLM)
c) Drain Induced Barrier Lowering (DIBL)

The depletion charges near source and drain are under the shared control of these contacts and the gate. In a short-channel device, this shared charge will constitute a relatively large fraction of the total gate depletion charge and can be shown to give rise to an increasingly large shift in the threshold voltage Vth with decreasing channel length L. Also, the shared depletion charge near drain expands with increasing drain-source bias, resulting in an additional Vds dependent shift in Vth. This effect is related to a drain voltage induced lowering of the injection barrier between the source and the channel and is termed the drain induced barrier lowering (DIBL). Figure 5-24 shows the band diagram at the semiconductor-insulator interface of an 0.1 m n-channel MOSFET
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simulated by a device simulator. The symmetrical profiles correspond to Vds = 0 and the asymmetrical profiles to Vds > 0. In the figure the simulated potential barrier near the source is observed to decrease with increasing drain bias which indicates the origin of the DIBL effect.
Figure 5-24. Band Diagram at Si-SiO2 Interface of a 0.1 m MOSFET The DIBL effect is modeled in BSIM3v3 with the following equations: ( V gsteff + 2V tm ) A bulk V dsat % & -$ V ADIBLC = ------------------------------------------------------------------ 1 # ----------------------------------------------------------------------- rout ( 1 + P DIBLC V bseff ) ! A bulk V dsat + V gsteff + 2V tm" with % D rout L eff& % D rout L eff& rout ( L ) = P DIBLC1 exp # -------------------------$ + 2 exp # -------------------------$ + P DIBLC2 2l t0 " l t0 ! ! " (41) (40)
Figure 5-25 shows the influence of the DIBL effect on the output resistance of a short channel transistor.
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Figure 5-25. Drain Induced Barrier Lowering (DIBL)
d) Substrate Current Induced Body Effect (SCBE)

Substrate current is induced through hot electrons at high drain voltages, as described in the next section, Substrate Current. It is suggested that the substrate current increases exponentially with the applied drain voltage. The total drain current will change, because it is the sum of the channel current from the source as well as the substrate current. It can be expressed as: I ds = I source + I bulk (42)
The increase of the total drain current through hot electrons will be described by the part VASCBE of the Early voltage which results in a lowering of the output resistance for high drain voltage (Figure 5-26). P SCBE1 l & 1 P SCBE2 % V ASCBE = ------------------- exp # ---------------------------------$ L ! ( V ds V dsat )" (43)
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Figure 5-26.
Substrate Current Body Effect (SCBE)
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Substrate Current
In a n-channel MOSFET, electrons in the channel experience a very large field near the drain. In this high field, some electrons coming from the source will be energetic enough to cause impact ionization, and additional electrons and holes are generated by avalanche multiplication. The high energy electrons are referred as "hot" electrons. The generated electrons are attracted to the drain, adding to the channel current, while holes are collected by the substrate contact, resulting in a substrate current, which is shown in Figure 5-27.
Figure 5-27. Generation of Substrate Current in an n-channel MOSFET
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Figure 5-28. Substrate Current Ibs Paramaterized by Vg The substrate current is described in BSIM3 by the following equation:
0 + 1 L eff 0 V ds V dseff& & I % 1 + --------------------------- ---------------------------I sub = ----------------------------- ( V ds V dseff ) exp % -" ds ! V ds V dseff" ! L eff VA
(44)
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Drain/Bulk and Source/Bulk Diodes

Figure 5-29 shows a pn-junction diode between the bulk and the drain of an n-type MOS Transistor
Figure 5-29. pn-junction diode The drain/bulk and the source/bulk pn-junctions can be used as diodes in CMOS designs. BSIM3v3 offers a simple DC model for the current Ibs or Ibd flowing through these diodes.
V bs & , ------------" % % & ) ! NV tm # ) I sbs e 1$ + G MIN V bs # $ ) ! " I bs = * ) IJTH + I sbs ) IJTH + ---------------------------- ( V bs V jsm ) + G MIN V bs ) NV tm '
(45)
where NJ is the emission coefficient of the source junction and the saturation current Isbs is calculated as: I sbs = A S J S + P S (46)
where JS is the saturation current density of the source/bulk diode, AS is the area of the source junction, JSSW is the sidewall saturation current density of the source/bulk diode and PS is the perimeter of the source junction. JS and JSSW are functions of the temperature and can be described as:
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J S = J S0 e
E g0 Eg T && % ---------- -------- + X TI ln % ---------! T nom" $ # V tm0 V tm # ------------------------------------------------------------------$ NJ # $ ! " E g0 Eg T && % ---------- -------- + X TI ln % ----------" ! Tnom # V tm0 V tm $ # ------------------------------------------------------------------$ NJ # $ ! "
(47)
J SSW = J S0SW e where:
(48)
7,02 10 Tnom E g0 = 1,16 ---------------------------------------------Tnom + 1108 7,02 10 T E g = 1,16 ---------------------------------T + 1108

4 2
JS0 is the saturation current density (default is 10-4 A/m2) JS0SW is the sidewall saturation current density (default is 0) NVtm = NJ (KbT/q) Vjsm = NVtm ln (ijth/Isbs + 1)
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The current Ibs through the diode is shown in the following diagram:
Figure 5-30. Current Ibs Through Diode
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Capacitance Model
Please use the model bsim3_tutor_cv.mdl provided with the BSIM3v3 Modeling Package to visualize the capacitance model parameters. Load the file into IC-CAP and run the different macros to see how certain parameters affect the device behavior of a deep submicron MOS transistor. The capacitance in a MOS transistor can be divided into three different parts: Junction capacitance CJunc between source/drain and the bulk region Capacitance of the extrinsic MOS transistor which consists of: The outer fringing capacitance CF between polysilicon gate and the source/drain The overlap capacitance CGDO between the gate and the heavily doped source/drain regions The overlap capacitance CGDOL between the gate and the lightly doped source/drain regions Capacitance of the intrinsic MOS transistor in the region between the metallurgical source and drain junction when the gate is at flat band voltage. These different parts of the capacitance of a MOS transistors are shown in Figure 5-31 below. The following three subchapters explain each type of capacitance and its implementation in the BSIM3v3 model.
Figure 5-31. Different Parts of the Capacitance of a MOS Transistor
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Junction Capacitance
The source/drain - bulk junction capacitance can be divided into three components as shown in Figure 5-32. The calculation is shown for the drain - bulk junction capacitance. The source - bulk capacitance is calculated in the same way with the same model parameters. The overall junction capacitance Cjdb is given by: , C AREA + C SW + C SWG C jdbs = * ' C AREA + C SW where: CAREA is the bottom area capacitance CSW is the sidewall or peripheral capacitance along the three sides of the junctions field oxide CSWG is the sidewall or peripheral capacitance along the gate oxide side of the junction if PS > Weff + if PS < Weff ( (49)
Figure 5-32. Dimensions of Drain/Source Region and Different Capacitance Parts Bottom area capacitance CAREA
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C AREA = AD C jbd where: AD Cjbd For Vbs < 0: V bs& M j % C jbs = C j # 1 --------$ Pb " ! For Vbs 0: V bs& % C jbs = C j # 1 + M j --------$ Pb " ! area of bottom side of pn junction, given as SPICE model parameter capacitance per unit area of the drain-bulk junction
(50)
Cjbd is calculated according to the following equation and is shown in Figure 5-33. (51)
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Figure 5-33. Bottom Area Capacitance Cjbd as a Function of Vg Peripheral sidewall capacitance CSW along the field oxide C SW = ( PD W eff ) C jbdsw where: PD Weff Cjbdsw total perimeter of pn junction, given as SPICE model parameter effective gate width of transistor, calculated in SPICE capacitance per unit length (52)
Cjbdsw is calculated according to the following equation and is shown in Figure 5-34: For Vbs < 0: V bs & M jsw % C jbdsw = C jsw # 1 -----------$ P bsw" ! (53)
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For Vbs 0: V bs & % -$ C jbdsw = C jsw # 1 + M jsw ----------P bsw" !
Figure 5-34. Sidewall Capacitance Cjbdsw as a Function of Vg Peripheral sidewall capacitance CSWG along the gate oxide C SWG = W eff C jbdswg where: Weff Cjbdswg effective gate width of transistor, calculated in SPICE capacitance per unit length (54)
Cjbdswg is calculated according to the following equation and is shown in Figure 5-35.
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For Vbs < 0: V bs & Mjswg % C jbs = C jswg # 1 --------------$ P bswg" ! For Vbs 0: V bs & % C jbs = C jswg # 1 + M jswg --------------$ P bswg" ! (55)
Figure 5-35. Sidewall Capacitance Cjbdswg Along the Gate Oxide as a Function of Vg
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Extrinsic Capacitance
As mentioned in the introduction to this chapter, the extrinsic capacitance of a MOS transistor consists of the following three components: the outer fringing capacitance CF between polysilicon gate and the source/drain the overlap capacitance CGDO between the gate and the heavily doped source/drain regions the overlap capacitance CGDOL between the gate and the lightly doped source/drain regions The contribution of these different components to the overall extrinsic capacitance is demonstrated in the following diagrams in Figure 5-36 and Figure 5-37.
Figure 5-36. Different Components of the Extrinsic Capacitance
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Figure 5-37. Overlap Capacitance Between Gate and Drain/Source/Bulk
a) Fringing Capacitance
The fringing capacitance of a MOS transistor consists of a bias independent outer fringing capacitance and a bias dependent inner fringing capacitance. In the present release of the BSIM3v3 model, only the bias independent outer fringing capacitance is implemented. Experimentally, it is virtually impossible to separate this capacitance with the overlap capacitance. Nonetheless if the model parameter CF is not given, the outer fringing capacitance can be calculated with the following equation:
7 2 si02 % 4 10 & - ln # 1 + ----------------CF = --------------$ T ox " !
(56)
b) Overlap Capacitance
In BSIM3v3 an accurate model for the overlap capacitance is implemented. In old capacitance models this capacitance is assumed to be bias independent. However, experimental data show that the overlap capacitance changes with gate to source and gate to drain biases. In a single drain structure or the heavily doped S/D to gate overlap region in a LDD structure the bias dependence is the result of depleting the surface of the source and drain regions. Since the modulation is expected to be very small this region can be modeled with a constant capacitance. However in
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LDD MOSFETs a substantial portion of the LDD region can be depleted, both in the vertical and lateral directions. This can lead to a large reduction of overlap capacitance. This LDD region can be in accumulation or depletion. In BSIM3v3, a single equation is implemented for both regions by using such smoothing parameters as Vgsoverlap and Vgdoverlap for the source and drain side, respectively. Unlike the case with the intrinsic capacitance, the overlap capacitances are reciprocal. In other words, Cgsoverlap = Csgoverlap and Cgdoverlap = Cdgoverlap. The model equations for the overlap capacitance are shown for the drain overlap capacitance and are identical for the source overlap capacitance: Overlap charge per gate width:
Q overlap 4V gd, overlap& , CKAPPA % ------------------ = CGDOV gs + CGDL * V gd V gd, overlap ------------------------ 1 + 1 ----------------------------! W eff CKAPPA " + 2 ' (
(57)
where: 2 si qN LDO CKAPPA = ---------------------------2 C ox with the smoothing parameter:

2 1% V gd, overlap = -- ( V gd + 2 ) ( V gd + 2 ) + 4 2& , 2 = 0,02 " 2!
(58)
for the measurement and simulation conditions given in Figure 5-36, this results in the overlap capacitance: Q overlap C gd, overlap = ----------------------- V gs The model parameter CGDO in equation 57 can be calculated by the following equation: CGDO = ( DLC C OX ) CGDL (60) (59)
where DLC represents the channel length reduction in the BSIM3v3 capacitance model. Please see the next sub-chapter for more details about DLC:
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Intrinsic Capacitance
a) Geometry for Capacitance Model
The BSIM3v3 model uses different expressions for the effective channel length Leff and the effective channel width Weff for the I-V and the C-V parts of the model. The geometry dependence for the intrinsic capacitance part is given as the following: WW WWL WL - + ------------------- + ---------------------------------- W = DWC + --------------WLN WWN WWN WLN W L L W LW LWL LL - + ----------------- + ------------------------------- L = DLC + ------------LLN LWN LWN LLN W L W L (61)
(62)
Lactive and Wactive are the effective length and width of the intrinsic device for capacitance calculations. The parameter L is equal to the source/drain to gate overlap length plus the difference between drawn and actual poly gate length due to processing (gate printing, etching and oxidation) on one side. The Lactive parameter extracted from the capacitance method is a close representation of the metallurgical junction length (physical length). W active = W Drawn 2 W L active = L Drawn 2 L (63) (64)
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Figure 5-38. Dimensions of a MOSFET While the authors of the BSIM3v3 model suggest to use a parameter LINT for the I-V model which is different from DLC, other literature sources [3] propose that LINT should have the same value as DLC. This approach is also implemented in the BSIM3v3 Modeling Package to ensure that the extracted values of the channel length reduction are very close to the real device physics. Therefore, the channel length reduction LINT for the I-V model will be set to DLC from the C-V model extracted from capacitance measurements.
b) Intrinsic Capacitance Model

The intrinsic capacitance model that is implemented in the BSIM3 model is based on the principle of conservation of charge. There are a few major considerations in modeling the intrinsic capacitance of a deep submicron MOS transistor: The difficulty in capacitance measurement, especially in the deep submicron regime. At very short channel lengths, the MOSFET intrinsic capacitance is very small while the conductance is large. Charge can only be measured at high impedance nodes (i.e. the gate and substrate nodes), only 8 of the 16 capacitance components in an intrinsic MOSFET can be directly measured. An alternative solution is to use a 2-D device simulator. The access to the internal charges in a simulator. Therefore, this sub-chapter presents no details about the intrinsic charge formulations. Please refer to the BSIM3v3 manual [1] for more information. Only the basic principles are described here.
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To ensure charge conservation, terminal charges instead of the terminal voltages are used as state variables. The terminal charges Qg, Qb, Qs, and Qd are the charges associated with the gate, bulk, source, and drain. The gate charge is comprised of mirror charges from 3 components: The channel minority (inversion) charge (Qinv) The channel majority (accumulation) charge (Qacc) The substrate fixed charge (Qsub) The accumulation charge and the substrate charge are associated with the substrate node while the channel charge comes from the source and drain nodes: Q g = ( Q sub + Q inv + Q acc ) Q b = Q sub + Q acc Q inv = Q s + Q d (65)
The inversion charges are supplied from the source and drain electrodes. The ratio of Qd and Qs is the charge partitioning ratio. Existing charge partitioning schemes are 0/100, 50/50 and 40/60 (given by the model parameter XPART = 0, 0.5 and 1) which are the ratios of Qd to Qs in the saturation region. From these four terminal charges, 9 transcapacitances C(terminal,voltage) are calculated inside the BSIM3 model as partial derivatives with respect to the voltages Vgb, Vdb and Vsb. The abbreviation can be interpreted as: Cggb ..... partial derivative of Qg with respect to Vgb
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Partial derivatives of Qg: Qg C ggb = ----------- V gb Qg C gdb = ----------- V db Qg C gsb = ---------- V sb Partial derivatives of Qd: Qd C dgb = ----------- V gb Qd C ddb = ----------- V db Qd C dsb = ---------- V sb Partial derivatives of Qb: Qb C bgb = ----------- V gb Qb C bdb = ----------- V db Qb C bsb = ---------- V sb (68) (67) (66)
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The 9 transcapacitances introduced above are shown in the following three plots for a simulation setup as shown below:
Figure 5-39. Simulation and Measurement Setup for Overlap Capacitances
Figure 5-40. Terminal charges Qg, Qb and Qd
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Figure 5-41. Partial derivatives of Qg, Qb and Qd with respect to Vdb, Vgb and Vsb
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The Overall Capacitance in BSIM3

In previous subchapters, the three components of the BSIM3 capacitance model has been introduced. Now, when an AC simulation is performed the capacitance, which can be "measured" at the terminals is composed of different parts of junction capacitances, extrinsic capacitances and intrinsic capacitances. The following diagram shows as an example the capacitance components for the overlap capacitance between gate and bulk/source/drain as simulated according to the circuit description below:
Figure 5-42. Simulation and Measurement Setup for Overlap Capacitances
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Figure 5-43. Different Parts of Overlap Capacitance C_Gate_SDB The overlap capacitance C_Gate_SDB consists of: V bs& % C jbs = C j # 1 + M j --------$ Pb " ! where: Cggb Cgd,overlap Cgs,overlap Cgb,overlap intrinsic capacitance overlap capacitance between gate and drain overlap capacitance between gate and source overlap capacitance between gate and bulk (69)
Other capacitances can be calculated in the same way. Please refer to the BSIM3 manual for more details.
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High Frequency Behavior

Macro Model for High Frequency Application
Using the BSIM3v3 model for the simulation of high frequency applications requires a major change in the model structure. A new concept of a SPICE simulation model for deep submicron devices based on the standard BSIM3v3.2 model was found which is able to satisfy a correct DC simulation and the representation of the RF behavior of the MOS devices.
Figure 5-44. Equivalent Circuit for the SPICE Macro Model
High Frequency Behavior 5-58
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The model itself is implemented as macro model as shown in Figure 5-44 and no changes are done in the BSIM3v3.2 model code itself. This is the ultimate pre-condition for its use in a commercial circuit simulator which includes the BSIM3v3.2 model and makes it available to circuit design engineers. The BSIM3v3.2 model already consists of a non-quasi-static model and an accurate capacitance model which makes it the ideal basis for RF simulations. However, the description of the resistance behavior of a transistor is very poor. In the BSIM3v3.2 model itself, no gate resistance is included. Due to the nature of the MOS transistor, such a resistance cannot be seen in the DC operation region. However, looking at the real existing poly silicon gates of modern MOS devices, there is a resistance which cannot be neglected in AC simulations. This resistance Rgate has a major influence on the reflections S11 of an input signal to the MOS transistor as demonstrated in Figure 5-45. It should be noted, that the parameter Rgate in this high frequency model is used to fit the input reflection of the MOS transistor. Therefore it is very likely that Rgate has a different value than the measured sheet resistance of the poly-Si gate during process characterization on PCMs using for instance a van-der-Pauw test structure. The second enhancement in the RF BSIM3v3.2 macro model is a resistance network for the substrate resistance which is described by the three resistors Rbulk1, Rbulk2 and Rbulk3 [7]. The substrate resistance can be seen in the back-reflection S22 at the output of the transistor. Together with the resistance network, the internal drain-bulk junction diode and source-bulk junction diodes of the BSIM3v3.2 model are replaced by the external elements Djdb_area, Djdb_perim, Djsb_area and Djsb_perim. The de-coupling diodes account for the same voltage dependant values of the bottom and the sidewall capacity as the internal junction capacitances. This replacement is the prerequisite for a correct modeling of the substrate resistance.
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With this approach, the model is valid for both the DC and the RF behaviour of the transistor.
Figure 5-45. Influence of gate resistance on input reflection S11 This macro model approach results in a subcircuit for an RF MOS transistor, which is shown in part on the following page.
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* ******************************************************* * Subcircuit of the BSIM3 RF macro model created by the * 'BSIM3v3 Modeling Package' * * The subcircuit contains the ideal MOS transistor modeled with the * UCB BSIM3v3.2 model and additional peripheric elements to enable * high frequency simulations * * Advanced Modeling Solutions, October 1999 * * ******************************************************* .SUBCKT nmos_0p25_tran1_bsim3_hf 1 2 3 * .MODEL bsim_mos_transistor NMOS + LEVEL=8 VERSION=3.2 MOBMOD=1 CAPMOD=3 ... NOIC=-1.4E-12 * .MODEL bsim_diode_area D + CJO=0.0005 VJ=1 M=0.5 IS=9.5E-05 N=1.05 * .MODEL bsim_diode_perim D + CJO=5E-10 VJ=1 M=0.33 IS=8.7E-11 N=1.05 * ******************************************************* * Subcircuit of the BSIM3 RF macro model for n-type MOS transistors * ******************************************************* *.SUBCKT bsim_ac_pel 1 2 3 4 * * --------- Gate network -----------------------------Lgate 2 20 4.534E-11 Cgd_ext 20 11 1.648E-14 Cgs_ext 20 31 0 Rgate 20 21 13.97 * --------- Drain network ----------------------------Ldrain 1 11 4.299E-11 * --------- Source network ----------------------------Lsource 3 31 4.299E-11 * --------- Substrate network ------------------------* Diodes are for n-type MOS transistors * Djdb_area 12 11 bsim_diode_area AREA=3E-11 Djdb_perim 12 11 bsim_diode_perim AREA=6.6E-05 * Djsb_area 32 31 bsim_diode_area AREA=4E-11
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Djsb_perim 32 31 bsim_diode_perim AREA=8.8E-05 * Rsub1 40 4 937.6 Rsub2 12 40 100 Rsub3 32 40 100 * --------- Ideal mos transistor ---------------------MAIN 11 21 31 40 + bsim_mos_transistor L=3.5E-07 W=6E-05 AD=0 AS=0 PD=0 PS=0 * .ENDS
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Modeling Strategy
Modeling the AC behaviour of a MOS device with the BSIM3v3 model heavily depends on the accurate modeling of the DC curves and the capacitances at low frequencies, e.g. 10kHz to 1MHz. However, more and more applications, especially in the telecommunication industry, require the modeling of MOS transistors for the use in a frequency range of 1 to 10GHz. Therefore, S-parameter measurements have to be done (see also the chapter about test structures for Sparameters) to cover this frequency range by a proper device model. As is pointed out, using the BSIM3v3 model for high frequency applications requires some special attention in the model strategy. We found, that the following procedure gives the most accurate results: Measurement of DC and CV curves Extraction of the BSIM3v3 model parameters from DC and CV measurements with a special emphasis on a physically based extraction strategy. Here, model parameters should not be used for fitting purposes, they should have a correct physical meaning The modeling of the output characteristic Id=f(Vds) and the output resistance Rout=f(Vds) is very important for further S-parameter measurements (see Figure 5-48 and Figure 5-47) Performing S-parameter measurements and proper de-embedding of parasitics The starting points of the S-parameter curves at the lowest frequency can be modeled by fitting the curves with DC and capacitance parameters. The following diagrams describe this influence on the high frequency behavior
Figure 5-46. Incorrectly Modeled Output Characteristic
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Figure 5-47. Influence of Incorrectly Modeled Output Characteristic on S21 Extraction of the gate resistance from the input reflection S11 (see Figure 5-48) Verification of the gate - drain overlap capacitance for higher frequencies Extraction of the substrate resistance network parameters from S22 (see Figure 5-48) If a good fitting could not be found, additional peripheral elements like inductances at drain, gate or source should be added in a further sub-circuit
Figure 5-48. Input and Output Reflection S11 and S22
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Figure 5-49. Forward and Reverse Transmission S21 and S12
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Temperature Dependence
Please use the model 'bsim3_tutor_temp.mdl' provided with the BSIM3v3 Modeling Package to visualize the temperature model parameters. Load the file into IC-CAP and run the different macros to see how certain parameters affect the device behavior of a deep submicron MOS transistor.
Built-in Temperature Dependencies

The BSIM3v3 model uses some physically based built-in temperature dependencies as listed below: Temperature voltage: kBT V tm = ---------q Intrinsic carrier concentration:
16 1,5 % 6885 -----------& ! T "
(70)
N i = 2,6310 T
(71)
Unfortunately, the surface potential S, which is a very important model parameter from a physical point of view is not temperature dependent in BSIM3. % N ch & s = 2V tm ( T nom ) ln # ------------------------$ ! N i ( T nom )" (72)
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Temperature Effects
In addition to the built-in temperature dependencies, the following temperature related effects are modeled in BSIM3. They are related to threshold voltage, mobility, saturation of carrier velocity, drain-source resistance, and the saturation current of the drain/source bulk diodes. a) Threshold Voltage KT 1 L % & T - + KT 2 V bseff$ % ------------ 1& V th ( T ) = V th ( T nom ) + # KT 1 + -------------! " L eff ! " T nom The behavior of the threshold voltage for a large and a short device is shown in Figure 5-50. (73)
Figure 5-50. Threshold Voltage Vth=f(T) of a Large (Left) and a Short (Right) Device
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b) Carrier Mobility
All four model parameters of the carrier mobility are implemented in BSIM3 with a temperature dependence: T & UTE 0 ( T ) = U0 % -----------!T " nom T U A ( T ) = UA + UA1 % ------------ 1& !T "
nom
(74) (75) (76) (77)
T & U B ( T ) = UB + UB1 % -----------! T - 1" nom T & U C ( T ) = UC + UC1 % -----------! T - 1" nom The following two diagrams show the effect of a temperature dependent mobility on the transconductance of a large transistor.
Figure 5-51. Temperature Dependence of Carrier Mobility U0
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c) Saturation of Carrier Velocity

The carrier velocity VSAT is reduced with increasing temperature as shown in the following equation, Figure 5-52: T - 1& V SAT ( T ) = VSAT AT % -----------!T "
nom
(78)
Figure 5-52. Output Characteristic Id=f(Vd,T) and VSAT = f(T)
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d) Drain source resistance

The temperature dependence of the drain source resistance is given by the following equation (see Figure 5-53): T - 1& R DSW ( T ) = RDSW PRT % -----------!T "
nom
(79)
Figure 5-53. Drain source resistance RDSW = f(T)
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e) Saturation Current of Drain/Source Bulk Diodes

The temperature dependence of the drain/source bulk diodes is given by the following equation for the saturation current density JS:
E g0 Eg T && % ---------- -------- + XT ln % ----------" ! T nom # V tm0 V tm $ -$ # ----------------------------------------------------------------NJ # $ ! "
J S ( T ) = JS e
(80)
The influence of XTI on diode current and saturation current density JS is shown below.
Figure 5-54. Saturation Current as a Function of Temperature
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Noise Model
There are two noise models implemented in BSIM3 - a conventional noise model which is named Spice2 model and a new formulated noise model, which is referred to as BSIM3v3 noise model. The following equations and diagrams should give insight into these two noise formulations. Please use the model 'bsim3_tutor_ac_noise.mdl' provided with the BSIM3v3 Modeling Package to visualize the model parameters. Load the file into IC-CAP and run the different macros to see how certain parameters affect the device behavior of a deep submicron MOS transistor.
Conventional Noise Model for MOS Devices

Flicker noise: KF1 ds V noise, eff = ------------------------------------2 EF C ox L eff f Channel thermal noise: 8kT V noise, eff = --------- ( g m + g ds + g mb ) 3 (82)
AF
(81)
Figure 5-55. Influence of AF (left) and EF (right) on Effective Noise Voltage
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BSIM3v3 Noise Model

The BSIM3v3 noise model uses the following equation to describe the flicker noise:
V noise, eff V tm q l ds eff % No + 2 10 14 & NOIA = ------------------------------------log --------------------------------+ NOIB ( No Nl ) # $ + 2 EF 8 ! Nl + 2 10 14 " 10 C ox L eff f
2
(83)
where: No is the charge density at the source given by: C ox ( V gs V th ) No = -------------------------------------q and Nl is the charge density at the drain given by: C ox ( V gs V th V ds ) Nl = ------------------------------------------------------q The channel thermal noise is given by: 4kT eff - Q inv V noise, eff = ------------------2 L eff with: A bulk % & - V dseff$ Q inv = W eff L eff C ox V gsteff # 1 --------------------------------------------2 ( V gsteff + 2V tm ) ! " (87) (86) (85) (84)
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SPICE Model Parameters

The model parameters of the BSIM3v3 model can be divided into several groups. The main model parameters are used to model the key physical effects in the DC and CV behavior of submicron MOS devices at room temperature. Here they are grouped into subsections related to the physical effects of the MOS transistor. The second group are the process related parameters. They should only be changed if a detailed knowledge of a certain MOS production process is given. The third group of parameters are the temperature modeling parameters. The following two groups are used to model the AC and noise behavior of the MOS transistor. Finally the last group contains flags to select certain modes of operations and user definable model parameters. For more details about these operation modes refer to the BSIM3v3 manual [1].
Main Model Parameters

Table 5-88. Main Model Parameters
Parameter Description Default Value (NMOS/PMOS) Threshold Voltage VFB VTHO K1 K2 K3 K3B W0 NLX VBM DVT0 Flatbandvoltage Ideal threshold voltage Second-order body effect coefficient Narrow width coefficient Body effect coefficient of K3 Narrow width parameter Lateral non-uniform doping coefficient Maximum applied body bias in VTH calculation. First coefficient of short-channel effect on VTH 0.7/-0.7 0.5 80.0 0.0 2.5E-6 1.74E-7 -5.0 2.2 V V V0.5 1/V m m V C Y Y Y Y Y Y Y C Y Unit Extraction (see notes)
First-order body effect coefficient 0.5
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Table 5-88. Main Model Parameters (continued)

Parameter Description Default Value (NMOS/PMOS) DVT1 DVT2 DVT0W DVT1W DVT2W ETA0 ETAB DSUB Second coefficient of shortchannel effect on VTH Body-bias coefficient of shortchannel effect on VTH 0.53 -0.032 1/V 1/V 1/V Y Y Y Y Y Y Y Y Unit Extraction (see notes)
First coefficient of narrow-channel 2.2 effect on VTH Second coefficient of narrowchannel effect on VTH Body-bias coefficient of narrowchannel effect on VTH DIBL coefficient in the subthreshold region Body-bias for the subthreshold DIBL effect DIBL coefficient in subthreshold region 5.3E6 -0.032 0.08 -0.07 DROUT
Mobility U0 UA UB UC Mobility First-order mobility degradation coefficient Second-order mobility degradation coefficient Body-effect of mobility degradation 670 / 250 2.25E-9 5.87E-19 -4.65E-11 cm2/ (Vs) m/V Y Y1)
(m/V)2 Y1) (m/V)2 Y1)
Drain current VSAT Saturation velocity 8.0E6 cm/s Y
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Parameter Description Default Value (NMOS/PMOS) A0 A1 A2 AGS B0 B1 KETA Bulk charge effect coefficient First non saturation factor Second non saturation factor Gate-bias coefficient of Abulk Bulk charge effect coeff. for channel width Bulk charge effect width offset Body-bias coefficient of the bulk charge effect. 1.0 0/0.23 1.0/0.08 0.0 0.0 0.0 -0.047 1/V 1/V m m 1/V Y Y 2) Y 2) Y Y Y Y Unit Extraction (see notes)
Subthreshold region VOFF NFACTOR CIT CDSC CDSCB CDSCD Offset voltage in the subthreshold -0.11 region Subthreshold swing factor Interface trap density 1.0 0 V F/m2 F/m2 Y Y N Y
Drain-Source to channel coupling 2.4E-4 capacitance Body-bias coefficient of CDSC Drain-bias coefficient of CDSC 0 0
F/Vm2 Y F/Vm2 Y
Drain-source resistance RDSW WR PRWB PRWG Parasitic resistance per unit width 0 Width offset from Weff for RDS calculation Body effect coefficient of RDSW Gate bias effect coefficient of RDSW 1.0 0 0 m V-0.5 1/V Y Y Y Y
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Parameter Description Default Value (NMOS/PMOS) Unit Extraction (see notes)
Channel geometry WINT WL WLN WW WWN WWL LINT LL LLN LW LWN LWL DWG DWB Channel width reduction on one side Coeff. of length dependence for width offset Power of length dependence for width offset Coeff. of width dependence for width offset Power of width dependence for width offset Coeff. of length and width cross term for width offset Channel length reduction on one side Coeff. of length dependence for length offset Power of length dependence for length offset Coeff. of width dependence for length offset Power of width dependence for length offset Coeff. of length and width cross term for length offset Coefficient of Weff's gate dependence Coefficient of Weff's substrate dependence 0 0 1 0 1 0 0 0 1 0 1 0 0 0 m m m m m m m m m/V Y Y Y Y Y Y Y Y Y Y Y Y N
m/V0.5 N
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Parameter Description Default Value (NMOS/PMOS) Unit Extraction (see notes)
Output resistance PCLM PDIBLC1 PDIBLC2 PDIBLCB DROUT PSCBE1 PSCBE2 PVAG ALPHA0 ALPHA1 BETA0 Channel length modulation coefficient Second output resistance DIBL effect Body effect coefficient of output resistance DIBL effect L dependent coefficient of the DIBL effect in output resistance 1.3 1/V Y Y Y Y Y V/m m/V m/V 1/V Y Y Y Y Y Y
First output resistance DIBL effect 0.39 8.6m 0 0.56
First substrate current body-effect 4.24E8 coefficient Second substrate current bodyeffect coefficient The first parameter of impact ionization Length dependent substrate current parameter The second parameter of impact ionization 1.0E-5
Gate dependence of Early voltage 0 0 0 30
Diode characteristic JS JSSW NJ Source drain junction saturation density Side wall saturation current density Emission coefficient of junction 1E-4 0 1 A/m2 A/m Y Y Y
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Parameter Description Default Value (NMOS/PMOS) IJTH Diode limiting current 0.1 A Y Unit Extraction (see notes)
Capacitance CJ CJSW CJSWG MJ MJSW MJSWG PB PBSW PBSWG CGSO CGDO GGBO CGSL CGDL Source/drain bottom junction capacitance per unit area Source/drain side junction capacitance per unit length Source/drain gate side junction capacitance per unit length Bottom junction capacitance grading coefficient Source/drain side junction capacitance grading coefficient Source/drain gate side junction cap. grading coefficient 5.0E-4 5.0E-10 CJSW 0.5 0.33 MJSW F/m2 F/m F/m V V V F/m F/m F/m F/m F/m Y Y Y Y Y Y Y Y Y Y Y N Y Y
Bottom junction built-in potential 1.0 Source/drain side junction built-in 1.0 potential Source/drain gate side junction built-in potential Gate-source overlap capacitance per unit W PBSW XJ*COX/2
Gate-drain overlap capacitance per XJ*COX/2 unit W Gate-bulk overlap capacitance per 0 unit W Light doped source-gate region overlap capacitance Light doped drain-gate region overlap capacitance 0.0 0.0
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Parameter Description Default Value (NMOS/PMOS) CKAPPA CF CLC CLE DLC DWC NOFF VOFFCV Coefficient for lightly doped region overlap Fringing field capacitance Constant term for the short channel model Exponential term for the short channel model Length offset fitting parameter from C-V Width offset fitting parameter from C-V 0.6 0.1E-6 0.6 LINT WINT m m V F/m F/m m N Y Y Y C C N N Unit Extraction (see notes)
Subthreshold swing factor for CV 1 model Offset voltage for CV model 0
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Process Related Parameters

Table 5-89. Process Related Parameters
Parameter TOXM TOX XJ NCH NSUB NGATE VFB PHI gamma1 gamma2 XT RSH Description Gate oxide thickness at which parameters are extracted Gate oxide thickness Junction depth Doping concentration near interface Doping concentration away from interface Poly gate doping concentration Flat-band voltage Surface potential Body-effect near interface Body-effect far from interface Doping depth Sheet resistance 1.55E-7 0 Default Value 15e-9 15E-9 150E-9 1.7E17 2.1E16 0 -1.0 Unit m m m Extraction C Y N
1/cm C3) 1/cm C3) cm3 V C C3) C3) V N N N N
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Temperature Modeling Parameters

Table 5-90. Temperature Modeling Parameters
Parameter UTE KT1 KT1L KT2 UA1 UB1 UC1 PRT AT XTI TPB TPBSW TPBSWG TCJ TCJSW TCJSWG Description Mobility temperature coefficient Threshold voltage temperature coefficient Channel length dependence of KT1 Threshold voltage temperature coefficient Temperature coefficient for UA Temperature coefficient for UB Temperature coefficient for UC Temperature coefficient for RDSW Saturation velocity temperature coefficient Junction current temperature exponent coefficient Temperature coefficient for PB Temperature coefficient for PBSW Temperature coefficient for PBSWG Temperature coefficient for CJ Temperature coefficient for CJSW Temperature coefficient for CJSWG Default Value -1.5 -0.11 0.0 0.022 4.31E-19 -7.61E-18 -0.056 0.0 3.3E4 3.0 0 0 0 0 0 0 Unit V Vm m/V m/V2 m m/s V/K V/K V/K 1/K 1/K 1/K Extraction Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
(m/V)2 Y
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Flicker Noise Model Parameters

Table 5-91. Flicker Noise Model Parameters
Parameter Description Default Value (NMOS/PMOS) NOIA NOIB NOIC EM AF EF KF Noise parameter A Noise parameter B Noise parameter C Saturation field Frequency exponent Flicker exponent Flicker noise parameter 1E20/9.9E18 5E4/2.4E3 -1.4E-12/1.4E12 4.1E7 1 1 0 V/m N N N Y4) Y4) Y4) Y4) Unit Extraction
Non-Quasi-Static Model Parameters

Table 5-92. Non-Quasi-Static Model Parameter
Parameter ELM Description Elmore constant of the channel Default Value 5 Unit Extraction Y
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Model Selection Flags

Table 5-93. Model Selection Flags
Parameter LEVEL MOBMOD Value 8 1 2 3 CAPMOD 0 1 2 3 NQSMOD NOIMOD 0 1 1 2 3 4 Noise model 4) Non quasi static model Capacitance model Type of Model BSIM3v3 model selector (in UCB SPICE) Mobility model Extraction for Model Available Y N N Y Y Y Y
User Definable Parameters

Table 5-94. User Definable Parameters
Parameter XPART DELTA Description Charge partitioning coefficient Parameter for smoothness of effective Vds calculation Default Value 0 0.01 Unit Extraction N N
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Notes on Extractions
N ....Parameter extraction will be implemented in a future release Y ....Extraction for this model parameter is implemented in the BSIM3v3 Modeling Package C ....The model parameter is calculated in the BSIM3v3 Modeling Package from other parameters
Notes on Model Parameters

1) Parameter extraction for mobility model MOBMOD = 1 2) Only for PMOS devices 3) Gamma1, gamma2, NCH and NSUB are calculated from K1 and K2 and are not included in the model parameter set. 4) Parameter extraction for these parameters will be included in future updates
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Test structures for Deep Submicron CMOS Processes

A very important prerequisite for a proper model parameter extraction is the selection of appropriate test structures. The following subsections describe the necessary test structures for the determination of CV and DC model parameters. A very detailed description of ideal test structures can be found in the JESSI AC-41 reports [2].
Transistors for DC measurements

The minimum set of devices for a proper extraction of DC model parameters is marked in with 'o'. This means one transistor with large and wide channel (and therefore showing no short/narrow effects), one transistor with a narrow channel, one transistor with a short channel and one device with both, short and narrow channel. Please note that with this minimum set of devices some parameters cannot be determined correctly (see chapter 3) and they are set to default values during the extraction. For an extraction of all model parameters and a better fit of the simulated devices over the whole range of designed gate length and gate width it is recommended to use more devices with different gate lengths and gate widths as shown in Figure 5-56 with 'o' signs.
Figure 5-56. Required Test Transistors for Parameter Extraction
a) Requirements for Devices

Large
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For a proper extraction of the basic model parameters, the short and narrow channel effects should not affect the large device extraction. Also the drain-source-resistance parameters should not have an influence on the simulated behavior of the large device. For a typical 0.5 micron CMOS process with a gate oxide thickness of 11 nm a large device with channel length of 10 microns and channel width of 10 microns was found to meet these requirements. You can check this prerequisite if you only extract the parameters in the idvg/Large setup and then perform a simulation of the setup idvg/Large_m. After that simulation, perform the other geometry extractions and re-simulate the idvg/Large setup again. Now, the curve ID = f(Vgs) should not change more than roughly 5% compared to the first simulation. If the difference is bigger, a larger device should be taken to enable a good extraction of the basic model parameters. Narrow For the DUT 'Narrow_m' you should use a device with the smallest designed gate width of your process. Using more narrow devices will increase the number of parameters which can be extracted and will lead to a better fit of the curves over the range of different channel widths. Short For the DUT 'Short_m' you should use a device with the shortest designed gate length of your process. Using more short devices will increase the number of parameters which can be extracted and will lead to a better fit of the curves over the range of different channel lengths. Small For the DUT 'Small_m' you should use a device with the shortest designed gate length and the smallest designed gate width of your process. This small device will incorporate all short and narrow channel effects and will be an indicator how good your parameter extractions are. In general It is recommended to use the designed gate lengths and widths. Effects due to under diffusion or decrease of poly-Si gate length are sufficiently covered by the extraction routines and the model itself.
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Drain/Source Bulk Diodes for DC Measurements

Table 5-95. Test Structures for Drain/Source - Bulk Diodes
DUT Diode_Perim_m Shape Comment Finger diode with a large perimeter and a small area (shown here for an n-type device) Area diode with a large area and a small perimeter (shown here for an n-type device)
Diode_Area_m
Test Structures for CV Measurements

Table 5-96. Test Structures for CV Measurements
DUT C_Area_m (pn-junction) Shape Applied bias (n-type) Comment Area diode with a large area, a small perimeter and the doping concentration n+ of the drain/source region (shown here for an n-type device). Finger diode with a large perimeter, a small area and the doping concentration n+ of the drain/source region (shown here for an n-type device).
C_Perim_m (pn-junction)
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Table 5-96. Test Structures for CV Measurements

C_Perim_Gate_m (pn-junction) Finger diode with a large perimeter and a small area and the doping concentration n- of the LDD region (shown here for an n-type device). Large area MOS capacitor
C_Oxide_m (Gate oxide)
C_Gate_SD_m (Overlap gate drain/source)
A large number of parallel switched LDD MOS transistors (e.g. 200 transistors with L=0.25m, W=10.0m) or multi-finger transistors (see shape)
C_Gate_SDB_m (Overlap gate - bulk/ drain/ source)
A large number of parallel switched LDD MOS transistors (e.g. 200 transistors with L=0.25m, W=10.0m) or multi-finger transistors (see shape)
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Table 5-97. Test Structures for Intrinsic Capacitance Measurements

DUT C_Gate_D_m (Overlap gate drain with applied DC bias) Shape Applied bias (n-type) Comment A short channel transistor, with such a channel width or different fingers that the measurement instrument (CV-meter or Network Analyzer) is not overloaded by DC currents and a reasonable capacitance value can be measured. For very small capacitance values, an additional OPEN calibration structure on the chip is necessary to compensate the capacitance of the pads and the lines to the transistor.
______
Testchips
You will find an example for a test chip design, which meets most of the requirements of the extraction of BSIM3v3 model parameter, in the JESSI Report AC 41 94-3 "Description of parametrized European Mini Test Chip." Please check also the test chip design of the Fabless Semiconductor Association in the U.S. (http://www.fsa.org).
Test Structures for S-parameter Measurements

a) Test Structures
Performing S-parameter measurements with MOS devices on a wafer requires properly designed test structures which meet certain requirements:
Test structures for Deep Submicron CMOS Processes 5-90
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The test devices must drive enough current for correct measurement results They should fulfill the specifications of the high frequency probes Additional structures should be available for the measurement of parasitic elements to deembed them from the measurements on the test device A principle layout of such a test structure is shown in Figure 5-57 below [4].
Figure 5-57. Layout of a Test Structure for a MOS Transistor The MOS transistor is designed as a finger structure with four common gates, three source areas and two drain areas. In summary, this compact layout results in a very wide gate width, which can drive a high current Ids. BSIM3v3 can handle a wide range of different test structures for S-parameter measurements of MOS transistors. The commonly used devices are explained below and a short description is given how to use them in the '__Define_DUTs' macro. The setup routine automatically calculates the overall gate width, drain and source area and the drain and source perimeter for SPICE simulations from the input in the '__Define_DUTs' macro. The probes are connected in a Ground-Signal-Ground scheme according to the recommendations in [4]. As it is shown above, the calibration plane of the network analyzer is at the end of the probe head. That means, the transmission lines which connect the DUT with the probe head must be
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modeled and their effect must be de-embedded from the measured data of the DUT.This can be done by measuring an OPEN and a SHORT test device without a DUT and using these measurements to de-embed the parasitic influence of the pads. The following two figures show the design of these OPEN and SHORT test structures. Both of these test structures will be used for a simple and effective de-embedding procedure (OPEN_SHORT) as will be shown later. Additional test devices, like a THROUGH device can be used to verify the de-embedding strategy. In general, the complexity of the de-embedding procedure depends on the frequency range of the measurements and the design of the test structures. However, a proper de-embedding is the absolute pre-requisite for an accurate AC modeling of the MOS transistor.
Figure 5-58. OPEN, SHORT and THROUGH structure without MOS transistor
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Table 5-98. Test Structures for S-parameter Measurements

Test Structure Top View One single transistor Input in ___Define DUT No gate: No drain: No source: L: W: Area drain: Area source: Per. drain: Per. source: No gate: No drain: No source: L: W: Area drain: Area source: Per. drain: Per. source: 1 1 1 L W AD AS PD PS 3 3 3 L W 1) AD 1) AS1) PD1) PS1)
n parallel transistors
multi finger transistors
No gate: No drain: No source: L: W: Area drain: Area source: Per. drain: Per. source:
6 4 3 L W1) AD 1) AS1) PD1) PS1)
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b) De-embedding procedures
The DUT 'Deembedding' contains three different setups with different de-embedding methods: OPEN OPEN_SHORT USER_DEFINED They can be selected depending on the availability of test structures and the frequency range of measurements:
1.OPEN:
This the simpliest way of de-embedding and is often used for freqency ranges up to 10GHz. It is assumed, that the parasitics can be modeled using the following equivalent circuit:
Figure 5-59. Equivalent circuit for the parasitic elements (including MOS-Transistor) The OPEN device is measured and the S-parameters of the DUT are calculated as shown next:
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Stotal -> Ytotal, Sopen -> Yopen
Ydut -> Sdut where: Stotal -> measured S-parameters of the DUT including parasitics Sopen -> measured S-parameters of the OPEN test structure Sdut -> S-parameters of the DUT without influence of the parasitics Yxxx -> transformed Y-parameters with 'Ytotal = TwoPort(Stotal,"S","Y")' The typical behaviour of this test structure is shown in Figure 5-60.
Figure 5-60. S11,22 and S12,21 of the OPEN structure
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2.OPEN_SHORT:
This is a very fast and effective way of de-embedding from measurements of an OPEN and a SHORT device. It is useful for frequencies above roughly 10GHz if the accuracy of the OPEN method is not satisfying. This method is described in detail in the IC-CAP demo_features. (See the file: $ICCAP_ROOT/ examples/demo_features/4extraction/deemb_short_open.mdl) It is assumed, that the parasitics can be modeled using the following equivalent circuit:
Figure 5-61. Detailed equivalent circuit of MOS-Transistor The transistor is located between nodes: Gate = 222, Drain = 111, Source,Bulk = 333 Regarding the two test structures OPEN and SHORT and their equivalent circuits, it is assumed that there are ONLY parallel parasitics followed by serial parasitics. If this pre-requisite is valid, the measured data of the SHORT device and the measured data from the DUT have to be deembedded from the outer parallel parasitic elements first (after a conversion of S to Y parameters): Zdut_without_open = Z(Ytotal - Yopen) Zshort_without_open = Z(Yshort - Yopen)
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The subsequent step is to de-embed the measured data of the DUT from the serial parasitic elements and convert them back to S-parameters: Sdut = S(Zdut_without_open - Zshort_without_open) The typical behaviour of the OPEN_SHORT structure is shown below:
Figure 5-62. S11,22 and S12,21 of the OPEN_SHORT structure
3.USER_DEFINED:
This setup can be used to implement user-specific de-embedding procedures with other test structures than OPEN and SHORT or to achieve a higher quality in de-embedding. Please have a look at the transform 'deembed_all' and you will find the entry point for your specific de-embedding procedure. The ultimate tool for de-embedding with IC-CAP is the 'De-embedding Tool-kit' where a large number of ready-to-go solutions together with the theoretical background can be found. Please contact Dr. Franz Sischka from HP EEsof (franz_sischka@hp.com) for more details
c) Verification procedures
The BSIM3v3 Modeling Package provides a method to verify the de-embedding. It uses a THROUGH dummy test device. After a correct de-embedding of the parasitic components, the Sparameters of the THROUGH should show the behavior of an ideal, matched transmission line with Z0=50 Ohm and a TD which represents the electrical length of the through line in the THROUGH dummy device.
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The S11 and S22 curve should be concentrated in the center of the Smith chart, while S21 and S12 should both begin at (1+j*0) and turn clockwise on the unity circle. If this pre-assumptions are not given, the following items should be checked: Is the calibration o.k.? If the OPEN method is used, consider to enhance the de-embedding quality by using the OPEN_SHORT method, which removes the inductive parasitics in the measured data. If the OPEN_SHORT method is used and the frequency is very high (>30GHz), it should be checked, whether the assumptions for using OPEN_SHORT are still given. The easiest way to do this, is to model the OPEN and the SHORT device using the equivalent circuits given in Test_open and Test_short. More about de-embedding If you want to use another than the implemented OPEN or SHORT-OPEN de-embedding method, please contact Advanced Modeling Solutions. Through the open architecture of the BSIM3v3 Modeling Package an integration of new features can be done according to your specifications.
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Extraction of Model Parameters

This section describes the the parameter extraction sequence and the extraction strategy, and then provides an example.
Parameter Extraction Sequence

To get correct results please follow the procedure shown in Table 5-99. The macro Extract_all is programmed according to this procedure. Using this macro, everything is done automatically. Many of the extraction functions are equipped with error and plausibility checks. If an error occurs or some parameters have strange or unrealistic values, you will get an error warning at the end of the macro. In some cases it can be useful not to extract all the parameters. For instance if a 3.0 micron CMOS process has to be modeled with BSIM3, the typical short channel effects of the threshold voltage are not given and the extraction of the parameters DVT0, DVT1 etc. can result in very unrealistic values. In this case, you should configure the extractions using the macro Select_extraction. Every setup contains a transform extract_all. Please use this transform if you want to perform the extractions for this particular setup manually because many transforms require the execution of auxiliary transforms first, e.g. the extraction of some threshold voltages before short channel effects can be determined. In general, if the macro Extract_all produces errors, it is recommended to add the visual tuning feature (macro Select_extraction) to those parameters which caused the error. In a further run, the correspondent curves are simulated and displayed and the user can try to find the source of the error. The sequence of the model parameter extraction as it is implemented in the macro Extract_all is shown in Table 5-99 on the following pages. You can modify this extraction flow by editing the macro if you find that another sequence will better fit your special process. The model parameters which describe the high frequency behavior (ELM and Rsheet_gate) are extracted in a separate model in a less automated procedure. Table 5-99. Sequence of Model Parameter Extraction
Step 1 Extracted Parameters TOX Test Structures DUT/Setup
MOS capacitor C_Oxide/oxide_cap/extract_all
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Table 5-99. Sequence of Model Parameter Extraction (continued)

Step 2 Extracted Parameters CF CGSL, CGDL, CKAPPA CGSO, CGDO LINT, DLC 3 U0 VOFF, NFACTOR VTH0, K1, K2 UA, UB, UC 4 PRWG, RDSW PRWB UA, UB, UC 5 6 7 8 9 10 11 12 A0, AGS KETA NLX, DVT0, DVT1, DVT2 CDSC CDSCB CDSCD WINT K3, W0 K3B RDSW, WR WINT WW, WWN UA, UB, UC 13 14 WL, WLN DVT0W, DVT1W DVT2W diff. Small diff. Small Small/idvg_W/extract_all Small/vth_W/extract_all Small, Short diff. Narrow Small/idvg/extract_all Narrow/idvg_W/extract_all Short Narrow diff. Narrow Short/idvgh/extract_all Narrow/idvg/extract_all Narrow/vth_W/extract_all diff. Short Short Short/vth_L/extract_all Short/idvg/extract_all_sub Large Large/idvgh/extract_all Short Short/idvg/extract_all_lin Large Large/idvg/extract_all Test Structures parallel transistors DUT/Setup C_Overlap/overlap_cap/extract_all
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Table 5-99. Sequence of Model Parameter Extraction (continued)

Step 15 Extracted Parameters VSAT A1, A2 PCLM PDIBLC1, PDIBLC2 ALPHA0, ALPHA1, BETA0, PSCBE1, PSCBE2 16 17 18 19 20 21 ETA0, DSUB, DROUT ETAB NJ, IJTH JS, JSW CJ, MJ, PB CJSW, MJSW, PBSW CJSWG, MJSWG, PBSWG CLE, CLC Diode_perim Diode_area C_area C_perim C_Area/junc_cap_area/extract_al C_Perim/junc_cap_perim/extr. Diode/ibvd/extract_all diff. Short Short/vth_L_high_vds/extract_all Test Structures Short DUT/Setup Short/idvd/extract_all
C_perim_gate C_Perim_Gate/junc_cap_perim_gate/ extract_all Short C_Overlap/intr_cap/extract_all
Extraction Strategy
This section describes two aspects of the extraction strategy: a group extraction and a physically oriented model parameter extraction.
Group Extraction Strategy

A major enhancement of the BSIM3v3 model compared to older simulation models is that one set of model parameters covers the whole range of channel lengths and channel widths of a certain process which can be used in circuit designs. Many effects in the BSIM3 model depend very strongly on device dimensions such as the channel length and width. This is considered in the determination of model parameters in the BSIM3v3 Modeling Package through the use of a group extraction strategy.
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Figure 5-63 shows the principle procedure of model parameter extraction as it was used in older models like the MOS Level 3 model. The model parameter Px is determined from the measured electrical behavior of one single test transistor. The measured data is transformed in such a way that Px can be determined with regression methods.
Figure 5-63. Model Parameter Extraction from Single Devices In contrast, the group extraction strategy, which is shown in Figure 5-64 uses the measured electrical behavior of several test transistors with different gate lengths and gate widths.
Figure 5-64. Group Extraction Strategy In a first step, intermediate values like the threshold voltage Vth are determined and stored in a new data array as a function of gate length. In the next step, this new data array is transformed in such a way that the model parameters Px can be determined with regression methods. Parameters extracted with this method describe the behavior of the devices in a wide range of channel lengths and channel widths very good.
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Physically Oriented Model Parameter Extraction

For the determination of device model parameters from measured I-V or C-V curves, usually two general principles are applied - the optimization of the simulated device behavior or the parameter extraction based on the device equation. The basis of the optimization process is the simulation of a device with exactly the same inputs (voltages, currents) that are used to measure the device. The error between simulated and measured data is the cost function for the optimization algorithms which changes certain model parameters of the device, re-simulates it and checks whether the error has increased or decreased. The advantage of this procedure is that the fitting between the measured curves and the simulated ones can be very good, because the optimizer always tries to minimize this difference. However, in order to achieve this very good fitting, the optimization algorithm can give the model parameter physically unreasonable values. Another disadvantage is, that many optimization algorithms are not able to find the global minimum of the failure function which is the difference between measurement and simulation and the success of the optimization depends on the start values of the model parameters. The last difficulty which can arise by using pure optimization algorithms for the model parameter determination is that the boundaries for the optimization process must be set very carefully. This means that the user of the optimization algorithm must have good knowledge about the device model and where the different model parameters have their influence on the device behavior in order to restrict the optimization process to a certain range of data. In contrast to the optimization strategy, the extraction strategy is strictly based upon the device equations. If these device equations are physically oriented, as in the case of the BSIM3v3 model for MOS transistors, the extraction of the model parameters must give an accurate and realistic representation of the device physics. The basic idea of this extraction strategy is to transform measured data into such a form that model parameters of a certain part of the device equations can be derived by mathematical regression methods. The extraction routines must therefore incorporate much more knowledge about the model and its behavior. Generally, model parameters extracted in this way are more realistic and physically oriented. However, the fitting between the measured and simulated curves can be less accurate than in the case of an optimization, because the extraction method gives a realistic physical representation of the device while the optimization only targets a minimum error between measurement and simulations. Figure 5-66 shows the principle data flow of such an extraction routine for the short channel model parameters DVT0 and DVT1. In this example the threshold voltage Vth of several test transistors with different gate lengths is determined and stored in an intermediate data array. The short channel effect Vth is isolated in the next step from Vth as a function of gate length and bulk voltage Vbs. Figure 5-65 shows Vth as a function of those two variables. Only a subset of this data array is used for the determination of DVT0 and DVT1 and the boundaries for defining this subset are set by the extraction routine. As shown in the flowchart in Figure 5-66 different results
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from this action are possible. In the first case, no data point is available for the extraction and the user is informed with a warning message. This may occur for instance after measurement errors or with old CMOS processes which do not show a short channel effect. As a further possible result, only one usable data point is returned. From this data point one model parameter can be determined while the second one has to be set to its default value.
Figure 5-65. Short Channel Effects in Vth as a Function of Gate Length and Vbs
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In the normal case, a group of usable data points can be identified and transformed in such a way that DVT0 and DVT1 can be extracted through linear regression methods.
Figure 5-66. Extraction of Short Channel Effect Parameters DVT0, DVT1
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Example of an Implemented Model Parameter Extraction

We use the same example as described in the previous section to take a more detailed look at the extraction strategy of the BSIM3v3 Modeling Package. The extraction of the model parameters DVT0, DVT1, DVT2 and NLX is performed in the DUT Short and the setup vth_L. Figure 5-67 shows the structure of DUTs, setups and transforms within IC-CAP 5.0.
Figure 5-67. Setup vth_L with all Transforms used for the Model Parameter Extraction a) Control Flow The extraction of the four model parameters DVT0, DVT1, DVT2 and NLX is invoked in the macro Extract_all which controls all parameter extraction. There is a transform extract_all in every setup, which is responsible for the local control flow and for details of the model parameter extraction. The main part of this transform is shown next.
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UPDATE_MANUAL ! if DC_NO_SHORT > 0 then ! check for short devices L=/bsim_pel/Short_m.MAIN.L W=/bsim_pel/Short_m.MAIN.W !--- Initialize reset=0 iccap_func("failure","execute") ! failure check reset=1 ! reset failure condition !--- Start of extraction print "Start of extraction of parameters from short devices" print "----------------------------------------------------" print !--- calling aux.routines iccap_func ("Ldes","execute") ! start preparation of data iccap_func ("id_L","execute") iccap_func ("vg_L","execute") iccap_func ("vb_L","execute") iccap_func ("VTH_L","execute") ! Vth for all used devices iccap_func ("ident_curve_form","execute") ! identification ! of effects of Vth !--- calling extraction routines !--- NLX, check conditions for extraction, tuning, optimization if Extr_conf/Method_Conf/act_extr[35]==1 then iccap_func("extr_NLX","execute") ! invoke extraction end if if Extr_conf/Method_Conf/act_tune[35]==1 then iccap_func("tune_NLX_DVTx","execute") ! invoke tuning end if if Extr_conf/Method_Conf/act_opt[35]==1 then iccap_func("opt_NLX_DVTx","execute") ! invoke optimization end if : : iccap_func ( "failure", "execute" ) ! check failure conditions ! and write them to a logfile
In a first step, the failure conditions will be reset to zero. Then the data which is necessary for the parameter extraction is prepared as described in the section, Using IC-CAP Files for DC, CV and Diode Modeling. This step is followed by the extraction of the threshold voltage for all short
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devices and an identification of several short channel effects in the resulting vector Vth = f(Ldes). After this step, the first model parameter NLX is extracted. Three methods for the parameter determination are implemented, the physical based extraction, the parameter tuning and the optimization. Each of these options can be set as shown in Figure 5-68 in the configuration macro Select Extraction.
Figure 5-68. Part of the Configuration Macro Select_extraction After the extraction of all four model parameters, the failures which may have occurred are summarized and written to the failure log file log_fail. Automatic Extraction Dependent on the Device Physics All four model parameters NLX, DVT0, DVT1and DVT2 are extracted now from the vector Vth = f(Ldes). The strategy behind these procedure is to isolate every parameter or group of parameters in that region of operation where they dominate the device behavior.
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Tuning Approach The second possibility of the determination of a model parameter is to use the tuner function of ICCAP. Changing a model parameter with the tuner tune_NLX_DVT012 invokes the function visualize_VTH_L shown below. The tuner feature is a very intuitive method for model parameter extraction and uses the human brain which is much more flexible than any other optimization or pattern recognition algorithm to fit the simulated curve to the measured one.
Figure 5-69. Principle of the Tuner Function
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Optimization
The last method to determine the model parameters DVT0, DVT1, DVT2 and NLX is to use the optimization algorithm of IC-CAP. Here, the values of Vth = f(Ldes) must be extracted before the optimization can start.
Figure 5-70. Optimization Setup for DVT0, DVT1, DVT2, NLX
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Using IC-CAP Files for DC, CV and Diode Modeling

Strategy for Measurement and Model Parameter Extraction
For a better handling of the measured data, the BSIM3v3 Modeling Package contains two types of files for modeling:
Filename in UNIX MASTER_PEL.mdl MASTER_MEAS.mdl IC-CAP model name bsim_pel bsim3_meas
Using this strategy, the modeling task can be divided into two parts: The first model file bsim3_meas contains DUTs with the measured and simulated data and the definition of plots. It is used to perform measurements and to keep the fitted curves after the extraction. No extractions or optimizations are included in this file. All DUT names have the extension _m. Macros for an automatic setup of test and measurement conditions are provided to make the measurements fast and efficient. The second model file bsim_pel consists of two sections: again a data section with the actual measured and simulated data (DUTs with the extension _m) plus a section containing the extraction routines in DUTs like Large, Narrow, C_Area or Temp. The main interaction between both types of files is as follows: Perform the measurements using the model bsim3_meas Copy the data of the model bsim3_meas into bsim_pels data section (macro ___Import_data) Perform extractions (and optimization) in file bsim_pel (macro ___Extract_all) Export the final model parameter set back to the file bsim3_meas (macro ___Export_parameters)
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The Measurement File, bsim3_meas The model file bsim3_meas contains four kinds of DUTs, as shown in Figure 5-71.
DUTs for the configuration of the DUTs, the measurements and different temperature-dependent measurements
User-defined DUTs for DC measurements of diodes
User-defined DUTs for CV measurements
User-defined DUTs for DC measurements of transistors
Figure 5-71. DUTs in the file bsim3_meas
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The model file bsim3_meas contains four different kinds of macros, as shown in Figure 5-72
Macros with information
Macros for the configuration of the DUTs, the measurements and different temperature dependent measurements
Macros for measurements
Utilities
Figure 5-72. Macros in the file bsim3_meas
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The Extraction File, bsim_pel The model file bsim_pel contains four different kinds of DUTs, as shown in Figure 5-73.
DUTs with the model parameter extraction routines
DUT for the configuration of the parameter extraction Do not delete above this line !! DUTs with configuration information and user-defined DUTs with measured DC and CV data (with ending _m) imported from bsim3_meas
Figure 5-73. DUTs in the file bsim_pel
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The model file bsim3_pel contains four different kinds of macros, as shown in Figure 5-74.
Macros with information
Macros for the import and export of measured data and extracted model parameters
Macros for the extraction of model parameters
Utilities
Figure 5-74. Macros in the file bsim3_meas
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Setting up and Performing Measurements

Setting up Measurement Conditions
The measurement conditions can be configured using IC-CAP macros. Please run the macro Define_measurement_conditions in the bsim3_meas model. Items #1 through #5 select menues to configure the polarity of the devices to measure, the use of a switch matrix, and the measurement conditions of DC, CV, and diode measurements.
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The device polarity can be configured in menu item #1.
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In item #3, you can specify the different voltages for DC measurements. Please note that you always specify the values for n-type transistors; they will automatically be transformed to negative values if you have specified TYPE = -1 (PMOS) for a p-type transistor.
The same procedure is done with CV(item #4) and diode(item #5) measurement conditions.
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Setting up DUTs for Measurements

The devices for the extraction of the BSIM3v3 model parameters can be configured by the user. Please consider the requirements for the devices geometries, which are described in the section Test structures for Deep Submicron CMOS Processes. The following sections describe the whole setup for DC, CV, and diode measurements. Once the setup has been done, the measurement file can be stored and can be reused for an unlimited number of measurements.
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a) Modelname
Execute the macro Define_DUTs in the bsim3_meas model and configure your DC and CV DUTs. You will be prompted for the name of your model. If you would like to change the name, do it within this macro. Do not change the model name by simply renaming the model in the IC-CAP main window; this will disable the subcircuit simulation concept.!
b) CV Measurements
The procedure for setting up CV measurements is similar to the setting of DC measurements. You will first be prompted whether you want to perform CV measurements in general:
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The following menu allows a selection of different numbers of CV test devices. Specify them if necessary and continue. A warning window will inform you that the following operation may take some seconds. During this operation, DUTs will be deleted, copied or renamed. If you interrupt this procedure, the program runs into an undefined state and you will have to repair it manually. This warning will be shown in different steps of the program.
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The following choices allow you to disable the measurement of certain devices.
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The settings for the CV DUTs are displayed in the following window:
You can change each DUT by typing in the DUT number and then changing the values for this DUT. Please use only blanks as separators for different values.
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c) DC Measurements
In the first step you will be prompted for a definition of the numbers of different devices.
Specify them if necessary and continue. A warning window will inform you that the following operation may take some seconds. During this operation, DUTs will be deleted, copied or renamed. If you interrupt this procedure, the program runs into an undefined state and you will have to repair it manually. This warning will be shown in different steps of the program.
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The actual setting for the DC DUTs will be shown in the following window:
You can change the data of every single DUT by specifying the number of the DUT and you will be prompted for the following input:
You can change the name, the dimensions or the matrix port connections now. Different values must be separated by blanks. Comma or semicolon as separators are not allowed.
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If you are using more than the minimum set of devices, the following conventions must be maintained (example for different short devices):
DUT Short_m Short_m1 Short_m2 : Large_m 10 large device channel length [micron] 0.5 0.8 1.2 comment shortest designed channel length according to the design rules of the process
Example: Short_m is the DUT of the smallest device, Short_m1 is the DUT of the next larger device etc. The same convention applies to the series of Narrow and Small devices. If you have done the configuration, the channel lengths and channel widths of your test transistors are displayed in the following diagram. You should check again to ensure that the conventions explained above are maintained. If not, please re-run the Define_DUTs macro.
The program will now create the necessary DUTs for the DC test. Do not interrupt this procedure. If you want to change or correct a single parameter of a test device, e.g. the gate length of a certain transistor, you can also use the macro Change_DUTs which keeps the number of test devices and only changes certain parameters.
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d) Parasitic Diodes
The setup of measurements for the drain/bulk and source/bulk diodes is done in the same way as DC and CV setups.
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Perform Measurements
You can perform the measurements by selecting the "Measure" button for the different DUTs manually or you can invoke the macros DC_measurements or CV_measurements. In this case, the following menu will be displayed and you can select the current device to measure. The menu is nearly the same for CV measurements. Here you may first want to calibrate your measurement equipment with the IC-CAP calibrate command. For the use of a HP switch matrix, the macros DC_drive_matrix and CV_drive_matrix are supplied. Please check if the commands in this macro are the correct ones in case you are using another matrix.
If you are measuring at different temperatures, please heat up or cool down your devices to the given temperatures and run the macro DC_measurements in the correspondent model. You can either save all models in separate files or in a common file.
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Documentation of Test
The whole test and measurement setup can be printed for documentation. Please use the macro Print to select the different reports to print.
Performing Model Parameter Extractions

Import and Export Data
First setup your test environment (DUTs, measurement conditions etc.) in the model bsim3_meas and perform all the measurements. Then load the model bsim_pel into the IC-CAP model window. To import the measured data from bsim3_meas simply run the macro Import_data. This macro will first delete the existing DUTs with measured data in bsim_pel and replace them with the DUTs from bsim3_meas. Additionally, the whole setup information from the bsim3_meas model will be copied with the DUTs DUT_Configuration, Meas_Configuration and Temp_Configuration to the extraction model. You are now ready to perform your model parameter extractions.
Extract Model Parameters

The model parameter extraction strategy was just demonstrated in the previous sections. The BSIM3v3 Modeling Package offers a ready to go solution for the user to configure the extractions according to special needs. The other advantage of this flexibility is, that if one extraction routine gives unreasonable results, e.g. for unconventional processes, it is possible to comment out this extraction and implement a work-around using the tuner feature. The principle flow of such a parameter extraction is demonstrated below and was shown in detail in the section, Extraction of Model Parameters with the example of the length-dependent threshold voltage parameters NLX, DVT0, DVT1 and DVT2.
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In the first step, you can select whether you want to use all measured devices for parameter extraction. This can be helpful, if for instance an error in the measurement data was not recognized during the measurements and you do not want to re-measure all the devices. For this purpose call the macro Select_devices and you can make your selection in the window shown below:
In the next step, it is possible to select a certain parameter extraction strategy. If you call the macro Select_Extraction you can choose between three different methods for extracting a model parameter.
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While the parameter extraction routines in the BSIM3v3 Modeling Package are all physically oriented, it is very common that some things must be adapted to the CMOS process that is being characterized. For instance, this can be the fact that you are using a 3 micron process, where no short channel effects can be observed and therefore these parameters cannot be extracted or you have special processes with special effects which are not covered by the BSIM3v3 model. However, in most cases it is possible to find a work-around for these problems by adapting the parameter extraction strategy. The first one of three different extraction methods is the recommended physically oriented one, where the model parameters are extracted on the base of device equations (here called Extraction). The second one is the manual parameter tuning feature of IC-CAP. For every model parameter, such a tuning feature has been implemented and the user can manually try to fit the simulated curves to the measured ones. This may be very useful compared to the third method, the optimization. Experience has shown that the human brain is better able to determine a good fit than the relatively mechanistic optimization function which has the RMS error as a target function. If you do not want to extract a certain parameter, please de-select all three methods. Please try and compare all three methods with a simple example, e.g. the threshold voltage VTH0.
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Naturally, parameter extraction is not a linear process and you will need some iteration steps to find the best way in extracting the BSIM3v3.2 model parameters for your process. Before you start with the model parameter extraction, please run the macro Init_parameters and then run the extractions with Extract_all. You can watch the intermediate results of the parameter extractions in the status window. Any failures that occur during the extractions will be written to the file log_fail, which will be displayed after the extractions as in the example below:
Now you can verify your parameter extraction by simulating all measured DUTs using the macro Simulate_all. Using the macro Extract_all is the simplest and fastest way to perform model parameter extractions. However, it is also possible to do the extractions more manually. Before you start with them, please run the macro Init_parameters to reset the model parameters and perform a first simulation. Then you can run the different extract_all transforms described in the section, Extraction of Model Parameters manually. It is strongly recommended to use these extract_all transforms because they invoke all the necessary data preparation functions for a proper model parameter extraction. Using this method, you can also create your specific model parameter extraction strategy which really fits your special needs.
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In some cases, it may be necessary to change some boundaries for model parameter extractions. As an example, the lowest usable value for the drain current for the extraction of subthreshold parameters heavily depends on the quality of the measurements in this region of operation of a transistor. Therefore, this lowest limit can be changed manually to adapt the extractions to the available measured data with the macro Set_extraction_variables as shown below:
Export Model Parameters

After a succesful parameter extraction, you can export your model parameters to the bsim3_meas model or the related temperature dependant models and store them together with the measured data. Use the macro Export_parameters for this task.
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Naming Conventions
To keep the extraction routines as simple and fast as possible, no overhead for checking the semantics and syntax of the names of parameters, setups and DUTs is implemented. Therefore the following naming conventions must be strictly maintained. (Changing names will lead to errors and will disturb the extraction flow.) Do not delete the first twelve DUTs in bsim_pel: Large, Narrow, Short, Small, C_Area, C_Perim, C_Oxide, C_Overlap, C_Perim_Gate, Diode, Temp and Extr_conf. They include the extraction and optimization strategy. Do not change the model name bsim_pel. This would affect the path names in the macros (ICCAP_FUNC statements). For the names of the geometry parameters use capital letters like L, W, AD as proposed. The names of DUTs and setups for the measured data in the model file bsim_pel must be in the following style and the DUTs must at least contain the following setups (see original file set that you have been provided with):
DUT Setup Inputs/Outputs
Large_m
idvg idvgh idvd
vg, vd, vb, vs, id : vg, vd, vb, vs, id, ib : : :
Narrow_m Narrow_m1 : Short_m Short_m1 : Small_m
: : :
If you like to use more than the minimum set of devices, the following conventions must be maintained (example for different short devices):
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DUT
Channel Length [micron]
Comment
Short_m
0.5 according to the design rules of the process
shortest designed channel length
Short_m1 Short_m2 : Large_m
0.8 1.2 10 large device
Example: Short_m is the DUT of the smallest device, Short_m1 is the DUT of the next larger device etc. The same convention applies to the series of Narrow devices.
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Using IC-CAP Files for Temperature Modeling

Setting up Measurements at Different Temperatures
The extraction of the temperature model parameters requires that measurements at different temperatures are performed. The strategy of the BSIM3v3 Modeling Package is that one separate model file is created for every temperature. At the nominal temperature (T=300K or =27C) the full range of different transistors has to be measured. At all other different temperatures, only measurements on the LARGE, the SHORT and the SMALL transistors and the drain/source junction diodes DIODE_AREA and DIODE_PERIM are necessary. You can select between a full measurement setup for temperatures other than the nominal one and a reduced setup containing the DUTs described above. If you like to extract the temperature dependent parameters, please create the appropriate models with the macro Define_temperature_measurement in the model bsim3_meas.
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You can define the number of different temperatures and the program creates the correspondent models:
Please take care that you always re-run this macro if you change your DC DUTs or your DC measurement conditions in the model bsim3_meas. These conditions are directly copied to the temperature dependent models. Please heat up or cool down your devices to the given temperatures and run the macros DC_measurements or Diode_measurements in the correspondent model. You can either save all models in separate files or in a common file.
Extract Temperature Dependent Model Parameters

To perform extractions of temperature model parameters, you need to open different model files. Please see the window below for an example:
The models bsim3_meas and bsim3_meas_400K contain measured data at nominal temperature and at T=400K. The strategy of temperature parameter extraction is to extract first a set of model parameters at nominal temperature T=300K (=27C). For all other temperatures, a subset of
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temperature dependent DC model parameters, such as U0 or RDSW, is extracted. Both tasks are done by bsim_pel. From this subset of parameters, the temperature parameters like UTE or PRT are generated in a final step. The model bsim_temp controls the whole extraction and calculates the final model parameter set with all temperature model parameters from the single parameter sets at different temperatures. Run the macro Extract_temp in the bsim_temp model to start the extraction of temperature dependant model parameters according to the described strategy. You must restart the macro after the extraction of every model parameter set for a certain temperature.
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Perform the different steps, starting with the initialization as shown below:
Continue with the model parameter extraction at nominal temperature and different temperatures as shown in the IC-CAP window. In the final step, the temperature modeling parameters are created and stored in the resulting model parameter set. After a succesful parameter extraction, you can export your model parameters to the bsim3_meas model or the related temperature dependant models and store them together with the measured data. Use the macro Export_parameters for this task.
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Using the IC-CAP Files for AC Modeling

Strategy for Measurement and Model Parameter Extraction
For a better handling of the measured data, the BSIM3v3 Modeling Package contains two types of files for modeling the high frequency behaviour:
Filename in UNIX MASTER_AC_PEL.mdl MASTER_AC_MEAS.mdl IC-CAP name model
bsim_ac_pel bsim3_ac_meas
Using this strategy, the modeling task can be divided into two parts: The first model file bsim3_ac_meas contains DUTs with the measured data. It is used to perform measurements. No extractions or optimizations are included in this file. All DUT names have the extension _m. Macros for an automatic setup of test and measurement conditions are provided to make the measurements fast and efficient. In addition, this model file contains all the measurements and procedures for the de-embedding of the test devices. The second model file bsim_ac_pel consists of two sections: again a data section with the actual measured and simulated data (DUTs with the extension _m) plus a section containing the extraction routines in DUTs like S_parameter. The main interaction between both types of files is as follows: Perform the measurements using the model bsim3_ac_meas De-embedding of the measured device behaviour in bsim3_ac_meas Copy the data of the model bsim3_ac_meas into the data section of bsim_ac_pel's (macro___Import_data) Perform extractions (and optimization) in file bsim_ac_pel (macro ___Extract_all) Create a final sub-circuit for the high frequency macro model in file bsim_ac_pel
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Setting up and Performing Measurements

Setting up Measurement Conditions
The measurement conditions can be configured using IC-CAP macros. Please run the macro Define_measurement_conditions in the bsim3_ac_meas model. You will be asked for the device type to measure.
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In the next step, you can specify the different voltages for the DC and AC measurements. Please take care that you always specify the values for a n-type transistor! They will automatically be transformed to negative values if you have specified TYPE = -1 (PMOS) for a p-type transistor.
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Setting up DUTs for Measurements

The measurements for the extraction of the BSIM3v3 model parameters can be configured by the user. Please consider the requirements of the devices which are described in the section, Test structures for Deep Submicron CMOS Processes. The following sections describe the whole setup for AC measurements on S-parameter test structures. Once the setup has been done, the measurement file can be stored and can be reused for an unlimited number of measurements. Execute the macro Define_DUTs in the bsim3_ac_meas model and configure your DUTs. In the first window you will be prompted for a definition of the numbers of different devices.
Change the number if necessary and continue. A warning window will inform you that the following operation may take some seconds. During this operation, DUTs will be deleted, copied or renamed. If you interrupt this procedure, the program runs into an undefined state and you will have to repair it manually. This warning will be shown in different steps of the program.
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The actual setting for the AC DUTs will be shown in the following window:
You can change the data of every single DUT by specifying the number of the DUT and you will be prompted for the following input:
Now you can change the name, the dimensions or the comment. Different values must be separated by blanks. Commas or semicolons as separators are not allowed. Finally, the macro will generate the necessary DUTs for the AC test. Do not interrupt this procedure. If you want to change or correct a single parameter of a test device, e.g. the gate length of a certain transistor, you should use the macro Change_DUTs which keeps the number of test devices together with the measured data and changes certain parameters only.
Perform Measurements
You can perform the measurements by selecting the "Measure" button for the different DUTs manually or you can invoke the macros AC_DUT_measure or AC_OPEN_measure. The first macro is used for the DUTs and the second one for the OPEN test devices. Please note that the macro assumes one separate OPEN device existing for every DUT.
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In both cases the following menu will be displayed reminding you about the connections of the SMUs and network analyzer ports to the DUTs.
In the next step, you can select the device to be measured from the following table:
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Performing Model Parameter Extractions

Import Data and Project Directory
Set up your test environment (DUTs, measurement conditions etc.) in the model bsim3_ac_meas first and perform all the measurements. Then load the model file 'MASTER_AC_PEL.mdl' into the IC-CAP model window.
Please note, that 'MASTER_AC_PEL.mdl' is a macro model which contains four different single models 'bsim_ac_pel', 'bsim_mos_transistor', 'bsim_diode_perim' and 'bsim_diode_area'. The last three models (bsim_mos_transistor, ..., bsim_diode_area) contain single models for the MOS transistors and the junction diodes, while the model bsim_ac_pel contains the sub-circuit description of the RF BSIM3v3 model, the extraction routines and all other control macros.
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Please see the following flow-chart for an explanation of the data flow between the different model files.
To import the measured data from 'bsim3_ac_meas' simply run the macro 'Prepare_data' in 'bsim_ac_pel'. You will be prompted to define a project directory, where the .mdm files and the resulting SPICE subcircuits are stored. The name of this directory is /home/iccap/bsim3/project in our current example. In addition, the name of the model parameter set which contains the DC and CV model parameters already extracted in a former session using the bsim_pel model has to be specified (see the following window). After all these specifications, the macro writes the measured data in separate .mdm files for every DUT in the project directory. The device specific information, like gate length or gate width etc. is copied to the 'bsim_ac_pel' model. This structure of data storing has been choosen because Sparameter measurements usually generate a huge amount of data which can slow down IC-CAP when it is permanently present in one big model file.
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Now, the pre-requisites for extracting model parameters are given and the 'bsim3_ac_meas' model can be closed and removed from the main window.
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Using the macro 'Extract_all' gives you all the information to perform model parameter extractions. In contrast to the extraction of DC and CV model parameters, the high frequency modeling for the RF BSIM3v3 macro model requires more user interaction. Please use the functions which are described below to perform this modeling.
In general, two major steps are required for successful high frequency modeling - a correct representation of the DC and CV behaviour and a fit of the external parasitic elements of the macro model. The physical background of the modeling strategy is explained in detail in the section High Frequency Behavior.
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Extract Model Parameters

The strategy for high frequency modeling inside the BSIM3v3 Modeling Package is to create a SPICE sub-circuit for each RF test transistor. Therefore, the measured data of this test transistor must be loaded from the data base into the project directory prior to extraction. You can perform this task using the macro 'Load_one_DUT':
You can select the device to extract. Before you start with the model parameter extraction, please run the macro 'Init_parameters' to reset the model parameters and calculate some constants.
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The DC extractions provide you the possibility to re-adjust some selected DC model parameters to enhance the fitting quality of the output curve and the output resistance of the AC test devices. Please see the selection of functions in the window below.
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The main modeling part is done with the extraction functions in DUT/Setup Extract/S_parameter. Please see the README transform for more information.
Export Model Parameters

After successful parameter extraction, you can store your model parameters and the circuit descriptions for the MOS transistor, the diode models and the macro model in the project directory using the 'Save_circuits' macro. This information can be reloaded using the macro 'Load_circuits'.
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To use the extracted macro model in a SPICE like simulator, the macro 'Create_subcircuit' generates the necessary subcircuit:
The subcircuit is generated for the general UC Berkeley SPICE input format, which is used e.g. in SPICE3e2. Please see the example below for the format of the sub-circuit. The generation routine can easily be customized to add additional features of commercial simulators.
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* ************************************************************************** * * Subcircuit of the BSIM3 RF macro model * * * created by the 'BSIM3v3 Modeling Package' * * * * * * The subcircuit contains the ideal MOS transistor modeled with the UCB * * * BSIM3v3.2 model and additional peripheric elements to enable high * * * frequency simulations * * * * * * Advanced Modeling Solutions, October 1999 * * ************************************************************************** .SUBCKT Device_1_bsim3_hf 1 2 3 * .MODEL bsim_mos_transistor NMOS + LEVEL = 8 VERSION = 3.2 MOBMOD = 1 CAPMOD = 3 ..... NOIC = -1.4E-12 * .MODEL bsim_diode_area D + CJ0 = 0.0005 VJ = 1 M = 0.5 IS = 9.5E-05 N = 1.05 * .MODEL bsim_diode_perim D + CJ0 = 5E-10 VJ = 1 M = 0.33 IS = 8.7E-11 N = 1.05 * * ***************************************************** * * Subcircuit of the BSIM3 RF macro model * * * for n-type MOS transistors * * ***************************************************** *.SUBCKT bsim_ac_pel 1 2 3 * --------- Gate network -----------------------------Lgate 2 20 1E-12 Cgd_ext 20 11 1E-16 Cgs_ext 20 30 0 Rgate 20 21 1 * --------- Drain network ----------------------------Ldrain 1 11 1E-12 * --------- Substrate network ------------------------* Diodes are for n-type MOS transistors * Djdb_area 12 11 bsim_diode_area AREA = 3E-11 Djdb_perim 12 11 bsim_diode_perim AREA = 4E-11 * Djsb_area 31 30 bsim_diode_area AREA = 6.6E-05 Djsb_perim 31 30 bsim_diode_perim AREA = 8.8E-05 * Rsub2 12 40 1 Rsub3 31 40 1 Rsub1 40 30 1 * --------- Ideal mos transistor ---------------------MAIN 11 21 30 40 + bsim_mos_transistor L = 3.5E-07 W = 6E-05 AD = 0 AS = 0 PD = 0 PS = 0 * RGND 3 30 0.001 * .ENDS
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Model Variables in bsim3_meas and bsim_pel

The following list gives the minimum required model variables which are used within the 'bsim_pel' model. The list might be important if you wish to extract parameters with 'bsim_pel' that refer to measurement data obtained with model files other than 'bsim3_meas'. Please make sure that you do not delete any of these model variables and that you are not modifying the variables in self-written macros or transforms.
Variable _General_settings TYPE POLARITY OPEN_RES SIMULATOR COX esi esio2 q kb Eg0 Vtm PHI NI TEMP TNOM gen_fail fail_file VBM NSUB NCH
Setting 1 NMOS 1.0E12 spice3 0.00627545 1.04E-10 3.4515E-11 1.60219E-19 1.38062E-23 1.17 0.0344683 0.684466 7.04291E+12 27 27 1 11 2 1.77434E+17 1.44486E+17
Comment device type " constants for simulation " constants for extraction " " " " " " " " defined by user " failure indicator file descriptor for failure file model parameters not included in the circuit "
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Variable XT _Data NOM_DATASOURCE DATASOURCE MODELNAME __DC_variables tmp_pind tmp_ping tmp_pins tmp_pinb DC_VGSTART_VD DC_VGSTEP_VD DC_VDSTART DC_VDSTOP DC_VDSTEP DC_VGSTART
Setting 1.5E-07 bsim3_meas bsim3_meas_400K bsim_pel 15 18 43 17 0.9 0.4 0 2.5 .1 0
Comment " model name of measured data like above at TEMP 27 DO NOT CHANGE pin assignment for switch matrix " " settings for DC measurements " " " " "
Variable DC_VGSTOP DC_VGSTEP DC_VBSTART DC_VBSTOP DC_VBSTEP DC_VGSTART_VD DC_NO_ADD DC_NO_LARGE DC_NO_NARROW DC_NO_SHORT
Setting 2.5 0.1 0 -2 -0.5 0.9 0 1 0 1
Comment " " " " " " number of DC DUTs " " "
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Variable DC_NO_SMALL DC_NO_TRAN DC_L[0] DC_L[1] DC_L[2] DC_L DC_W[0] DC_W[1] DC_W[2] DC_W DC_DUT[0] DC_DUT[1] DC_DUT[2] DC_DUT __CV_variables CV_DUT CV_L CV_W CV_n CV_AREA CV_PER CV_TEST CV_VGSTART CV_VGSTEP CV_VBSTART CV_VBSTOP CV_VBSTEP CV_NO_TRAN __Temp_variables
Setting 1 3 1E-05 2.5E-07 2.5E-07 ICCAP_ARRAY[3] 1E-05 1E-05 3.2E-07 ICCAP_ARRAY[3] Large_m Short_m Small_m ICCAP_ARRAY[3] ICCAP_ARRAY[0] ICCAP_ARRAY[0] ICCAP_ARRAY[0] ICCAP_ARRAY[0] ICCAP_ARRAY[0] ICCAP_ARRAY[0] ICCAP_ARRAY[0] 2.5 0.1 -2 0.2 0.1 0
Comment " " geometry of DC devices " " " " " " " names of meas. DC DUTs " " " names of meas. CV DUTs geometry of CV devices " " " " flag for measured CV data settings for CV measurements " " " " number of CV Duts
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Variable TEMP_NO TEMP_TEMP[0] TEMP_TEMP[1] TEMP_TEMP[2] TEMP_TEMP TEMP_MEAS_ALL __Diode_variables
Setting 3 300 250 400 ICCAP_ARRAY[3] y
Comment number of measured temp. different temperatures " " " flag for temperature meas.
Variable DI_DUT[0] DI_DUT[1] DI_DUT DI_AREA[0] DI_AREA[1] DI_AREA DI_PER[0] DI_PER[1] DI_PER DI_TEST[0] DI_TEST[1] DI_TEST DI_NO_TRAN DI_VBSTART DI_VBSTOP DI_VBSTEP __Extraction_settings idmin_voff
Setting Diode_Area_m Diode_Perim_m ICCAP_ARRAY[2] 4E-10 5E-10 ICCAP_ARRAY[2] 8E-05 0.001 ICCAP_ARRAY[2] y y ICCAP_ARRAY[2] 2 -0.6 0 20m 1e-9
Comment names of meas. diode DUTs " " geometry of diode devices " " " " " flag for measured diode data " " number of diode DUTs settings for diode measurements " " user definable settings for
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Variable AREA_CLM_DIBL idmin_js idmin_cds PR_CMD mins[0] mins maxs[0] maxs params[0] params inits[0] inits scale[0] scale CV_NO_BASIC CV_NO_OVER CV_NO_INT CV_VGSTART_VD CV_VGSTOP_VD CV_VGSTEP_VD CV_VDSTART CV_VDSTOP CV_VDSTEP vgd_extr vs_extr MESSAGE
Setting 2 1e-10 1e-11 lp -dlaser -0.921219 ICCAP_ARRAY[1] 0.5 ICCAP_ARRAY[1] PRWB ICCAP_ARRAY[1] -0.01224 ICCAP_ARRAY[1] 0 ICCAP_ARRAY[1] 4 2 2 0 2.5 0.5 0 2.5 0.1 1.2 1.2 1
Comment parameter extraction set in macro 'Set_extraction_variables' variables for tuning " " " " " " " " " number of basic CV DUTs number of overlap DUTs number of DUTs for intr. cap. measurement conditions for intrinsic capacitance measurement " " " Bias point for extraction of CLC, CLE switch of input windows in extraction transforms (1=on / 0 = off)
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References
[1] "BSIM3 Manual," University of California at Berkeley, March 1997 [2] "Characterisation System for Submicron CMOS Technologies," JESSI Reports AC41 94-1 through 94-6 [3] Peter Klein, "A consistent parameter extraction method for deep submicron MOSFETs," Proc. 27th European Solid-State Device Research Conferenc, Stuttgart, 1997 [4] "Layout Rules for GHz Probing", Application Note Cascade Microtech [5] F. Sischka, "Deembedding Toolkit," Hewlett-Packard GmbH, Bblingen, Germany [6] File: "deemb_short_open.mdl" in IC-CAP examples, Hewlett-Packard EEsof [7] W. Liu et al., "R.F. MOSFET Modeling Accounting for Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3 SPICE Model," Proc. IEEE IEDM, 1997 How to get the BSIM3v3 manual from University of Berkeley/California: University of Berkeley/California provides a comfortable way to get a free copy of the BSIM3v3 manual and the BSIM3v3 source code from their world-wide web home page: http://www-device.EECS.Berkeley.EDU/~bsim3/
References
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Other useful internet addresses: Advanced Modeling Solutions: http://www.admos.de Compact Model Council in the United States (standardization of the BSIM3v3 model). http://www.eia.org/eig/CMC/ Agilent EEsof homepage http://www.tm.agilent.com/tmo/hpeesof
Copyright
BSIM3 is developed by the Device Research Group of the Department of Electrical Engineering and Computer Science, University of California, Berkeley and copyrighted by the University of California.
References
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Chapter

Chapter 5: BSIM3v3 Characterization

Mobility reduction due to vertical fields

Bulk charge effect Subthreshold conduction Source/drain parasitic resistance

Short channel capacitance model Temperature dependence of the device behavior

Versions of the BSIM3 Model

Versions of the BSIM3 Model

The Unified I-V Model of BSIM3v3

The Unified I-V Model of BSIM3v3 5-4

eff& % D L ! VT1 -------lt "

W eff L eff& % D ------------------! VT1w 2l tw "

W eff L eff& % D ------------------! VT1w l tw "

T ox + ( K 3 + K 3b V bseff ) ------------------------------- s ( W eff + W 0 ) e

eff& % D L ! sub -------l t0 "

( E ta0 + E tab V bseff ) V ds

Ideal Threshold Voltage

The Unified I-V Model of BSIM3v3 5-5

Non-Uniform Vertical Channel Doping

The Unified I-V Model of BSIM3v3 5-6

(6) (7) (8)

The Unified I-V Model of BSIM3v3 5-7

Figure 5-2. Threshold Voltage Vth as a Function of Vbs

The Unified I-V Model of BSIM3v3 5-8

Non-Uniform Lateral Channel Doping

The Unified I-V Model of BSIM3v3 5-9

The Unified I-V Model of BSIM3v3 5-10

Short Channel Effect

si T ox X dep ---------------------------- ( 1 + D VT2 V bseff ) sio2 2 si ( s V bseff ) ------------------------------------------qN ch

K B T % N ch N d& - ln # ---------------= -----------$ q ! n2 " i

The Unified I-V Model of BSIM3v3 5-11

Narrow Channel Effect

The Unified I-V Model of BSIM3v3 5-12

Figure 5-6. Influence of Narrow Channel Effects on the Threshold Voltage

The Unified I-V Model of BSIM3v3 5-13

Threshold Voltage Reduction Through DIBL

( E ta0 + E tab V bseff ) V ds

si T ox X dep --------------------------- sio2

The Unified I-V Model of BSIM3v3 5-14

Carrier Mobility Reduction

Figure 5-7. Influence of Mobility Reduction

The Unified I-V Model of BSIM3v3 5-15

Figure 5-8. Effective Mobilityeff as a Function of Gate- and Bulk-Source-Voltage

The Unified I-V Model of BSIM3v3 5-16

Effective Channel Length and Width

The Unified I-V Model of BSIM3v3 5-17

Figure 5-10. Channel Length Reduction dL as a Function of Channel Length L

The Unified I-V Model of BSIM3v3 5-18

Effective Channel Width

Figure 5-11. Influence of Channel Width Reduction on the Drain Current

The Unified I-V Model of BSIM3v3 5-19

Figure 5-12. Channel Width Reduction dW as a Function of Channel Width W

The Unified I-V Model of BSIM3v3 5-20

The Unified I-V Model of BSIM3v3 5-21

The Unified I-V Model of BSIM3v3 5-22

Figure 5-14. Effective Voltage Vdseff

The Unified I-V Model of BSIM3v3 5-23

Drain Saturation Voltage Vdsat

The Unified I-V Model of BSIM3v3 5-24

Bulk Charge Effect

The Unified I-V Model of BSIM3v3 5-25

The influence on the drain current is visualized in Figure 5-17.

Figure 5-17. Influence of A0 and KETA on Ids at High Drain Voltages

The Unified I-V Model of BSIM3v3 5-26