W

????

W
KW
WW
K K
K K

K K
K K

K K
KW
W
W
K J
KPower point J
W

--

Introduction
?Binary numbering system?

K?Digital Electronic Circuits?

Numbers Systems J

W
KK

KK

KK
KK

Decimal Numbering System J

?10?

K?0,1,2,3,4,5,6,7,8,9?

8W128K?Positional Weight?

218E100 =1F

2E101 =10F

E102 =100 F110

WK1001
1

102

101

100

1102 + 2101 + 8100

(128)10Z 100+

20 +
--

W10-1

KKK102

101

100 10-1

10-2

10-3 ...

(DecimalPoint)

Binary Numbering System J

?2?

W?2? ?1,0?
... 24

23

22

21

20

W (25)10(11001)2
24
1

23

22

21

20
1

(11001)2 = (124) + (123) + (022) + (021) + (120)

= 16 + 8 + 0 + 0 + 1 = (25)10
W
WNumber of Binary Combinations

WNK?Bits?
N 2 n (1-1)

K?Bits? nW

N 2 2 4 W?2?
3
N 2 8 W?3?

--

N 2 4 16 W?4?
W?Bit?

21?1??1?20
K ?4?22?2?

?LSB??Least Significant Bit?

?Most Significant Bit?

K?MSB?

Decimal-to-Binary Conversion J J
Repeated ?2

K?Division-by-2 Method

W
214W(14)10

.2

K
W?MSB??LSB?
14
7
3
1

2
2
2
2

=
7
0
=
3
1
=
1
1
=
0
1
1 1 1 0
MSB

LSB

(14)10 = (1110)2 W
--

K(25)10WE JF

25 2 =12
1 (LSB)
12 2 =6
0
6 2 =3
0

3 2 =1
1
210 =0
1 (MSB)
W
1(25)
= (11001)2

K(87)10WE JF

87 2 = 43
1 (LSB)

43 2 = 21
1
21 2 = 10
1
10 2 = 5
0

5 2=2
1
2 (87)
210==1(1010111)02W
1 2=0
1 (MSB)
:W

K2

?Decimal Fractions?

W(0.3125)102

MSB ( 0 . 0 1 0 1 )2 LSB
KEF

0.3125 2 = 0.625
0

0.625

0.25
0.5

2 =

1.25

2 =

0.5

2 =

1.0

K(39.25)10WE JF
--

39 2 = 19

(LSB)

19 2 = 9
1
9 2=4
1

4 2=2
0
2 2=1
0
(39)10 = (100111)2W
1 2=0
1 (MSB)

W2
MSB ( 0 . 0

1 )2 LSB

0.25 2 = 0.5
0 (MSB)
0.5 2 = 1.00

(LSB)

(0.25)10 = (0.01)2W

(39.25)10 = (100111.01)2W
Binary-to-Decimal Conversion J J
?Bit?

K(1101001)2WE JF

26
1

25

24 23

22

21

20W

1W

(1101001)2 = 1 26 + 1 25 + 0 2 + 1 23 + 0 22 + 0 21 + 1 20

(1101001)2 = (105)10 W

--

?Binary Point? ?Bits?

24

23

22

21

20 2-1

2-2

2-3

2-4.

K (0.1011)2WE JF

2-1

2-2

2-3

2-4

0K1000
(0.1011)2 = 12-1 + 02-2 + 12-3 + 12-4
= 0.5 + 0 + 0.125 + 0.0625 = (0.6875)10
Hexadecimal Numbering System J
?16?

?A,B,C,D,E,F??0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F?

K?10, 11, 12, 13, 14, 15?

HexadecimaltoDecimal Conversion J J

?KKK163 162 161 160??16?

W(522.39)16?... 4096 256 16 1?

162
5

161

160

16-1

16-2 W

9 W

(522.39)16 = 5162 + 2161 + 2160 + 316-1 + 916-2

= 5256 + 216 + 21 +30.0625+ 90.0039062
= 1280 + 32 + 2 + 0.1875 + 0.0351558
(522.39)16 = (1314.222655)10 W
--

Decimal-to-Hexadecimal Conversion J J

?16?

K?2? ?16?

WW
?16?97(97)10

K?16?

?MSB??LSB?K
W

97 16 = 6
6 16 = 0

1
6

(LSB)
(MSB)

W
(97)10 = (61)16
K(314)10WE JF

314 16 = 19
19 16 = 1
1 16 = 0

A
(LSB)

3
1

(MSB)

(314)10 = (13A)16
--

K?16?

MSB ( 0 . C

0.78125
0.5

x16 = 12.5
x16 = 8.0

C
8

8 )2 LSB

(0.78125)10 = (0.C8)16 W

K(329.52)10WE JF

W?16?

329 16 = 20
20 16 = 1
1 16 = 0

9
4
1

(LSB)
(MSB)

(329)10 = (149)16 W

W?16?

0.52 16 = 8.32
0.32 16 = 5.12
0.12 16 = 1.92
0.92 16 = 14.72
0.72 16 = 11.52
0.52 16 = 8.32

8
5
1
E
B
8

(MSB)

(LSB)

(0.52)10 = (0.851EB8)16W?6?
(329.52)10 = (149.851EB8)16 W
--

:Hexadecimal-to-Binary Dirct Conversion J J

?A,B,C,D,E,F??0,1,2,,9,A,B,C,D,E,F?

?10,11,12,13,14,15?

KE JF?4-bit?
WE JF

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

10

1011

11

1100

12

1101

13

1110

14

1111

15

K(3A5)16WE JF

(3A5)16 =

3
0011

A
1010

5
0101 = (001110100101)2
- -

K(B35.D1)16WE JF

(B35.D1)16 = B

1011 0011 0101 1101 0001 = (101100110101.11010001)2

:Binary-to-Hexadecimal Direct Conversion J J

K
K(110111101.101001)2WE JF

0001

1011

1101

1010

0100
4

K
(110111101.101001)2 = (1BD.A4)16

K(110101011.01101)2WE JF

0001
1

1010
A

1011
B

0110

1000
8

(110101011.01101)2 = (1AB.68)16
- -

WArithmatic Operations in Binary System J

Addition of Binary Numbers J J

?Binary Digits?

0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0 Carry EF 1 = (10)2

10102?2?1 + 1

K011, 100WWE JF

4
+3
EF 7

1
+0
1

0
1
1

0
1
1

K011, 110WWE JF

1
6
+3
EF 9

1
1
+0
0

1
1
0
- -

0
1
1

W Subtraction of Binary Numbers J J

W
KW

KW

EF

00=0
10=1
11=0
01=1

?1?

W
K

W
K

?0??1??0??1?W
K?0??1??1?

K
K(101)(011)WE JF

01
1
K11102
- -

0
1

1
0

0
0

1
1

1
0

:1's and 2's Complements of Binary Numbers J J

K

W?1??0??0??1?
1 0 1 1 0 0 1 1
0 1 0 0 1 1 0 0

W
?1?KW

1HZW

10110011

K?1?
1 0 1 1 0 0 1 1

0 1 0 0 1 1 0 0
1+
0 1 0 0 1 1 0 1

?1?

(LSB)W

?1??0?

K
K

W(10101101)2

1 0 1 0 1 1 0 1
0101001 1
- -

WRepresentation of Signed Numbers J J

?1??0?

?Sign?

K?Magnitude?

K?2's Complement??1's Complement??Sign-Magnitude?

WSign-Magnitude System W

?Bit?

K
W(+23)

00010111

(Magnitude Bits)

(Sign Bit)

W (-23)
10010111

K(23) (+23)

- -

W1's Complement System W

(23) K
W

00010111
11101000

(+23)
(23)

K
W2's Complement SystemW

KK
W(+23)(23)
(+23)

00010111

(23)

11101001

K
Arithmetic Operations of Signed Numbers J J

KE JF

K
- -

01111010 00001110WE JF
K

01111010
+11110010
(Discard carry)

(+122)

(+108)

111101100

122 (14) = 108

K(00001000)2 (00000100)2WWE JF

W
( +8)

00001000

1 0 0 0 0 0 1 0 0 (+4)

+11111100

(Discard carry)

8 4 = 8 + (-4) = 4
- -

K(01100111)2 (00001001)2WE JF

W
01100111

( +103)

+11110111

101011110

(+94)

(Discard carry)

103 (9) = 94

- -

W E JF
a) 64
e) 77.0625

b) 112
f) 47.875

c) 257
g) 33.125

d) 27.26

W E JF
a) 11011
e) 10101.1101

b) 1110101
c) 111111
f) 1100001.11011

d) 1110.11

WE JF
a) 14
e) 62500

b) 80
f) 204.125

c) 560
g) 255.875

d) 3000
h) 631.25

WE JF
a) 9F
e) F.4

b) D52
f) B3.E

c) 67F
g) 1111.1

d) ABCD
h) 888.8

WE JF
a) 8

b) 1C

c) A64

d) 1F.C

e) 239.4

WE JF
a) 1001.1111
d) 10100111.111011

b) 10000.1
e) 1000000.000111

c) 110101.11001
f) 1111100.1000011

WE JF
a) 100 + 111
c) 1111 + 1101

b) 1110.11 + 11.10
d) 1001.101 + 1101.11

WE JF
a) 1101 0100
c) 11010 10111

b) 1001 0111
d) 1100 1001
- -

WE JF
a) 00110101

b) 11100100

c) 00010101

WE JF
a) 11110110

b) 01011101

c) 00110011

E JF
W(8-bits)

a) +28

b) 83

c) +99

d) 120

E JF
W(8-bits)

a) +14

b) 63

c) +107

d) 122

KEFE JF
WE JF
a) 101110001

b) 01100100

c) 10110011

WE JF
a) 10011101

b) 01100110

c) 10101101

WE JF
a) 10101011

b) 000111101

c) 10111011

WE JF
a) 00010110 00110011
c) 10001100 00111001

b) 01110000 10101111
d) 11011001 11100111

- -

W
KW
WW
K K
K K

K K
K K

K K
K K
K K

KW
W
W
K J
Power point J
K

W
K
- -

Introduction

WLogic Gates J
WAND Gate AND J J
?Logic Functions?AND

?Logical Multiplication?

?Two Binary Variables?BA E JF

?1??Open? ?0?
K?Closed?

(A)

Voltage Source

(B)

(L)

ANDWE JF

E JFK

(L)(L)
K?Truth Table?

- -

E JFWE JF
A

ANDWE JF

E JF AND ?Standard? E JF

KAND

ANDWE JF

?1?A, B?1?

?1? AND

nNK?1?
W

N 2n

(2.1)

- -

AND JWE JF

KAND J

W J
N 2 n 25 32

E JFK 23 8 WAND J
K

ANDWE JF

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
1

?Boolean Algebra?

?Boolean Expression?

WAND

Y A.B

or

Y AB

(2.2)

E JF?LOW??HIGH??Pulses?

Yt1?1?A, B

B?0?At2?1?
- -

K?0?Y
K?Timing Diagram?

B
t1

t2

t3

t4

t5

t6 t7

AND
WE JF
OR Gate OR J J

ORK OR

?Logical Addition?

KE JF
(A)

(L)

(B)

Voltage Source

OR
WE JF

?0? BAAND

K?Closed? ?1??Open?
E JFWE JF
A

- -

E JF

K (L)

ORWE JF

E JFORE JF

?1??1? OR

WORK?0??0?
Y A B

(2.3)

ORWE JF

B
0
1
0
1

0
0
1
1

Y
0
1
1
1

t1?1?BAE JF

At2?1? Y

KK?1? YB?0?

B
t1

t2

t3

t4

t5

t6

A
t7

KORWE JF

- -

NOT Gate (INVERTER) J J

NOTWE JF

?0??1?
NOT K?1? ?0?

E JF

K?Complementation??Inversion?

NOT

KE JF

NOTWE JF

E JF

YA

(2.4)

NAND Gate NAND J J

NAND WE JF

A
0
0
1
1

B
0
1
0
1
A
B

Y
1
1
1
0
Y

NANDWE JF

NOTNAND

AND AND

E JFAND

AND

K

E JF
K NAND

?1? ?0?

NAND?0? ?1?

- -

ANDORNOT
WNAND

Y AB

(2.5)

t1?1?BAE JF

At2?0? Y

?1?Y?1?B?0?
K

A
A

B
t1

t2

t3

t4

t5

t6

t7

NAND
WE JF

NOR WE JF

A
0
0
1
1

B
0
1
0
1

OR NOT NOR

Y
1
0
0
0

A
Y

NORWE JF

NOR Gate NOR J J

OR

NOT

E JF OR
NOR

NOR

KE JF

?0?Y

?0??1? ?1?

NANDNOR

WNORKAND OR NOT
- -

Y A B

(2.6)

BANORE JF

K?Y?NOR

t5

t1

t2

t3

t4

NOR
WE JF
XORWE JF

A
0
0
1
1

B
0
1
0
1

? XOR

Y
0
1
1
0

XORWE JF

Exclusive-OR Gate XOR J J

XOR - gate ?

E JF

E JF K

Y XOR
K B A ?1?

W
Y A B AB A B

(2.7)

XORBA

E JFNOTORAND
XORE JFKXOR

K
- -

A
B

K NOTORAND XOR WE JF

A
B
t1

t2

t3

t4

t5

t6 t7

t8

A
B

XOR WE JF

Exclusive-NOR Gate XNOR J J

A

XNORWE JF

XORXNOR

KE JF

YE JFXNOR

?0? A=B=1A=B=0 BA?1?

- -

XNOR WE JF

A
0
0
1
1

B
0
1
0
1

Y
1
0
0
1

W
Y AB A B = A B

(2.8)

XNOR

E JF NOT ORAND
KXNOR

NOTORAND
XNORWE JF

BAXNORE JF

K?Y?XNOR

B
t1
Y

t2

t3

t4

t5

t6

t7

A
t8

XNORWE JF

- -

Boolean Algebra J
The Boolean Expression for a Logic Circuit J J

WE JF

K AB A, B WANDK

K A C A, C WANDK

K AB A C A B , A C WORK
Y AB A C W

AB

B
Y
C

AC

KWE JF

KE JFWE JF

A

A B

D A B

BC

E JFWE JF

- -

E JF

Y D ( A B ) (B C )

(2-9)

W J J
Implementation of Logic Circuit Using Boolean Expression

W
(2-10)

Y AB(CD EF )

CD EF BA

FEAND C D CD EF AND

ORAND
AND

W AB(CD EF )
K D NOTK

K CD , EF ANDK
K CD EF ORK

KYANDK
KE JF
A
B

C
D
E
F

K Y AB(CD EF ) WE JF

- -

J
Implementation of the Logic Circuit via Truth Table

Y 1E JF K
A 0, B 1, C 0 Y 1

?1? A BC

K ABC ?1??0?
K

WE JF
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

OR Y 1

C
0
1
0
1
0
1
0
1

Y
0
0
1
0
0
0
1
0

Y A BC ABC

A BC

A, B , C ABC AND A , B , C

ORAND

KE JFKY

B
C

WE JF
Y A BC ABC

- -

WE JF

KE JF

WE JF

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1
0
1
0
0

OR Y 1

Y A B C A BC AB C

KE JF

B
C

A B C A BC AB C WE JF

W J
Converting of Boolean Expression to a Truth Table

(22 = 4)(1 or 0)

K(23 = 8)
- -

?0?Y?1?

WWE JF
Y A B C A BC ABC ABC

?A, B, C ?

KE JF

A B C 000 , AB C 010 , AB C 110 , ABC 111

(2-11)

Y?1?

KY?0?

WE JF

- -

W J
Simplification of Boolean Expressions Using Rules of Boolean algebra

E JFK

WE JF
A + 0 = A

A + 1 =1

A . 0 = 0

A
A
A
A
A

. 1 = A
+ A=A
+ A =1
. A=A
. A =0
A =A
A + AB = A
A+AB=A+B
(A+B)(A+C)=A+BC

5
6
7
8
9
10
11
12

WWE JF
Y AB A( A C ) B( A C )

(2-12)

Y AB AA AC AB BC W

Y AB A AC AB BC WE7FAAA

Y AB A AC BC WAB + AB = ABA + A = A5

Y A( B 1 C ) BC W
A

Y A.1 BC WA+1=12

Y A BC WA.1= A4
- -

E JF

?EF?

K?EF?

A
B

B
C

EF

E JFWE JF

EF

KWE JF
Y A B C A B C A BC ABC

(2-13)

- -

Y A B C A B C A BC ABC AB C C BC A A

(2-14)

Y A B 1 BC 1 W6
Y A B BC W4

A
B
C

A
B
Y

Y
C

EF

EF

WE JF

- -

A, BANDXE JF
KE JF

A
B

E JF

A, BORXE JF
KE JF

A, BNANDXE JF
KE JF

E JF

BANORXE JF
KE JF

E JF

BAXORXE JF
KE JF

- -

BAXNORXE JF
KE JF

KE JFE JF
A
B
C

E JF

WE JF
b) AB AB A BC

a) AB A B
c) AB (C D)

d) A B(C D( B C ))

- -

WE JFE JF
E JFW

A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

C
0
1
0
1
0
1
0
1

Y
0
1
0
1
0
1
0
1

WE JF
a) A B C

b) A B B C

c) A AC A B

d) A A A B

WE1 JF
Y A B C A B C A BC ABC

- -

W
W
WW
NORNAND K
K

?Karnaugh-Map? K
KK-mapK-

K
K

KW
W
W
J
Power point J
K
W
K

- -

Introduction

?10??Combinational Logic Circuit?

NAND

NOR

?Karnaugh-Map?
KKmap K

Demorgan's Theorems J

?Bars?KORAND

W
A B A B W
A B A B W

E JFANDORW

ANDNOR

KE JF

K?negative AND?AND
- -

WE JF

0
0
1
1

0
1
0
1

AB
1
0
0
0

A B
1
0
0
0

A B

A B

ANDORWE JF

E JF OR AND W

ORNAND

E JF
K?negative OR?OR

WE JF

0
0
1
1

0
1
0
1

A B
1
1
1
0

A B
1
1
1
0

AB

AB

OR ANDWE JF

K
Y (A B C ) (A B C ) WWE JF

Y (A B C ) ( A B C ) ( A B C ) ( A B C ) A BC A BC ABC A BC
Y ( A B) CD ) W WE JF

Y ( A B) CD ( A B).CD ( A.B)(C D) AB(C D)

- -

(3-1)

W NAND NOR J
Universal Properties of NAND and NOR Gates

AND

NORNANDOR

K?Universal Gates?

:NAND Gate as a Universal Logic Element NAND J J

ANDNAND

NANDNOROR

KNANDEEF JF

KEEF JFNANDAND
EEF JFNANDOR

KEEF JFNOR

AB

AB AB

EF

AB

EF

A
B

A.B A B
B

A
A+B
B

EF

A.B A B
A B

NAND WE JF

- -

A
A B

EF

WNOR Gate as a Universal Logic Element NOR J J

ORANDNORNAND

NOTNORE JFKNAND
KNANDOR

A B

A B A B

A+B

EF

EF

A
A B A.B

AB

EF

A B A.B

A.B
B

AB

NOR WE JF

EF

WNORNAND J
Design of Combinational Logic Circuits using NAND and NOR Gates

NORNAND

NOR?Negative-OR?ORNAND
K?Negative AND?AND

- -

WNAND J J
ORNAND

A B A B

NAND

Negative-OR

KE JF

AB

Y = AB + CD
C
D

CD

NAND
WE JF

Y ( AB )(CD ) W?Y?
Y AB CD W
Y

AB CD W?Bars?

EEF JF?Y?

ORNAND

E JFEEF JF
(NAND-NAND-NAND) (AND-AND-OR)WEEF JF
A

A
B
C
D

Y = AB + CD

Y = AB + CD

EF

AB

CD

EF

E JF AND-AND-OR WE JF
- -

NANDE JF

KOR

AB

ABC

DE

DEF
F
ORWE JF

WE JF?Y?
Y [( AB)C ] [( DE ) F ] [( A B )C ] [( D E ) F ]
( A B )C ( D E ) F
( A B )C ( D E ) F

NAND OR

K?Y?E JF
A

AB

Y ( A B )C ( D E ) F

C
D

( A B )C

DE

(D E )F

ORE JF WE JF

E
F

WNAND WE JF
(a ) Y ABC DE
(b) Y ABC D E

- -

A
B

ABC

KE JF

ABC

Y = ABC + DE

Y = ABC + D + E

EF

D
E

EF

DE

KE JFWE JF

NOR J J
ANDNORNOR

A B A B

Negative-AND

NOR

KE JF
A
B

A B

(A + B) (C + D)

C
D

CD

NOR WE JF

Y A B C D W
Y ( A B) (C D) W
Y ( A B ) (C D ) W

- -

ANDOR(A + B)(C + D)

ANDOR

KANDEEF JFEEF JF

A B

(A + B) (C + D)

C
D

CD

EF

A B

A
B

(A + B) (C + D)

CD

EF

ANDE JF WE JF

NORE JF

W?Y ? KAND

Y [ ( A B ) C ] [( D E ) F ]

[ A B C] [D E F ]
( A B C )( D E F )
A

A B

( A B) C

C
D

DE

E
(D E) F

NOR WE JF

KE JFNORAND
- -

AB

E
F

B C
A

C
D

DE

Y ( A B C ) (D E F)

DE F

E JF
WE JF

Y ABC ( D E ) WNORWE JF

A
B
C
D
E

A B C A B C

KE JF
Y A B C ( D E)

NOR
WE JF
WKarnaugh Map J
K-

K
?Cells??Array?

K
K

- -

Simplification Using Karnaugh Map J

??

? A, B ??A B?E JF

K?00, 01, 10, 11?

AB

AB

AB

AB

AB

AB

AB

AB

WE JF

E JF?Input Labels?

A K
B KA

KB

EEF JFEEF JFEEF JFK AB

K??????

CD

CD

CD

CD

AB
AB

BC

AB

AB

A
4

BC

BC

BC

- -

A
3

KEEF JF

JFOR?1?
KEEF JFEEF

KEEF JFW

A A
B B

AB

AB

EF

EF
B

EF

Y AB AB

EF

A A B B

EF

EF

K WE JF

?1??1?K
?0??0?

??1?K
- -

? AB, A B ?K? AB?? AB

K?0??0?

K A A 1 W?Complements?

EEF JF

EEF JFK
?Adjacent cells?

EEF JF?1?

B B AB, AB

WA

Y A( B B) A 1 A W Y AB AB W
EEF JF

AY
KEEF JF

E JFWE JF
E JFWE JF

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

- -

Y
0
0
1
0
1
1
1
0

WW
Y ABC ABC ABC ABC

?1?W

E JF?1?KE JFY
?0?KE JF?1?

BC

BC

BC

A
A

AB

EF

BC

BC

E JF WE JF

E JF?1?W

EF
BC A, A

K AB C, C
KE JF
A A B B C C

Y AB BC

K WE JF

- -

AND

K
OR

AND

OR

KE JF

??1's

E JFE JFK2

K
1's

K
K1's
CD

CD

CD

CD

AB

AB

AD
ABC

AB

AD

EF

AB

CD

CD

AABB

1
1

AB

AB

AB

EF

Y ABC D ABC D ABCD ABCD

ABC D ABCD ABC D AB
C D
ABCD ABC D ABCD
Y ABC AD AD AB

E
F

BC

CD CD

EF

AC

EF

Y A B C D A B CD A B CD A BC D
A BCD A BCD ABC D ABCD
AB C D AB CD AB CD

EF
Y AC BC D

WE JF

- -

AB
AB

AB
AB

CD

CD

CD

CD

CD

CD

CD

CD

AB

AB

D
0

AB

AB

EEFF

EF

A A B CD
Y A B C D A B C D A B CD

EF

A B C D A BCD AB CD ABCD

EF

BD

CD

AB

EF

A B C D A BC D A BC D A BCD

ABC D ABC D ABCD AB C D

AB C D AB C D AB C D AB CD
Y BD

AB C D AB CD AB CD
Y C D AB BD

WE JF

EF

E JFW J
WE JF

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Y
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
1

- -

Y W

WKE JF?1?
Y ABCD ABCD ABC D ABCD ABCD ABCD

E JFW

KY1's
CD

CD

CD

CD

AB

AB

AD

AB
AB

CD

E JF WE J F

E JFW

1's
C C B B 1's
1'sK AD

K CD A, A, B, B
Y AD CD W

Binary Adder and Subtractor Circuits J

K
- -

WHalf-Adder Circuit J J
E JF

.Carry (C)Sum (S) A, B

WE JF

XOR S

EEF JF .AND C

C, S A, B
K

HA
S

EF

S (Sum)

C (Carry)

EF

WE JF

EEF JF

S ,CHalf AdderHA

S AB A B

(3.2)

C AB

(3.3)

- -

WFull-Adder Circuit J J
2-bits

Carry

Bits

K

Bits

A,B

Input carryECinF

KE JFSum

Carry

WE JF

Cin

00

0+0+0=0

01

0+0+1=1

01

0+1+0=1

10

0 + 1 + 1 = 102 or 210 1

01

1+0+0=1

10

1 + 0 + 1 = 102 or 210 1

10

1 + 1 + 0 = 102 or 210 1

11

1 + 1 + 1 = 112 or 310 1

A, B, Cin

C , S K 2 3 8
K

W S , C

S ABCin ABC in ABC in ABCin

(3.4)

C ABCin ABCin ABC in ABCin

(3.5)

- -

WS

S A BCin ABC in A BC in ABCin ( AB A B )C in ( AB AB )Cin (3.6)

XNOR AB AB XOR AB A B

S ( A B)C in ( A B)Cin

(3.7)

Cin ( A B ) XOR

WS

S ( A B ) Cin A B Cin

(3.8)

A, B XOR S

K Cin

W C
C ABCin ABCin ABC in ABCin ( AB AB)Cin AB(C in Cin )
C ( A B )Cin AB

(3.9)
(3.10)

EEF JFCS

FAEEF JF

K?Full Adder?

FA

Cin

S (Sum)

C (Carry)

Cin

EF

EF
K WE JF

- -

EEF JF

OR2OR
KE JF

Cin

HA
S

HA
B

K WE JF

WHalf Subtractor Circuit J J

Bit

KDifference

Borrowed?1?

?D??2-bits?

K?1?? B0 ?
?1?
K

?E JF

W B0 DK?
- -

D AB AB

&

Bo AB

(3.11)

WE JF

B0

SD

AC B0 XOR

K B A AND

EEF JFEEF JF

KHalf SubtractorHS
A

B
A

HS
D

D (Difference)

B0 (Borrow)

B0

EF

EF

WE JF

WFull Subtractor Circuit J J

1 2-bits

KK

DK Bi n BA

E JF B0
- -

K A B Bin K

K Bin 0
W Bin 1

K D 2 0 1 1 A 0 2 2 B0 1 1 A 0, B 0

K D 2 1 1 0 A 0 2 2 B0 1 1 A 0, B 1

K D 1 0 1 0 A 1 B0 0 A 1, B 0
K D 3 1 1 1 A 1 2 3 B0 1 1 A 1, B 1
KWE JF

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

Bin
0
1
0
1
0
1
0
1

D
0
1
1
0
1
0
0
1

B0
0
1
1
1
0
0
0
1

W
D ABBin AB Bin AB Bin ABBin

(3-12)

E JFFS

W
(3-13)

D ( A B ) Bin A B Bin

WB0
Bo A BBin AB B in ABBin ABBin Bin ( A B AB ) AB( B in Bin )

(3-14)

Bo Bin ( A B ) AB

(3-15)

- -

EEF JFB0D

Full SubtractorFSEEF JF

EEF JFK
KE JFOR
A

B Bin
A
B

FS

B0

Bin

B0

EF

EF

KWE JF

Bin

HS

HS
B

B0

B0

B0

WE JF

- -

WE JF
a) AB(C D)
c) ( A B C D) ABC D

b) AB (CD EF )
d) ( A B C D )( A BC D )

WNAND E JF
a) ABCD DE
c) ABC D E

b) ABC AB D
d) ABC ABC ABC ABC

WNOR E JF
a) ( A B C )( A B )

b) ABC ( D E )

c) ( AB C )( D E F )

d) ( A B )(C D )

WE JF
WE JF

W E JF
a)
b)
c)
d)

ABCD ABC D ABC D ABCD ABCD ABC D

ABC D ABCD ABCD ABCD ABC D ABC D ABC D
ABCD ABC D ABC D ABCD ABCD
ABC D ABCD ABC D ABCD ABCD ABC D ABCD ABCD

- -

(1 or 0)E JFE JF
W

a) A = 1, B = 1, Cin = 1
c) A = 0, B = 1, Cin = 0

b) A = 0, B = 1, Cin = 1
d) A = 1, B = 1, Cin = 0

WE JF
a) S = 0, Cout = 0
c) S = 1, Cout = 1

b) S = 1, Cout = 0
d) S = 0, Cout = 1

(1 or 0)E JFE JF
W

a) A = 1, B = 1, Bin = 1
c) A = 1, B = 1, Bin = 0

b) A = 1, B = 0, Bin = 1
d) A = 0, B = 1, Bin = 1

- -

W
W
WW
K K
K K

K K
KEF K
KW
W
W
K J
Power point J
K
W
K

- -

Introduction

?Combinational Logic Circuits?

?Sequential Logic Circuits?

?Memory?

?Flip-Flop Circuit?

K?1??0?

K?1??0?

NORNAND?Bi-stable Multi-vibrator?
K?Digital Integrated Circuits?
K?Shift Registers??Counters?

WFlip-Flop's J
WLatches J J

- -

KBistable Multi-vibrator?Latch?

SRE JF

R?1??Set Input?S

?0??Reset Input?
K Q Q
SET
Inpu
RESET
Input

Q output

Q output

SRWE JF

Q 0 , Q 1 Set

K Q 1 Q 0 Reset
EF Q 1?1?S

K Q 0 Q

EF Q 0 Q 1 ?1?R

?1?S, R
K?Unpredictable?

NORSR

KE JF

SR WE JF
- -

F?1?NOR

.?Active High Inputs?E JF

SRWE JF

Q0

EF

(Mode of Operation)
No Change

Latch RESETS
Latch SETS
Invalid condition

W
S ,R?0? -

K Q o EF

F Q 0 ?1??0?R -
K Q 0 E

EF Q 1?1??0?S -
K Q 1

S, R?1? -
KNOR

- -

E JFNAND

E JF?0?NAND
K?Active Low Inputs?
S

SR WE JF

SRWE JF

R
0

Qo

EF

(Mode of Operation)

Invalid condition
Latch SETS
Latch RESETS
No Change

W
?0? K
KEFNAND

?1? R 1 S 0 K
K Q 1

?0? R 0 S 1 K
K Q 0

?1? K
KEF Q0

- -

?Logic Symbol?E JF

LOWEFHIGHEF

WE JF

S 0, R 0 K Q S, R

KE JF S , R W J

K Qo 0 Q

S

KWE JF

WClocked S-R FlipFlop SR J J

Q SR SR

K
- -

EF

SR
K

KCK?Clock Pulse?

SRE JF

KCK

CK
R

Q
CK

Q
R F
Q
EFE

EF
EF

SRWE JF

EEF JF

?Positive Edge Trigger?SR

EEF JF?1??0?

K?0??1??Negative Edge Trigger?

NANDSRE JF

KNAND

QS ,R

CK

SRWE JF
- -

SRWE JF

CK

Q
Qo

(Mode of Operation)

EF
No Change

Latch RESETS

Latch SETS

Invalid condition

WSRE JF
?0?S, RCK K
K

?1??0? S 0, R 1R K
.Reset?0?

?1??0? S 1, R 0 S K
.SetQ = 1

S 1, R 1 K
K

?1?)SR

(?0?

E JFSR QW J

KE JFS, R, CK
K Q 0

K Q 0 Q S 0, R 0 W -

K(Reset) Q 0 S 0, R 1W -
- -

K(Set) Q 1 ?1?Q S 1, R 0 W -
.(Reset) Q 0 S 0, R 1W -

K(Set) Q 1 S 1, R 0 W -

K Q 1 ?1? S 1, R 0 W -
CK

SR
WE JF

WD-Type Flip-Flop?D? J J
?Single Bit?D

SRK?10?

KE JFD

Q
CK

WE JF
D
DD

R 0 S 1?1?DKCK

DK (Set)?1?CK

CK R 1 S 0 ?0?

K(Reset)?0?
- -

?Reset??1??Set?

DK?0?

KE JF?Positive Edge Trigger?

D WE JF

CK

(Mode of Operation)

(SET) (stores 1)

(RESET) stores 0)

KDQ

DEEF JF

K?Delayed time Filp-flop?CK

KEEF JFNANDD

S
Q

CK

EF

CK

E F

NANDDWE JF

DQW J

KE JFDE JF
K Q 0

- -

?1? ?0? D Q

CK

DE JF

WClocked JK Flip FlopJK J J

KJ, KK JK
SR JK

JK.(Reset)(Set)

KSR

K JKE JF

SR
K?1?J, K

J

CK

JKEF

JK EF

WE JF
KJK
- -

CK

SRE JF

K Q Q

JKE JF

?0?J, K

J 0, K 1 ?0?(Reset)

J 1, K 0 JK(Set)

?Toggle?JKK

Q?1?J, K
KCK

JKWE JF

(Mode of Operation)

Q0

EF

No Change

(RESET)

(SET)

Toggle

CK

E JFJKQW J

KE JF CKJK
KQ = 0

CK

KJK
WE JF
- -

?1?J, K -
K?1?Q

K J K 0 -

K Q 0 Reset J 0, K 1 -
K Q 1 Set J 1, K 0 -

QJ, KSet -
K?1?

WT-Type Flip-Flop ?T? J J

JKT

TE JFJ,K
(Toggle)TKT

CK?1?T

CK

KE JFCK
KTE JF

J
CK

TWE JF
TWE JF

CK

Q0

Q0

(Mode of Operation)

EF

No Change

- -

Toggle

TTQW J

K Q 0 E JFCK

CK

TWE JF

T=1Q

K?1??0?Q T 1Q T 0
:Shift Registers J

?Bit?

?Left Shift??Buffer Register?

?Parallel Data??Serial Data??Right Shift?

K?Shift Registers?

WBuffer Registers J J
?Digital word?

EEF JFK?Bits?
?4-stages? D

K?Positive edge-triggered?

- -

?4-bit word to be stored?

D1

D2

Q
CLR

CLR

CLR

CK

CLR

D4

D3

CLR
Q1

Q2

Q3

?Parallel data outputs?

D
EF

Clock
D1

Input data

D2
D3
D4
Q1

Output data

Q2
Q3
Q4

1
0
1
0

EF


W JF
- -

Q4

?4-bits?

Q1,Q2, Q3,Q4D1,D2,D3,D4

KEEF JFCK

?Clear-input?K?Parallel-in, Parallel-out Registers?

K?Active-low?
Shift Registers J J

?Shift??move?

WE JF

KSerial-in, Serial-out Shift Registers?SISO? .

.Serial-in, Parallel-out Shift Registers ?SIPO? .

KParallel-in, Serial-out Shift Registers ?PISO? K

Serial-in, serial-out "SISO" Shift Registers

Shift Right
Serial-In

Shift Left
Serial-Out

Rotate Right

Serial-In

Serial-Out

Rotate Left

E F

Serial-in, parallel-out "SIPO" Shift Registers

Serial-In

Parallel-in, Serial-out "PISO" Shift Registers

Parallel Data In

Parallel Data Out

EF

WE JF
- -

Serial-Out

?SISO?- J J J
KE JF

1001EF0110
K

WE JF

Q0

Q1

Q2

Q3

1st

2nd

3rd

4th

Clock

Input

1st Clock pulse

2nd Clock pulseK

K?1001??0110?

K
?0110?

K?1001?

4-bitsEEF JF

FF0DKD

Q1FF1DQ0

- -

Q2FF2
K Q3 FF3

Serial
Data
Input

FF1

FF0

Q0

Q1

CK

CK

FF2

FF3

Q2

CK

Q3

Serial
Data Out

CK

Clock
Input

SISO Shift
Right

EF

Serial
Data Out
Q3

CK

Clock
Input

FF3

Q2

CK

FF2

Q1

CK

FF1

Serial
Data
Input

Q0

CK

FF0

Shift
Left
SISO
EF



SISO Rotate Left
EF

WE JF

SISO Rotate Right

?Clock input?

1-bit?Positive edge?

DEEF JF

.?SISO Shift-Right Shift Register?

- -

EEF JF

K?SISO Shift-Left Shift Register?D

EEF JFEEF JF

EEF JF

?SISO Rotate-Right?

K?SISO Rotate-Left?

W- J J J
Serial-in, Parallel out Shift Registers ?SIPO?

E JF

4-bits

F?Serial data input?

KE

Serial
Data
Input

FF1

FF0
D

Q0

CK

FF2
Q1

Q2

CK

CK

FF3
Q3

CK

Clock
Input

Q0

Q1

Q2

Q3

- -

Parallel data outputs

J WE JF

?4-bits?

K
K?4-bits?Q3,Q2,Q1,Q0

W- J J J
Parallel-in, Serial-out Shift Registers ?PISO?

E JF

KD

Low SHIFT / LOAD K SHIFT / LOAD

?Enabled?AAND

K?Inverter?
Clock ?KD3,D2,D1,D0

.Q3,Q2,Q1,Q0?pulse

( SHIFT / LOAD ) control

(1 for shift , 0 for load )

Parallel data inputs

D0

D1

D2

D3

FF0
D

CK

FF2

FF1
Q0

Q1

FF3
Q2

CK

CK

Clock
Input

Serial
Out

Q3

CK

K J WE JF
- -

ANDHigh SHIFT / LOAD

DQ0KEnabledB

FF2Q1FF1

KFF3Q2

?1-bit?
.?Clock input?

WCounters J
K

?Binary bits?

?Clock input?

K?Synchronous Counters? ?Asynchronous Counters?

K
WAsynchronous Binary-Up Counters J J
EEF JF

KJK

HighJ, K

K?Negative edge??Toggle?
Q
KEEF JF

- -

?4-bit word?Q3,Q2,Q1,Q0

0000

FF0KE JF
KQ3MSBFF3Q0LSB

FF0

Clock
Input

FF1
Q0

Q1

CK
CK (

FF2

Q2

CK

FF3

CK

CK
K

Q3

Q1

Q0

Q2

Q3

E F

10 11

12

13

14

15 16

17

Q0

Q1

Q2

Q3

EF

WE JF
- -

?Clock input?FF0

?Toggle?Q0

Q0EEF JFQ0
Q0 K?0? ?1? ?1? ?0?
Q0 FF1

Q2 Q1 K?Toggle? Q1
KQ3Q2

WE JF

Q3

Q2

Q1

Q0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
2
3
4
5
6
7
8
9
10
11
12
13
13
15

Cycle Repeats

Binary Count

WMaximum Count of a Counter N

E JF

00100001
KKKK0011
- -

WMaximum count before cycle repeats

(4-1)
K?Number of flip-flops in the counter circuit? nW
N 2n 1

WEEF JF

N 2 n 1 2 4 1 16 1 (15 )10 (1111) 2

(4-2)

WModulus of Counter MOD

MOD?Modulus of counter?

16MODEEF JFK
KE JF11110000 16
MOD = 2

WMOD
(4-3)

WAsynchronous Binary-Down Counters J J

K?1?

EEF JFK?1?
Q KJK

K Q

KEEF JF Q

Q3,Q2,Q1,Q0RESET

Q Low Q K0000
FF3,FF2,FF1,FF0K1111

HighJ ,KKHigh

K?Toggle?

?1??0?Q0FF0
FF1?0??1? Q 0
Q1 ?1??0?Q1
- -

KKKKFF2 Q 1 K?0??1?
Q0

Q1

Q2

Q3

HIGH

FF1

FF0
Q0

Clock
Input

Q1

CK
Q0
1

EF
9

10 11

Q3

CK
Q1

Q2

CK

FF3

FF2

CK
Q2

12 13 14 15 16

Q3

Q0

EF

Q1

Q2

Q3

WE JF

Q2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0

Q3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

17

Clock
Input

Q1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0

Q0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

15
13
13
12
11
10
9
8
7
6
5
4
3
2
1
0

Binary Count
- -

WE JF

Cycle Repeats

(15)10 = 1111Q3,Q2,Q1,Q0

KE JF

K
FF0EEF JF

Q3,Q2,Q1Q0

K
WL J J
Asynchronous Binary Up/Down Counters

K Q

LE JF

K UP / DOWN AND-OR

Q0

Q2

Q1

HIGH

FF0
Q0

Clock
Input

CK
K

Q1

Q2

FF3

Q1

Q3

CK

CK

CK
Q0

FF2

FF1

Q3

Q2

Q3

UP/DOWN
Control

WE JF

ANDHigh UP / DOWN

QEnabledA

UP / DOWN K

?Disabled?Low
- -

Q ?Enabled? B

WSynchronous Binary Counters J J

ANDJKE JF

MOD-16 4-bit

??
K?Trigger?

K
Q0

Q1

HIGH

FF0
Q0

CK
Clock
Input

FF1
Q1

CK
K

Q3

Q2

FF2
Q2

Q3

CK
K

FF3

CK
K

K WE JF

FF0J, K

?Toggle?High

Low
KLowHighHigh

2FF1J, K

Q1LowQ0KFF0
Q1HighQ0?No change?FF1

K?Toggle?

- -

AND-AFF2J, K

High AND-A Q0 Q1 HighKQ0 ,Q1

KFF2?Enable?

AND-BFF3J, K

AND-BHighQ2,Q1,Q0KQ2,Q1,Q0

KFF3High

WSynchronous Counters Advantages

Ripple Counters

E JF
KE JFEF

Propagation-delay time

EF

tp = tp (Single flip-flop) + tp (Single AND-gate)

- -

WMultiplexers or Data Selectors J

E JF K

So
S1

0
1

Do
D1

0 Mux
1
2

D2
D3

WE JF

S E JF

S1 0, S 0 0 ?0?

D0

D1 S1 0, S 0 1 ?1?

D2 S1 1, S 0 0 ?2?

KE JFD3 S1 0, S 0 0 ?3?
WE JF

S0

S1

D0

0
1
1

1
0
1

D1
D2
D3

Y D0 S1 S 0
Y D1S1S0

Y D1S1 S 0

Y D1S1S0

Y D0 S1S 0 D1S1S0 D2S1S 0 D3S1S0 W

- -

AND

KE JFS1, S0OR
S0

S1

D0

D1

D2

D3

WE JF

D0

W J

D1
D2

E JF

D3
S0

S1

KE JF

Y
D0

D1

D2

D3

D0

D1

D2

WE JF

D3

KY

WDemultiplexers J

K?Data subscriber?
- -

E JF

KAND

K
Data
Input

D0

D1

Data
Output
Lines

S0
Select
Lines

D2

S1

D3

WE JF

?Data in?E JFW J

KE JFD3, D2, D1, D0KS0S1

KE JFD3, D2, D1, D0

S0

S1
D0
D1
D2
D3

0
1

0
0

1
1

WE JF
- -

SRQE JF

?Negative edge trigger?

Q 0 KE JF

CK
S
R
E JFWE JF

DQE JF

?Positive edge trigger?

Q 0 KE JF

CK
D

E JFWE JF

JKQE JF

KE JFNegative edge trigger

K Q 0
- -

CK

E JFWE JF

TQE JF

?Negative edge trigger?

Q 0 KE JF

CK

E JFWE JF

S1=0, S0=1, D3=0, D2=1, D1=0, E JFE JF

KD0=1

- -

W
KW
WW
K K
K K
K K

K K
KW
W
W
K J

Power point J
K
W
K

--

Introduction

W J
WDevelopment of Computers J J

K Boole OR NOTAND

K William Javors

Herman Hollerith
1890

Hollerith K

International Business Machines IBM

K Otto Steigeas

AudionVacuum tube Lee De forest

K

Flip Flop Ecdes and Jorda

K

Analogue

K
--

Ecker
K

K Logic Machine

K Shannon
ABC Digital
KAnat soff , Berry and Cony

K Z-3 Digital

50Mark-1
K

Bug Mark-11

KENIAC

K
K

K Core Memory

Whirl Wind Computer

UNIVAC

Wilkes K
KMicroprogramming

KTRAPIC

RAMac
K

KFORTRAN

--

Lisp
K

Cobol
K K

IBM
K

K BASIC

K
KINTEL

RISC IBM
K

AT IBM
IBM

K Apple

Software

KHardware

--

WBasic Construction of a Computer J J

W

Input and Output ??Memory??Central Proccessing Unit CPU?

?Data Bus??Devices

K?Control Bus??Address Bus?

KE JF
W

WE JF

WMotherboard J

?Motherboard?

E JF
?Clock??Logic Gates??Multiplexers?

K?Power Supply?

?Motherboard? WE JF
--

WL J
K

WInput Interface J J

K
Parallel TransmissionW

D7D6D5D4D3D2D1D0

Do
D1
D2
D3
D4
D5
D6
D7

WE JF

WSeries TransmissionW

KE JF

--

D0 D1 ----D7
D7 D6 ----D0

WE J F

WOutput interface J J

KKKWL

KKKW

KKKW
KKKW

WL J J
?Handshaking?

WE JF
--

WK

?Data Available?

W?Data Acknowledge?

KL

KK

W J
W J J
K10

KE JF?Word?

1 K byte = 210 = 1024 bytes

(5-1)

E10F

EF

W( J )

Kn2n

16

12

10

8W
WE JF

21621221028W

26Kbyte22 Kbyte1Kbyte256 byteW

--

W J J
Random Access Memory RAM W
K

KTemporary

: Read Only Memory ROM W

PROM & EPROM W
K

K
WBinary Decoder J J

1
2

0
0
1
1

0
1
0
1

0
0
0
1

0
0
1
0

0
1
0
0

1
0
0
0

WE JF

E 2EF=FWE JF

?21?E JF
--

?4321??A14A15?

A15
A14

1
2

KE JF

CS

CS

CS

CS

WE JF

W J J
WELF
KERD: ReadF

KEWR: WriteF

K(CS: Chip Select)

W
K K
EFK K
K

K K
W J J

K
K?Memory Access Controllers?
K

--

WMicroproccessor J

E JF

WE JF

W

K

W J J
Central Processing Unit?CPU?

KEE JFFWControl Unit?CU?

--

.W( J)

WRead Only Memory?ROM? K

KK

WRandom Access Memory?RAM? K

K

WInput unit K
K

WOutput unit K
K

WBus Types J J
Bus

E1 0F 5v 0v
WE JF

WData Bus

K
K8BitD7 D6D5D4D3D2D1D064,32,16,8Bits
--

KWAddress Bus
EF
A15...A2A1A0.

K16

WControl Bus
K

ROM

RAM

W( J)

KWE JFWE JF
--

1111 0101 0000 1100

0
1
1
0
1
0
1
1

D7 D0

1111 0101 0000 1100

11010110

WE JF

EWRFERDF
K

ROM RAM

MEMR

RAM

MEMW

IOR

IOW

W J J
?Word???

K64,32,16,8Bits

WByte ??8
K?Binary Coded Decimal?

K?Hexadecimal?

--

K
WIntel 8085 Proccessor J J

KIntel 8085E JF

WEF

Intel 8085W( J)
--

K K

K K
K K

W J J

KE JFFK

Z A

CY(Carry)

P(Parity)

AC(Auxiliary Carry)

Z(Zero) S(Sign)

WE JF

KE5,31F10
W J J
KA1W
05B 04WE JF

7E JFK-01EA-BF
K1EF

1W
K0

--

1W
K

02B0EWE JF

EA+BF

00001110

H 00000010B
Z00010000
KD3D4
F1W
KE

A1W
EFFF
10 B FF WE JF

W(A)+(B)

KE5,31F10
11111111

H10000000B

Z01111111

K1

--

WE JF
0111E A01FB ABCDE 9812F 7FE3D 54F 69F A3F EFC

E JF
WXE JF
KEFRAM/ROM

KEFRAM/ROM

E JF

WE JF

WE JF
K J

K J
K J

K J

K J

K J
K J

W
K JK J

K JK J
K JK J

K JK J

--

E JF
E JF E JF

IOR

MEMR

MEMW

WE JF

KE JF
LE JF
E JF
E JF
WE JF


K

E JF

--

[1] Nigel P. Cook, Introductory Digital Electronics. New Jersey: Prentice-Hall, Inc. 1998.
[2] M. Morris Mano, Digital Logic and Computer Design, Prentice- Hall, Inc. of India
2000.
[3] Thomas L. Floyd, Digital Fundamentals, Seventh Edition, Prentice-Hall, Inc. 2000.
[4] M. Morris Mano, Digital Design, Prentice- Hall, Inc. Aug 2001.

- -

K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K
J J K K K K K K K K K K K K K K K K K K K K K KNumbers SystemsW
J J K K K K K K K K K K K K K K K K K K K K K K K K K K K K Introduction
J J K K K K K K K K K K K K K K K K K K K K K K K Numbers Systems J
J J K K K K K K K K K K K K K K K KDecimal Numbering Systems J
J J K K K K K K K K K K K K K K K K Binary Numbering System J
J J K K K K K K K K K K K K Hexadecimal Numbering System J
J J K K K K K KArithmatic Operations in Binary System J
J J K K K K K K K K K K K K K K K K K K K K K K K K K K K
J J K K K K K K K K K K K K K K K Simple Logic Circuits W
J J K K K K K K K K K K K K K K K K K K K K K K K K K K K K Introduction
J J K K K K K K K K K K K K K K K K K K K K K K K K Logic Gates J
J J K K K K K K K K K K K K K K K K K Rules of Boolean Algebra J
J J Implementaion of Logic Circuit via Truth Table J
J J

Converting Booleen Expression to Truth Table J

J J K K Simplification of Boolean Expression J

J J K K K K K K K K K K K K K K K K K K K K K K
J J K K K K K K K K K K K K Combinational Logic Circuits W
J J K K K K K K K K K K K K K K K K K K K K K K K K K K K K Introduction
J J K K K K K K K K K K K K K K K K K K K Demorgan's Theorems J
J J K K K K K K K Universal Properties of NAND and NOR Gates J
J J K K K K K K K K K K K K KNORNAND J
J J K K K K K K K K K K K K K K K K K K K K K K K K Karnaugh Map J
J J K K K K K K K K KSimplification Using Karnaugh Map J
J J K K K K K K K K Binary Adder and Subtractor Circuits J
J J K K K K K K K K K K K K K K K K K K K K K K K K K K

- -

J J K K K K K K K K K K K K K K Sequetial Logic Circuits W

J J K K K K K K K K K K K K K K K K K K K K K K K K K K K K Introduction
J J K K K K K K K K K K K K K K K K K K K K K K K K K K K KFlip-Flop's J
J J K K K K K K K K K K K K K K K K K K K K K K K K Shift Registers J
J J K K K K K K K K K K K K K K K K K K K K K K K K K K K K Counters J
J J

Multiplexers or Data Selectors J

J J K K K K K K K K K K K K K K K K K K K K K K K Demultiplexers J
J J K K K K K K K K K K K K K K K K K K K K K K K K K K
J J K K K K K K K K K K K KIntroduction to Microcomputer W
J J K K K K K K K K K K K K K K K K K K K K K K K K K K K Introduction
J J K K K K K K K K K K Basic Fundamentals of Computers J
J J K K K K K K K K K K K K K K K K K K K K K K K K K KMotherboard J
J J K K K K K K K K K K K K K K K K K Input / Output UnitsL J
J J K K K K K K K K K K K K K K K K K K K K K K K K K K K K K Memory J
J J K K K K K K K K K K K K K K K K K K K K K K K K Microprocessor J
J J K K K K K K K K K K K K K K K K K K K K K K K K K K
J J K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K Referances

- -

English

1's Complement

st

1 Clock pulse

2's Complement

4-stages
Active High Inputs

Active Low Inputs

Active-low

Addition of Binary Numbers

Address Bus

Adjacent cells
Advantages

Analogue

Arithmetic Operations

Array

Asynchronous Binary Up/Down Counters

Asynchronous Binary-Down Counters

Asynchronous Binary-Up Counters

Asynchronous Counters

Auxiliary Carry AC

Bars

Basic Construction of a Computer

Binary Adder and Subtractor Circuits

Binary bits

Binary Coded Decimal

Binary Decoder

Binary Digits

Binary Numbering System

Binary Point

Binary Subtraction

Binary Variables

Binary-to-Decimal Conversion

Binary-to-Hexadecimal Conversion

--

English

Bi-stable Multi-vibrator

Bits

Block Diagram

Boolean Algebra

Boolean Expression

Borrowed

Buffer Register

Bus Types
Carry

Cells

Central Processing Unit CPU

Central Processors
Clear-input

Clock Pulse

SR

Clocked SR Flip-Flop

Closed

Combinational Logic Circuit

Complementation

Complements

Control Bus

Control Unit CU

Converting

Core Memory

Counters
CS: Chip Select

CY(Carry)

Cycle Repeats

Data Acknowledge

Data Available
Data Bus

Data subscriber

Decimal Fractions

Decimal Numbering System

Decimal Point

Decimal-to-Binary Conversion

--

English

DecimaltoHexadecimal Conversion

Delayed time Filp-flop

Demorgan's Theorem

De-multiplexers

Design of Combinational Logic Circuits

Developments of Computer

Difference bit

Digital
Digital Electronic Circuits

Digital Integrated Circuits

Digital word

Disabled
Discard

Enabled

Flip Flop

Flip-Flop Circuit
Full Subtractor Circuit

Full-Adder Circuit

Gate
Half Subtractor Circuit

Half-Adder Circuit

Handshaking

Hardware

Hexadecimal Numbering System

Hexadecimal-to-Binary Conversion

HexadecimaltoDecimal Conversion

HIGH
Implementation

Input and Output Devices

Input Interface

Input Labels

Input unit

INTEL

Invalid condition

Inversion

--

English

INVERTER

JK Flip Flop

JK

Karnaugh-Map

Latches

Least Significant Bit

Left Shift

Logic Circuit

Logic Functions

Logic Machine
Logic Symbol

Logical Addition

Logical Multiplication

LOW

Magnitude

Maximum Count of a Counter

Memory

Memory Access Controllers

Microprogramming

Mode of Operation

Most Significant Bit

Motherboard

Multiplexers or Data Selectors

NAND

NAND Gate as a Universal Logic Element

Negative Edge Trigger

EF

No Change

NOR

NOR Gate as a Universal Logic Element

NOT Gate

Number of Binary Combinations

Numbering Systems

Output interface

Output unit

P(Parity)

Parallel Data
Parallel Data In

Parallel Data Out

--

English

Parallel Transmission

Parallel-in, Serial-out Shift Registers

Positional Weight

Positive edge

Positive Edge Trigger

Power Supply

PROM & EPROM

Propagation-delay time

Pulses

Random Access Memory RAM

RD: Read

Read Only Memory ROM

Repeated Division-by-2 Method

Representation of Signed Numbers

Reset

Reset Input

RESETS

Right Shift

Ripple Counters
Rotate Left

Rotate Right

Rules of Boolean Algebra

S(Sign)

Sequential Logic Circuits

Serial Data

Serial-In
Serial-in, Parallel-out Shift Registers

Serial-in, Serial-out Shift Registers

Serial-Out

Series Transmission

Set Input

SETS

Shift Registers

Sign

Signed Numbers

--

English

Sign-Magnitude

Sign-Magnitude System

Simplification

Simplification of Boolean Expressions

Simplification Using Karnaugh Map

Single Bit

SISO Rotate-Right
Software

Standard

stores

Sum

Synchronous Binary Counters

Synchronous Counters

Temporary

Timing Diagram
Toggle

Trigger

Truth Table

Universal Gates

Universal Properties
Unpredictable

Vacuum Tube

via

Voltage Source

Whirl Wind Computer

WR: Write

Z(Zero)

Parallel Data Output

Modulus of Counter MOD

--