Low Power MAC Unit for DSP Processor

AIM: The main aim of the project is to design Low Power MAC Unit for DSP Processor. (ABSTRACT) Power dissipation is one of the most important design objectives in integrated circuit, after speed. Digital signal processing (DSP circuits whose main building bloc! is a "ultiplier#$ccumulator ("$% unit. &igh speed and low power "$% unit is desirable for an' DSP processor. This is because speed and throughput rate are alwa's the concerns of DSP s'stem. This paper e(plores the design of low power "$% unit with bloc! enable techni)ue to reduce power dissipation. The "$% unit is implemented using *+,#nm %"-S process technolog'. The whole "$% chip is operated at .,, "&/ with*.01 suppl' voltage. The result anal'sis shows that the power consumption is reduced b' using bloc! enable techni)ue. Proposed Method: 2n this paper we have the "$% unit with . operands . we are going to propose this "$% unit architecture with + operands. $dvantage is we can do + multiple operations at a time. $nd we can increase the bit si/e .

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

Advanta e: This "$% unit has *3 bit output and its operation is to add repeatedl' the multiplication results. The improvement of power#dela' product of the "$% unit can be used in high speed DSP application..

BL!C" DIA#RAM:

T!!LS4 (lin( 5..i ise, model sim 6.7c

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

R$%$R$&C$: 8*9S. :. :ou, %. ;. %hen, <. %. ;ang and %.%.Su, $ pipeline "ultiplier# $ccumulator using a high speed, low power static and d'namic full adder design, 2<<< custom 2ntegrated circuit conference, *550, pp. 05+#056 8.9 =est and &arris, %"-S 1>S2 Design4 a circuits and s'stems perspective, $ddison#=esle' Publishing %ompan',+rded. 8+9 Design and 1>S2 2mplementation of Pipelined "ultipl' $ccumulate ?nit4 Shanthala S, %'ril Prasanna @aj, Dr. S.;.Aul!arni. 879 T.&.&arun, &igh Speed 3#bits B 3#bits =allace Tree "ultiplier, %hapter +, "a' .,,C. 809 D. >u and &. Samulei, $ .,,#"&E %"-S pipeline "$% using a )uasi# domino d'namic full adder cell design, 2<<< :. Solid state circuits, vol..3, pp. *.+#*+., Deb *55+

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &