A New VLSI Architecture of Parallel MultiplierAccumulator Based on Radix- Modified Booth Al!

orithm AIM The main aim of the project is to design A New VLSI Architecture of Parallel MultiplierAccumulator Based on Radix- Modified Booth Al!orithm. (ABSTRACT) In this paper, we proposed a new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and de ising a hybrid type of carry sa e adder (C!A), the performance was impro ed. !ince the accumulator that has the largest delay in MAC was merged into C!A, the o erall performance was ele ated. "he proposed C!A tree uses #$s-complement-based radi%-& modified Booth$s algorithm (MBA) and has the modified array for the sign e%tension in order to increase the bit density of the operands. "he C!A propagates the carries to the least significant bits of the partial products and generates the least significant bits in ad ance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimi'e the pipeline scheme to impro e the performance. "he proposed architecture was synthesi'ed with &(), #*) and #+) m, and ,) nm standard CM-! library. Based on
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the theoretical and e%perimental estimation, we analy'ed the results such as the amount of hardware resources, delay, and pipelining scheme. 4e used !a/urai$s alpha power law for the delay modeling. "he proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the pre ious research in the similar cloc/ fre5uency. 4e e%pect that the proposed MAC can be adapted to arious fields re5uiring high performance such as the signal processing areas. Proposed Method: In this architecture a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic is proposed. By combining multiplication with accumulation and de ising a hybrid type of carry sa e adder (C!A), the performance was impro ed. !ince the accumulator that has the largest delay in MAC was merged into C!A, the o erall performance was ele ated. Advantage: Following the approach, the proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the pre ious research in the similar cloc/ fre5uency.

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 4e e%pect that the proposed MAC can be adapted to arious fields re5uiring processing areas. BLOCK DIAGRAM: high performance such as the signal

Fig.1 hardware architecture of MAC

Fig.

hardware architecture of proposed MAC

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Fig. ! proposed architecture of C"A tree

TOOLS# $I%%I&$ I"' (. , M)*'% "IM +.,c RE ERE!CE: -1. /. /. F. Ca0anagh, *igital Computer Arithmetic. &ew 1or2# Mc3raw4 5ill, 1(6,. - . Information Technolog74Coding of Mo0ing 8icture and Associated Autio, M8'34 *raft International "tandard, I")9I'C 1!61641, , !, 1((,.
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-!. /8'3 ::: 8art I Fina111(l *raft, I")9I'C /TC19"C ( ;31. -,. ). %. Mac"orle7, 5igh speed arithmetic in <inar7 computers, 8roc. I=', 0ol. ,(, pp. +>?(1, /an. 1(+1. -@. ". ;aser and M. /. Fl7nn, Introduction to Arithmetic for *igital "7stems *esigners. &ew 1or2# 5olt, =inehart and ;inston, 1(6 .

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