BJT Amplier Circuits

As we have developed dierent models for DC signals (simple large-signal model) and AC signals (small-signal model), analysis of BJT circuits follows these steps: DC biasing analysis: Assume all capacitors are open circuit. Analyze the transistor circuit using the simple large signal mode as described in pages 77-78. AC analysis: 1) Kill all DC sources 2) Assume coupling capacitors are short circuit. The eect of these capacitors is to set a lower cut-o frequency for the circuit. This is analyzed in the last step. 3) Inspect the circuit. If you identify the circuit as a prototype circuit, you can directly use the formulas for that circuit. Otherwise go to step 4. 4) Replace the BJT with its small signal model. 5) Solve for voltage and current transfer functions and input and output impedances (nodevoltage method is the best). 6) Compute the cut-o frequency of the amplier circuit. Several standard BJT amplier congurations are discussed below and are analyzed. For completeness, circuits include standard bias resistors R1 and R2 . For bias congurations that do not utilize these resistors (e.g., current mirror), simply set RB = R1 R2 . Common Collector Amplier (Emitter Follower) DC analysis: With the capacitors open circuit, this circuit is the same as our good biasing circuit of page 110 with RC = 0. The bias point currents and voltages can be found using procedure of pages 110-112. AC analysis: To start the analysis, we kill all DC sources:
VCC = 0 R1 vi Cc vo R2 RE R1 R2 vi Cc B E RE C vo

VCC R1 vi Cc vo R2 RE

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We can combine R1 and R2 into RB (same resistance that we encountered in the biasing analysis) and replace the BJT with its small signal model:
vi Cc

B
+ v
BE

i i
B

vi

Cc

B
i
B

E
RE i
B

vo

ro vo

RB

RB

ro

RE

The gure above shows why this is a common collector conguration: collector is shared between input and output AC signals. We can now proceed with the analysis. Node voltage method is usually the best approach to solve these circuits. For example, the above circuit will have only one node equation for node at point E with a voltage vo : vo v i vo 0 vo 0 + iB + =0 r ro RE Because of the controlled source, we need to write an auxiliary equation relating the control current (iB ) to node voltages: iB = vi v o r

Substituting the expression for iB in our node equation, multiplying both sides by r , and collecting terms, we get: vi (1 + ) = vo 1 + + r 1 1 + ro RE = vo 1 + + r ro R E

Amplier Gain can now be directly calculated: Av vo = vi 1+ r (1 + )(ro 1

RE )

Unless RE is very small (tens of ), the fraction in the denominator is quite small compared to 1 and Av 1. To nd the input impedance, we calculate ii by KCL: ii = i1 + iB = vi v o vi + RB r 124

ECE65 Lecture Notes (F. Najmabadi), Winter 2006

Since vo vi , we have ii = vi /RB or Ri vi = RB ii

Note that RB is the combination of our biasing resistors R1 and R2 . With alternative biasing schemes which do not require R1 and R2 , (and, therefore RB ), the input resistance of the emitter follower circuit will become large. In this case, we cannot use vo vi . Using the full expression for vo from above, the input resistance of the emitter follower circuit becomes: Ri vi = RB ii [r + (RE ro )(1 + )]

and it is quite large (hundreds of k to several M) for RB . Such a circuit is in fact the rst stage of the 741 OpAmp. The output resistance of the common collector amplier (in fact for all transistor ampliers) is somewhat complicated because the load can be congured in two ways (see gure): First, RE , itself, is the load. This is the case when the common collector is used as a current amplier to raise the power level and to drive the load. The output resistance of the circuit is Ro as is shown in the circuit model. This is usually the case when values of Ro and Ai (current gain) is quoted in electronic text books.
VCC R1 vi Cc vo R2 RE = RL

VCC R1 vi Cc vo R2 RE RL

RE is the Load

Separate Load

vi

Cc

B
i
B

E
i ro
B

vo RE

vi

Cc

B
i
B

E
i ro
B

vo

RB

RB

RE

RL

C
Ro

C
R o

Alternatively, the load can be placed in parallel to RE . This is done when the common collector amplier is used as a buer (Av 1, Ri large). In this case, the output resistance is denoted by Ro (see gure). For this circuit, BJT sees a resistance of RE RL . Obviously, if we want the load not to aect the emitter follower circuit, we should use RL to be much
ECE65 Lecture Notes (F. Najmabadi), Winter 2006

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larger than RE . In this case, little current ows in RL which is ne because we are using this conguration as a buer and not to amplify the current and power. As such, value of Ro or Ai does not have much use. When RE is the load, the output resistance can be found by killing the source (short vi ) and nding the Thevenin resistance of the two-terminal network (using a test voltage source). vT KCL: iT = iB + iB ro KVL (outside loop): r iB = vT
vi Cc

B
i
B

E
iB

iT vT

RB

ro

C
Ro

Substituting for iB from the 2nd equation in the rst and rearranging terms we get: Ro vT (ro ) r = iT (1 + )(ro ) + r r , the expression for Ro simplies to

Since, (1 + )(ro ) Ro

(ro ) r r r = = re (1 + )(ro ) (1 + )

As mentioned above, when RE is the load the common collector is used as a current amplier to raise the current and power levels . This can be seen by checking the current gain in this amplier: io = vo /RE , ii vi /RB and Ai io RB = ii RE
vi Cc

B
i
B

E
iB RE

iT vT

RB

ro

We can calculate Ro , the output resistance when an additional load is attached to the circuit (i.e., RE is not the load) with a similar procedure: we need to nd the Thevenin resistance of the two-terminal network (using a test voltage source). We can use our previous results by noting that we can replace ro and RE with ro = ro RE which results in a circuit similar to the case with no RL . Therefore, Ro has a similar expression as RO if we replace ro withro :
ECE65 Lecture Notes (F. Najmabadi), Winter 2006

C
R o vi Cc

B
i
B

E
iB

iT vT

RB

r o

C
R o

126

Ro

vT (ro ) r = iT (1 + )(ro ) + r r (unless we choose a small value for RE ) and Ro re

In most circuits, (1 + )(ro )

In summary, the general properties of the common collector amplier (emitter follower) include a voltage gain of unity (Av 1), a very large input resistance Ri RB (and can be made much larger with alternate biasing schemes). This circuit can be used as buer for matching impedance, at the rst stage of an amplier to provide very large input resistance (such in 741 OpAmp). The common collector amplier can be also used as the last stage of some amplier system to amplify the current (and thus, power) and drive a load. In this case, RE is the load, Ro is small: Ro = re and current gain can be substantial: Ai = RB /RE . Impact of Coupling Capacitor: Up to now, we have neglected the impact of the coupling capacitor in the circuit (assumed it was a short circuit). This is not a correct assumption at low frequencies. The coupling capacitor results in a lower cut-o frequency for the transistor ampliers. In order to nd the cut-o frequency, we need to repeat the above analysis and include the coupling capacitor impedance in the calculation. In most cases, however, the impact of the coupling capacitor and the lower cut-o frequency can be deduced be examining the amplier circuit model. Consider our general model for any amplier circuit. If we assume that coupling capacitor is short circuit (similar to our AC analysis of BJT amplier), vi = vi .
Vi Cc Ro + V i Ri Io + AVi Vo ZL

Voltage Amplifier Model

When we account for impedance of the capacitor, we have set up a high pass lter in the input part of the circuit (combination of the coupling capacitor and the input resistance of the amplier). This combination introduces a lower cut-o frequency for our amplier which is the same as the cut-o frequency of the high-pass lter: l = 2 fl = 1 Ri Cc

Lastly, our small signal model is a low-frequency model. As such, our analysis indicates that the amplier has no upper cut-o frequency (which is not true). At high frequencies, the capacitance between BE , BC, CE layers become important and a high-frequency smallsignal model for BJT should be used for analysis. You will see these models in upper division
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courses. Basically, these capacitances results in amplier gain to drop at high frequencies. PSpice includes a high-frequency model for BJT, so your simulation should show the upper cut-o frequency for BJT ampliers. Common Emitter Amplier DC analysis: Recall that an emitter resistor is necessary to provide stability of the bias point. As such, the circuit conguration as is shown has as a poor bias. We need to include RE for good biasing (DC signals) and eliminate it for AC signals. The solution to include an emitter resistance and use a bypass capacitor to short it out for AC signals as is shown.
VCC VCC

R1 Cc

RC vo vi

R1 Cc

RC vo

vi

R2

R2

RE

Cb

Poor Bias

Good Bias using a bypass capacitor

For this new circuit and with the capacitors open circuit, this circuit is the same as our good biasing circuit of page 110. The bias point currents and voltages can be found using procedure of pages 110-112. AC analysis: To start the analysis, we kill all DC sources, combine R1 and R2 into RB and replace the BJT with its small signal model. We see that emitter is now common between input and output AC signals (thus, common emitter amplier. Analysis of this circuit is straightforward. Examination of the circuit shows that:
vi Cc

B
i
B

C
iB

vo

vi = r iB Av

vo = (RC vi r Ri = R B r

vo = (RC

ro ) iB RC RC = r re
RB

ro

RC

ro )

E
Ro R o

The negative sign in Av indicates 180 phase shift between input and output. The circuit has a large voltage gain but has a medium value for input resistance. As with the emitter follower circuit, the load can be congured in two ways: 1) RC is the load; or 2) load is placed in parallel to RC . The output resistance can be found by killing the source (short vi ) and nding the Thevenin resistance of the two-terminal network. For this circuit, we see that if vi = 0 (killing the source), iB = 0. In this case, the strength of

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the dependent current source would be zero and this element would become an open circuit. Therefore, Ro = r o Ro = R C ro

Lower cut-o frequency: Both the coupling and bypass capacitors contribute to setting the lower cut-o frequency for this amplier, both act as a high-pass lter with: l (coupling ) = 2 fl = 1 Ri Cc 1 l (bypass) = 2 fl = RE Cb re re and, therefore, RE re .

where RE RE Note that usually RE

In the case when these two frequencies are far apart, the cut-o frequency of the amplier is set by the larger cut-o frequency. i.e., l (bypass) l (coupling ) l (coupling ) l (bypass) 1 Ri Cc 1 l = 2 fl = RE Cb l = 2 fl =

When the two frequencies are close to each other, there is no exact analytical formulas, the cut-o frequency should be found from simulations. An approximate formula for the cut-o frequency (accurate within a factor of two and exact at the limits) is: l = 2 fl = 1 1 + Ri Cc RE Cb

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Common Emitter Amplier with Emitter resistance A problem with the common emitter amplier is that its gain depend on BJT parameters Av (/r )RC . Some form of feedback is necessary to ensure stable gain for this amplier. One way to achieve this is to add an emitter resistance. Recall impact of negative feedback on OpAmp circuits: we traded gain for stability of the output. Same principles apply here.
VCC

R1 Cc

RC vo

vi

R2

DC analysis: With the capacitors open circuit, this circuit is the RE same as our good biasing circuit of page 110. The bias point currents and voltages can be found using procedure of pages 110-112. AC analysis: To start the analysis, we kill all DC sources, combine R1 and R2 into RB and replace the BJT with its small signal model. Analysis is straight forward using node-voltage method.
vi C1

B
+ v
BE

vo

vE v i vE vE v o + iB + =0 r RE ro vo vo v E + + iB = 0 RC ro vi v E iB = (Controlled source aux. Eq.) r

iB

ro

RB

E
RE RC

Substituting for iB in the node equations and noting 1 + , we get : vE v i vE v o vE + + =0 RE r ro vo vo v E vE v i + =0 RC ro r Above are two equations in two unknowns (vE and vo ). Adding the two equation together we get vE = (RE /RC )vo and substituting that in either equations we can nd vo . Using r / = re , we get: Av = vo RC RC = vi re (1 + RC /ro ) + RE (1 + re /ro ) re (1 + RC /ro ) + RE ro and

where we have simplied the equation noting re ro . For most circuits, RC re RE . In this case, the voltage gain is simply Av = RC /RE .
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The input resistance of the circuit can be found from (prove it!) Ri = R B vi iB

Noting that iB = (vi vE )/r and vE = (RE /RC )vo = (RE /RC )Av vi , we get: Ri = R B r 1 + Av RC /RE 1), we get:

Substituting for Av from above (complete expression for Av with re /ro Ri = R B RE + re 1 + RC /ro ro and re

For most circuits, RC Ri = RB (RE ).

RE . In this case, the input resistance is simply

As before the minus sign in Av indicates a 180 phase shift between input and output signals. Note the impact of negative feedback introduced by the emitter resistance: The voltage gain is independent of BJT parameters and is set by RC and RE (recall OpAmp inverting amplier!). The input resistance is also increased dramatically. As with the emitter follower circuit, the load can be congured in two ways: 1) RC is the load. 2) Load is placed in parallel to RC . The output resistance can be found by killing the source (short vi ) and nding the Thevenin resistance of the two-terminal network (by attaching a test voltage source to the circuit). Resistor RB drops out of the circuit because it is shorted out. Resistors r and RE are in parallel. Therefore, i1 = (r /RE )iB and by KCL, i2 = ( + 1 + r /RE )iB . Then: iT = iB i1 = iB 1 + r RE r RE + r
B
B
i
B

C
iB ro

iT

E
i1 RE

i2

vT

Ro

C
iB ro

iT

E
i1 RE

i2

RC

vT

vT = iB r i2 ro = iB ro + 1 + Then: Ro = 1 + ro /re vT = ro + RE iT 1 + RE /r

R o

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131

where we have used r / = re . Generally ro re (rst approximation below) and for most circuit, RE r (second approximation) leading to Ro r o + r o RE RE ro RE /re ro + = ro +1 1 + RE /r re re

Value of Ro can be found by a similar procedure. Alternatively, examination of the circuit shows that Ro = R C Ro RC

Lower cut-o frequency: The coupling capacitor together with the input resistance of the amplier lead to a lower cut-o frequency for this amplier (similar to emitter follower). The lower cut-o frequency is given by: l = 2 fl = 1 Ri Cc

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132

A Possible Biasing Problem: The gain of the common emitter amplier with the emitter resistance is approximately RC /RE . For cases when a high gain (gains larger than 5-10) is needed, RE may be become so small that the necessary good biasing condition, VE = RE IE > 1 V cannot be fullled. The solution is to use a by-pass capacitor as is shown. The AC signal sees an emitter resistance of RE 1 while for DC signal the emitter resistance is the larger value of RE = RE 1 + RE 2 . Obviously formulas for common emitter amplier with emitter resistance can be applied here by replacing RE with RE 1 as in deriving the amplier gain, and input and output impedances, we short the bypass capacitor so RE 2 is eectively removed from the circuit.

VCC

R1 Cc

RC vo

vi

R2

R E1

R E2

Cb

The addition of by-pass capacitor, however, modies the lower cut-o frequency of the circuit. Similar to a regular common emitter amplier with no emitter resistance, both the coupling and bypass capacitors contribute to setting the lower cut-o frequency for this amplier. Similarly we nd that an approximate formula for the cut-o frequency (accurate within a factor of two and exact at the limits) is: l = 2 fl = 1 1 + Ri Cc RE Cb (RE 1 + re )

where RE RE 2

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133

Summary of BJT Ampliers

Common Collector (Emitter Follower): (RE ro )(1 + ) 1 Av = r + (RE ro )(1 + ) Ri = R B [r + (RE (ro ) r r Ro = = re (1 + )(ro ) + r Ro = r (ro ) r (1 + )(ro ) + r ro )(1 + )] RB 1 2 fl = Ri Cc RC
R1

VCC R1 vi Cc vo R2 RE

where ro = ro

VCC

Common Emitter: (RC r Ri = R B r Av = Ro = r o ro ) RC RC = r re

vi

RC vo

Cc

R2

Ro = R C 1 1 + 2 fl = Ri Cc RE Cb

ro RC where RE RE re

RE

Cb

VCC

Common Emitter with Emitter Resistance: RC RC RC Av = re (1 + RC /ro ) + RE re + R E RE Ri = R B RE + re 1 + RC /ro RB RE RB

vi

R1 Cc

RC vo

R2 RE

RE /re RE Ro r o + r o ro +1 1 + RE /r re Ro = R C Ro RC and 2 fl = 1 Ri Cc
R1 Cc

VCC

Replace RE with RE 1 in the above formulas except 1 1 + 2 fl = Ri Cc RE Cb where RE RE 2 (RE 1 + re )

vi

RC vo

R2

R E1

If bias resistors are not present (e.g., bias with current mirror), let RB in the full expression for Ri .
ECE65 Lecture Notes (F. Najmabadi), Winter 2006

R E2

Cb

134

Examples of Analysis and Design of BJT Ampliers Example 1: Find the bias point and AC amplier parameters of this circuit (Manufacturers spec sheets give: hf e = 200, hie = 5 k, hoe = 10 S). r = hie = 5 k DC analysis:
9V

ro =

1 = 100 k hoe

= hf e = 200

re =

r = 25

Replace R1 and R2 with their Thevenin equivalent and proceed with DC analysis (all DC current and voltages are denoted by capital letters): RB = 18 k 22 k = 9.9 k 22 VBB = 9 = 4.95 V 18 + 22 KVL: VBB = RB IB + VBE + 103 IE
3

18k vi 0.47 F vo 22k 1k

IB =

IE IE = 1+ 201
RB IB + VBE VBB

9V IC + _ _ 1k VCE

4.95 0.7 = IE IE = 4 mA IC ,

9.9 10 + 103 201 IC = 20 A

+

IB =

KVL: VCC = VCE + 103 IE VCE = 9 103 4 103 = 5 V DC Bias summary: IE IC = 4 mA, IB = 20 A, VCE = 5 V

AC analysis: The circuit is a common collector amplier. Using the formulas in page 134, Av 1 Ri RB = 9.9 k Ro re = 25 1 1 l = = fl = = 36 Hz 3 2 2RB Cc 2 9.9 10 0.47 106

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135

Example 2: Find the bias point and AC amplier parameters of this circuit (Manufacturers spec sheets give: hf e = 200, hie = 5 k, hoe = 10 S). r = hie = 5 k ro = 1 = 100 k hoe = hf e = 200 re = r = 25
15 V

DC analysis: Replace R1 and R2 with their Thevenin equivalent and proceed with DC analysis (all DC current and voltages are denoted by capital letters). Since all capacitors are replaced with open circuit, the emitter resistance for DC analysis is 270+240 = 510 . RB = 5.9 k 34 k = 5.0 k 5.9 15 = 2.22 V VBB = 5.9 + 34 KVL: VBB = RB IB + VBE + 510IE 2.22 0.7 = IE IB = IE IE = 1+ 201

34 k

1k vo

vi

4.7 F

5.9 k

270

240

47 F

5.0 103 + 510 201

RB IB + VBE VBB

15 V 1k IC + _ _ 270 + 240 = 510 VCE

IC IE = 3 mA IC , IB = = 15 A KVL: VCC = 1000IC + VCE + 510IE VCE = 15 1, 510 3 10 DC Bias: IE IC = 3 mA,

3

= 10.5 V VCE = 10.5 V

IB = 15 A,

AC analysis: The circuit is a common collector amplier with an emitter resistance. Note that the 240 resistor is shorted out with the by-pass capacitor. It only enters the formula for the lower cut-o frequency. Using the formulas in page 134 (with RE 1 = 270 ): Av = RC 1, 000 = = 3.70 RE 1 270 RE 1 RB = 5.0 k R o re RE 1 + 1 = 1.2 M re

Ri R B

RE = RE 2 (RE 1 + re ) = 240 (270 + 25) = 132 l 1 1 fl = = + = 2 2Ri Cc 2RE Cb 1 1 + = 31.5 Hz 6 2 5, 000 4.7 10 2 132 47 106
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136

Example 3: Design a BJT amplier with a gain of 4 and a lower cut-o frequency of 100 Hz. The Q point parameters should be IC = 3 mA and VCE = 7.5 V. (Manufacturers spec sheets give: min = 100, = 200, hie = 5 k, hoe = 10 S).
VCC

r = hie = 5 k

ro =

1 = 100 k hoe

re =

r = 25
vi

R1 Cc

RC vo

The prototype of this circuit is a common emitter amplier with an emitter resistance. Using formulas of page 134 RC |Av | =4 RE The lower cut-o frequency will set the value of Cc . We start with the DC bias: As VCC is not given, we need to choose it. To set the Q-point in the middle of load line, set VCC = 2VCE = 15 V. Then, noting IC IE ,: VCC = RC IC + VCE + RE IE 15 7.5 = 3 10 (RC + RE )
3

R2 RE

VCC RC iC RB iB + vBE VBB + _ _ RE vCE

RC + RE = 2.5 k

Values of RC and RE can be found from the above equation together with the AC gain of the amplier, AV = 4. Ignoring re compared to RE (usually a good approximation), we get: RC =4 RE 4RE + RE = 2.5 k RE = 500 , RC = 2. k

Commercial values are RE = 510 and RC = 2 k. Use these commercial values for the rest of analysis. We need to check if VE > 1 V, the condition for good biasing. VE = RE IE = 510 3 103 = 1.5 > 1, it is OK (See next example for the case when VE is smaller than 1 V). We now proceed to nd RB and VBB . RB is found from good bias condition and VBB from a KVL in BE loop: RB KVL: ( + 1)RE RB = 0.1(min + 1)RE = 0.1 101 510 = 5.1 k

VBB = RB IB + VBE + RE IE 3 103 + 0.7 + 510 3 103 = 2.28 V 201 137

VBB = 5.1 103

ECE65 Lecture Notes (F. Najmabadi), Winter 2006

Bias resistors R1 and R2 are now found from RB and VBB : RB = R 1 VBB VCC R1 R2 = 5 k R1 + R 2 R2 2.28 = 0.152 = = R1 + R 2 15 R2 =

R1 can be found by dividing the two equations: R1 = 33 k. R2 is found from the equation for VBB to be R2 = 5.9 k. Commercial values are R1 = 33 k and R2 = 6.2 k. Lastly, we have to nd the value of the coupling capacitor: l = 1 = 2 100 Ri Cc

Using Ri RB = 5.1 k, we nd Cc = 3 107 F or a commercial values of Cc = 300 nF. So, are design values are: R1 = 33 k, R2 = 6.2 k, RE = 510 , RC = 2 k. and Cc = 300 nF. Example 4: Design a BJT amplier with a gain of 10 and a lower cut-o frequency of 100 Hz. The Q point parameters should be IC = 3 mA and VCE = 7.5 V. A power supply of 15 V is available. Manufacturers spec sheets give: min = 100, hf e = 200, r = 5 k, hoe = 10 S.
VCC

r = hie = 5 k

ro =

1 = 100 k hoe

re =

r = 25
vi

R1 Cc

RC vo

The prototype of this circuit is a common emitter amplier with an emitter resistance. Using formulas of page 134: RC = 10 |Av | RE The lower cut-o frequency will set the value of Cc .

R2 RE

We start with the DC bias: As the power supply voltage is given, we set VCC = 15 V. Then, noting IC IE ,: VCC = RC IC + VCE + RE IE 15 7.5 = 3 103 (RC + RE ) RC + RE = 2.5 k

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138

Values of RC and RE can be found from the above equation together with the AC gain of the amplier AV = 10. Ignoring re compared to RE (usually a good approximation), we get: RC = 10 RE 10RE + RE = 2.5 k RE = 227 , RC = 2.27 k
VCC

We need to check if VE > 1 V which is the condition for good biasing: VE = RE IE = 227 3 103 = 0.69 < 1. Therefore, we need to use a bypass capacitor and modify our circuits as is shown. For DC analysis, the emitter resistance is RE 1 + RE 2 while for AC analysis, the emitter resistance will be RE 1 . Therefore: DC Bias: AC gain: RC + RE 1 + RE 2 = 2.5 k RC = 10 Av = RE 1

R1 Cc

RC vo

vi

R2

R E1

R E2

Cb

Above are two equations in three unknowns. A third equation is derived by setting VE = 1 V to minimize the value of RE 1 + RE 2 . VE = (RE 1 + RE 2 )IE 1 RE 1 + R E 2 = = 333 3 103 Now, solving for RC , RE 1 , and RE 2 , we nd RC = 2.2 k, RE 1 = 220 , and RE 2 = 110 (All commercial values). We can now proceed to nd RB and VBB : RB ( + 1)(RE 1 + RE 2 )
+

VCC RC iC RB iB + vBE VBB + _ _ R E1 + R E2 vCE

RB = 0.1(min + 1)(RE 1 + RE 2 ) = 0.1 101 330 = 3.3 k KVL: VBB = RB IB + VBE + RE IE 3 103 + 0.7 + 330 3 103 = 1.7 V 201 VBB = 3.3 103

Bias resistors R1 and R2 are now found from RB and VB B : RB = R 1 VBB VCC R1 R2 = 3.3 k R1 + R 2 R2 1 = = = 0.066 R1 + R 2 15 R2 = 139

ECE65 Lecture Notes (F. Najmabadi), Winter 2006

R1 can be found by dividing the two equations: R1 = 50 k and R2 is found from the equation for VBB to be R2 = 3.6k . Commercial values are R1 = 51 k and R2 = 3.6k Lastly, we have to nd the value of the coupling and bypass capacitors: RE = R E 2 (RE 1 + re ) = 110 (220 + 25) = 76

Ri RB = 3.3 k 1 1 l = + = 2 100 Ri Cc RE Cb This is one equation in two unknown (Cc and CB ) so one can be chosen freely. Typically Cb Cc as Ri RB RE RE . This means that unless we choose Cc to be very small, the cut-o frequency is set by the bypass capacitor. The usual approach is the choose C b based on the cut-o frequency of the amplier and choose Cc such that cut-o frequency of the Ri Cc lter is at least a factor of ten lower than that of the bypass capacitor. Note that in this case, our formula for the cut-o frequency is quite accurate (see discussion in page 129) and is l 1 = 2 100 RE Cb

This gives Cb = 20 F. Then, setting 1 1 Ri Cc RE Cb 1 1 = 0.1 Ri Cc RE Cb Ri Cc = 10RE Cb Cc = 4.7 106 = 4.7 F

So, are design values are: R1 = 50 k, R2 = 3.6 k, RE 1 = 220 , RE 2 = 110 , RC = 2.2 k, Cb = 20 F, and Cc = 4.7 F. An alternative approach is to choose Cb (or Cc ) and compute the value of the other from the formula for the cut-o frequency. For example, if we choose Cb = 47 F, we nd Cc = 0.86 F.

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140

Example 5: Find the bias point and AC amplier parameters of this circuit (Manufacturers spec sheets give: = 200, r = 5 k, ro = 100 k).
15 V

This is a two-stage amplier. The rst stage (Tr1) is a common emitter amplier and the second stage (Tr2) is an emitter follower. The two stages are coupled by a coupling capacitor (0.47 F). DC analysis: When we replace the coupling capacitors with open circuits, we see the that bias circuits for the two transistors are independent of each other. Each bias circuit can be solved independently.

33k vi 4.7 F

2k

18k 0.47 F Tr2 vo 22k 1k

Tr1 6.2k 500

For Tr1, we replace the bias resistors (6.2k and 33k) with their Thevenin equivalent and proceed with DC analysis: RB 1 = 6.2 k 33 k = 5.22 k and VBB 1 = IB 1 6.2 15 = 2.37 V 6.2 + 33 IE 1 IE 1 = = 1+ 201

BE-KVL: VBB 1 = RB 1 IB 1 + VBE 1 + 103 IE 1 2.37 0.7 = IE 1 IE 1 = 3.17 mA IC 1 , 5.22 103 + 500 201 IC 1 = 16 A

IB 1 =

CE-KVL: VCC = 2 103 IC 1 + VCE 1 + 500IE 1 VCE 1 = 15 2.5 103 3.17 103 = 7.1 V DC Bias summary for Tr1: IE 1 IC 1 = 3.17 mA, Following similar procedure for Tr2, we get: RB 2 = 18 k 22 k = 9.9 k and VBB 2 = 22 15 = 8.25 V 18 + 22 IE 2 IE 2 = IB 2 = 1+ 201 IB 1 = 16 A, VCE 1 = 7.1 V

BE-KVL: VBB 2 = RB 2 IB 2 + VBE 2 + 103 IE 2 8.25 0.7 = IE 2 9.9 103 + 103 201

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IE 2 = 7.2 mA IC 2 ,

IB 2 =

IC 2 = 36 A

CE-KVL: VCC = VCE 2 + 103 IE 2 VCE 2 = 15 103 7.2 103 = 7.8 V DC Bias summary for TR2: IE 2 IC 2 = 7.2 mA, AC analysis: We start with the emitter follower circuit (Tr2) as the input resistance of this circuit will appear as the load for the common emitter amplier (Tr1). Using the formulas in page 134: Av 2 1 Ri2 RB 2 = 9.9 k 1 1 l 2 = = = 34 Hz fl 2 = 3 2 2RB 2 Cc2 2 9.9 10 0.47 106 Since Ri2 = 9.9 k is NOT much larger than the collector resistor of common emitter amplier (Tr1), it will aect the rst circuit. Following discussion in pages 125 and 128, the eect of this load can be taken into by replacing RC in common emitter ampliers formulas with RC = RC RL = RC 1 Ri2 = 2 k 9.9 k = 1.66 k. RC 1.66k = = 3.3 RE 500 Ri1 RB 1 = 5.22 k l 1 1 1 fl 1 = = = = 6.5 Hz 2 2RB 1 Cc1 2 5.22 103 4.7 106 |Av1 | The overall gain of the two-stage amplier is then Av = Av1 Av2 = 3.3. The input resistance of the two-stage amplier is the input resistance of the rst-stage (Tr1), Ri = 9.9 k. To nd the lower cut-o frequency of the two-stage amplier, we note that: Av1 (j ) = Av 1 1 jl1 / and Av2 (j ) = Av 2 1 jl2 / IB 2 = 36 A, VCE 2 = 7.8 V

Av (j ) = Av1 (j ) Av2 (j ) =

Av 1 Av 2 (1 jl1 / )(1 jl2 / )

From above, it is clear that the maximum value of Av (j ) is Av1 Av2 and the cut-o frequency, l can be found from |Av (j = l )| = Av1 Av2 / 2 (similar to procedure we used for lters). For the circuit above, since l2 l1 the lower cut-o frequency would be very close to l2 . So, the lower-cut-o frequency of this amplier is 34 Hz.
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Example 6: Find the bias point and AC amplier parameters of this circuit (Manufacturers spec sheets give: = 200, r = 5 k, ro = 100 k).
15 V

This is a two-stage amplier. The rst stage (Tr1) is a common emitter amplier and the second stage (Tr2) is an emitter follower. The circuit is similar to the twostage amplier of Example 5. The only difference is that Tr2 is directly biased from Tr1 and there is no coupling capacitor between the two stages. This approach has its own advantages and disadvantages that are discussed at the end of this example. DC analysis:

33k vi 4.7 F

2k

I1 IB2 I C1 Tr1 V B2 1k Tr2 vo

6.2k

500

Since the base current in BJTs are typically much smaller that the collector current, we start by assuming IC 1 IB 2 . In this case, I1 = IC 1 + IB 2 IC 1 IE 1 (the bias current IB 2 has no eect on bias parameters of Tr1). This assumption simplies the analysis considerably and we will check the validity of this assumption later. For Tr1, we replace the bias resistors (6.2k and 33k) with their Thevenin equivalent and proceed with DC analysis: RB 1 = 6.2 k 33 k = 5.22 k and VBB 1 = IB 1 6.2 15 = 2.37 V 6.2 + 33 IE 1 IE 1 = = 1+ 201

BE-KVL: VBB 1 = RB 1 IB 1 + VBE 1 + 103 IE 1 2.37 0.7 = IE 1 IE 1 = 3.17 mA IC 1 , 5.22 103 + 500 201 IC 1 = 16 A

IB 1 =

CE-KVL: VCC = 2 103 IC 1 + VCE 1 + 500IE 1 VCE 1 = 15 2.5 103 3.17 103 = 7.1 V DC Bias summary for Tr1: IE 1 IC 1 = 3.17 mA, To nd the bias point of TR2, we note: VB 2 = VCE 1 + 500 IE 1 = 7.1 + 500 3.17 103 = 8.68 V
ECE65 Lecture Notes (F. Najmabadi), Winter 2006

IB 1 = 16 A,

VCE 1 = 7.1 V

143

BE-KVL: VB 2 = VBE 2 + 103 IE 2 8.68 0.7 = 103 IE 2 IE 2 = 8.0 mA IC 2 , IB 2 = IC 2 = 40 A

KVL: VCC = VCE 2 + 103 IE 2 VCE 2 = 15 103 8.0 103 = 7.0 V DC Bias summary for TR2: IE 2 IC 2 = 8.0 mA, We now check our assumption of IC 1 our assumption was justied. IB 2 = 40 A, VCE 2 = 7.0 V IB 2 = 41 A. So,

IB 2 . We nd IC 1 = 3.17 mA

It should be noted that this bias arrangement is also stable to variation in transistor . The bias resistors in the rst stage will ensure that IC 1 ( IE 1 ) and VCE 1 is stable to variation of TR1 . Since VB 2 = VCE 1 + RE 1 IE 1 , VB 2 will also be stable to variation in transistor . Finally, VB 2 = VBE 2 + RE 2 IE 2 . Thus, IC 2 ( IE 2 ) will also be stable (and VCE 2 because of CE-KVL). AC analysis: As in Example 5, we start with the emitter follower circuit (Tr2) as the input resistance of this circuit will appear as the load for the common emitter amplier (Tr1). Using the formulas in page 134 and noting that this amplier does not have bias resistors (RB 1 ): Av 2 1 Ri2 = r + (RE ro )(1 + ) = 5 103 + 201 103 = 201 k

Note that because of the absence of the bias resistors, the input resistance of the circuit is very large, and because of the absence of the coupling capacitors, there is no lower cut-o frequency for this stage. Since Ri2 = 201 k is much larger than the collector resistor of common emitter amplier (Tr1), it will NOT aect the rst circuit. The parameters of the rst-stage common emitter amplier can be found using formulas of page 134. |Av1 | RC 2, 000 = =4 RE 500 Ri1 RB 1 = 5.22 k 1 1 l 1 = = = 6.5 Hz fl 1 = 2 2RB 1 Cc1 2 5.22 103 4.7 106 144

ECE65 Lecture Notes (F. Najmabadi), Winter 2006

The overall gain of the two-stage amplier is then Av = Av1 Av2 = 4. The input resistance of the two-stage amplier is the input resistance of the rst-stage (Tr1), Ri = 9.9 k. The nd the lower cut-o frequency of the two-stage amplier is 6.5 Hz. The two-stage amplier of Example 6 has many advantages over that of Example 5. It has three less elements. Because of the absence of bias resistors, the second-stage does not load the rst stage and the overall gain is higher. Also because of the absence of a coupling capacitor between the two-stages, the overall cut-o frequency of the circuit is lower. Some of these issues can be resolved by design, e.g., use a large capacitor for coupling the two stages, use a large RE 2 , etc.. The drawback of the Example 6 circuit is that the bias circuit is more complicated and harder to design.

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