An Illustration of 0.

1m CMOS layout design on PC

Agenda
The technology scale down Design trends The MOS device CMOS cell design Signal propagation Embedded Memory SOI

giving you the squeeze of nanometer design technology

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1. The technology scale down

1992

10 10 years years of of evolution evolution

2002
0.12m, 7 metal Up to 500MT, 1.5GHz
Introduction to CMOS design on PC Microwind, Dsch

0.7m, 2 metal layers Up to 100K transistors, 50MHz

Introduction to Electronics on PC

IC

MSK, PROF, 3D

giving you the squeeze of nanometer design technology

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1. The technology scale down

1992 Devices 0.7 m

2000 0.18 m
1992-2002

2003

90nm

Slightly decreased 1014 1 nMOS, 1pMOS 3 nMOS, 3pMOS neurons Interconnects 2 layers Slightly increased number 7 layers of students Endless fight against obsolete teaching Constant 24H per day

6 nMOS, 6pMOS

8 layers

Frequency 5V

2V

1V

50MHz

500MHz
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1.5GHz

giving you the squeeze of nanometer design technology

2. Design trends
Complexity (Millions transistors) Technology always ahead
RF RF RS RS Host Interface Code Manager

100 10 1.0 0.1 0.01

Link Link Controller Controller

System design

IP design

Logic design

Layout design

1992

1994

1996

1998

2000

2002

giving you the squeeze of nanometer design technology

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2004 Microwind

2. Design trends
Core
Physical level 3 BSIM BSIM3 VHDL-Ams BSIM4 SystemC

Structural

VHDL, Verilog

Interface
Physical

IBIS 1000 1997 100 10 Level 1 1

IBIS v2 Model parameters

IBISv3

IBIS-ML

1995

1999
Bsim Level 2 Level 3 1980 1990 Bsim2 MM9

2001
Bsim4 BsimSOI

2003

1970

2000

2010

giving you the squeeze of nanometer design technology

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3. The MOS devices

Dependence of Id vs. Length Impact ionization at high Vds

0.5.DVT0 (Vbi s ) Leff 1) cosh(DVT1. lt

Important Ioff current for small Length Complex dependence of Vt vs. Length

vth = VTHO + K1. ( s Vbs s ) K 2.Vbs + Vt SCE + Vt NULD + Vt DIBL

Vt SCE =

Vt NULD = K1( 1 +

LPE0 1). s L eff

Vt DIBL = 0.5.ETA 0.Vds

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3. The MOS devices

Ultra High Speed Low Leakage High Voltage EEProm

RF High Speed
Application-oriented MOS device Same basic mechanism

MRam

New physical properties in EEPROM and MRam

giving you the squeeze of nanometer design technology
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3. The MOS devices

Ioff ~10nA

Ioff ~100pA

Small Ion reduction

High Speed
High current MOS, low VT Shorter channel L=100nm, high leakage (Critical path)

Low Leakage
Default MOS device, high VT low leakage (<1nA)

giving you the squeeze of nanometer design technology

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4. CMOS cell design

Stacked vias Salicide/unsalicide (Large R) but Antenna effects Contact parasitic effect (20 )
giving you the squeeze of nanometer design technology
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5. Signal propagation
5 4 3 2 1 0 0 1 2 3ns 1 Volt 3 2 Volt

0.7 m

0.35 m

Volt 2 1.5 1 0.5

0.18m

Al

0 0 0.5

Al
1.0 1.5ns

0 0 0.25 0.5

Cu
0.75 1.0ns

3mm

3Rx3C=9RC (680ps) Repeaters help to propagate signals at long distance 3RC+2tgate (380ps)

giving you the squeeze of nanometer design technology

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1mm

1mm

1mm

5. Signal propagation
0.7m Small coupling 0.12m Strong coupling

Very large noise, close from fault Low K to reduce coupling Long distance routing is forbidden (Critical routing length 2mm in 0.12m)
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6. Embedded Memories
80% of a system-on-chip Bottleneck for bandwidth

Cmos Embedded memories

Volatile

Non volatile

eDRAM

SRAM

ROM

EEPROM

FRAM

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6. Embedded Memories

CS CB

Parasitic capacitance: 2fF

Specific capacitance: 3-30fF

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giving you the squeeze of nanometer design technology

6. Embedded Memories
VDD

Create a small channel

VDD

Cannot create channel

Electrons injected in the floating gate by tunneling

giving you the squeeze of nanometer design technology

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7. SOI
The next major evolution? CMOS compatible Less distance between nMOS and pMOS Less capacitance Less leakage >50% faster circuits Kink effect
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Fully or partially depleted?

giving you the squeeze of nanometer design technology

Conclusion
The technology scale down has been illustrated Design trend towards higher levels of abstraction More MOS options oriented to applications in 0.1m technology Increased interconnect layers improve density but many issues RC delay & crosstalk illustrated Embedded memories have several design styles and technological option Substrate below 0.1m should be in SOI Lots of educational messages illustrated in Microwind PC tool
giving you the squeeze of nanometer design technology
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