SYLLABUS 13MEVL202 LOW POWER VLSI DESIGN 3 0 0 3 100

UNIT I POWER DISSIPATION IN CMOS Sources of power dissipation Physics of power dissipation in CMOS FET devices- Basic principle of low power design. UNIT II POWER OPTIMIZATION Logical level power optimization Circuit level low power design: logic styles, transistor sizing and ordering Circuit techniques for reducing power consumption in adders and multipliers. UNIT III DESIGN OF LOW POWER CMOS CIRCUITS Computer Arithmetic techniques for low power systems Reducing power consumption in memories Advanced techniques: Adiabatic Computation, Asynchronous Circuits Special techniques UNIT IV POWER ESTIMATION AND ANALYSIS Logic level power estimation Simulation power analysis Probabilistic power analysis UNIT V SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Synthesis for low power Behavioral level transforms- Software design for low power Software Power Estimation Software Power Optimization REFERENCES
S.NO Author(s) Name Title of the book Publisher Year of publication

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Roy.K and Prasad.S.C Dimitrios Soudris, Chirstian Pignet, Costas Goutis Kuo.J.B and Lou.J.H Chandrakasan.A.P and Broadersen.R.W Gary Yeap

Low Power CMOS VLSI circuit design Designing CMOS Circuits For Low Power Low voltage CMOS VLSI Circuits Low power digital CMOS design Practical low power digital VLSI design

Wiley, New Jersey Kluwer academic publishers, Boston

2000 2002

3 4 5

Wiley, New Jersey Kluwer academic publishers, Boston Kluwer academic publishers, Boston

1999 1995 1998

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HOD / ECE