A BIST Scheme for Testing DAC

Chun Wei Lin

Department of Electronic Engineering, National Yunlin University of Science & Technology, Yunlin 64002, Taiwan linwei@yuntech.edu.tw
Abstract In this paper, we propose a low speed built-in-self-test (BIST) scheme for testing static parameters of high-speed digitalto-analog converter (DAC). Based on under-sampling technique, the DAC output signal is modulated into low speed pulse signal by pulse-width-modulation (PWM) with two sinusoidal carriers. The nonlinearity errors of DAC hence represents on duty ratio of converted pulse signal. In addition, a precise embedded time-todigital converter (TDC) is inserted to measure the pulse width of converted signal on chip. The static parameters of DAC then can be estimated through analyzing output signal of TDC captured by conventional logic analyzer. To demonstrate the proposed scheme, we applied the method on 8-bits 200MS/s DAC. The experiment showed very good result that the maximum estimated error of DNL and INL are less than 0.2LSB and 0.35LSB. Moreover, the most important merit is that the required test environment and equipment are low speed compared to DAC under test. Keywords- DAC; testing; BIST; PWM; TDC

Sheng Feng Lin

Graduate School of Engineering Science and Technology, National Yunlin University of Science & Technology, Yunlin 64002, Taiwan g9510812@yuntech.edu.tw without using any high speed or high resolution test equipments. II. THE PRELIMINARY OF PROPOSED METHOD

The fundamental concept of developed test scheme is shown in Fig. 1 [9]. Through pulse-width-modulation, the analog signal of DAC is converted into low speed pulse width variation, which can be used to estimate the nonlinearity error of DAC.
f ( t )

DAC

Lowpass filter
Sin. Wave generator

s (t )

w(t )

Comparator
f ( 't )

(a)
f ( t )

I.

INTRODUCTION

High-speed DACs are one of the most critical circuit modules for communication systems and multi-media devices. However, testing these converters is a very difficult task. Conventional test methods require instruments with higher speed and accuracy than DAC under test [1]. In order to avoid transferring analog signal to external instruments directly, onchip testing approach was proposed to obtain accurate test result for high speed DAC [2-5]. In addition, BIST approach can overcome the requirements of high performance test equipment. The analog signal under test can be converted into specific test signature through builtin circuits for convenience of analysis. By converting the amplitude of analog signal of DAC into the representation of duty ratio or frequency of pulse signal, the analog signal can be measured by a digital counter [6-8]. However, these BIST techniques need some complex modules such as code memory, high speed on-chip processing circuits or arithmetic logic unit, which may increase design effort and raise another test issue on these circuits. In this paper, we propose a BIST scheme for DAC testing based on a new under-sampling technique. The analog signal of DAC is modulated by the two sinusoidal carriers and then converted into low speed pulse stream. The relationship between nonlinearity of DAC and width of pulse stream can be further derived. Under this method, we can use conventional on-chip TDCs to quantify the nonlinearity error of DAC

Vdac
P2

f ( 't )
P3

P1

V1 Tdac W1

V2

Vdac

W2

s(t ) w(t )
W1 = Tdac + W1 W2 = Tdac + W2

(b) Figure. 1 (a) The concept of proposed BIST scheme. (b) The relative signals.

Assume f ( t ) and f ( ' t ) are the output signal of DAC and carrier of modulation respectively. If we plan to capture N sample points, the operation frequency of carrier should be decided as:

f ( ' t ) = and

1 Tdac + T

978-1-4673-2025-2/12/$31.00 2012 IEEE

T <

Tdac 2
i =1 N

1 mdac 1 + m [i ] s

, where Tdac is period of DAC output signal, T is the difference of period between output signal of DAC and sinusoidal carrier, mdac is the ideal slope of output signal of DAC and ms [i ] is the slope of sinusoidal carrier.

the PWM process inherently. This is because the sinusoidal carrier using in PWM is treated to be combination of many linear pieces when developing the estimation method of DNL. In addition, the variation of this error is periodic since it appears cyclically with respect to frequency of DAC output signal. For this reason, the estimated INL should be characterized to be: INLestimation [i ] = DNLestimation = [ DNLreal [k ] + (k )]
k =1 k =1 i i

After modulation, the voltage difference Vi of adjacent sample points Pi is converted to pulse width variation Wi , where Wi = Tdac + Wi . Therefore, the nonlinearity error of DAC, f (t ) / dt , will be represented as the variation of pulse width, i.e. Wi . If Wi is the pulse width of modulated signal in faulty case, the slope of faulty signal of DAC can be estimated and represented as:

, where (k ) is systematic error in DNL and =

2 . Tdac

Because period of DAC output signal is quite a large value, we know that the frequency of systematic error is far less than operational frequency of DAC. Consequently, we can remove systematic error and yield more accurate INL estimation simply by using a high pass filter (HPF) which modifies the INL estimation to be: INL[i ] = HPF { [ DNLreal [k ] + (k )]} = DNLreal [k ]
k =1 k =1 i i

mi =

T (Wi Tdac ) m s [i ] Wi Tdac

For the differential nonlinearity (DNL) estimation, we assume N sample points are captured and the slopes between adjacent points are calculated. The DNL of n-bits DAC with N sample points can be estimated through the following algorithm:

III.

THE DUAL UNDER-SAMPLING TECHNIQUE

for (mi ; i = 1 to N )
find local max imum set

mmax [k ] = {mmk }, k = 1,2,...,2 n 1

for (k = 1 to 2 n 1) case (mmk +1 > mmk +1 2 > mmk +1 1 )

mk +1 1

In the previous section, we described the concept of proposed method and expressed the nonlinearity estimation in detail. To proceed to analyze the converted digital stream, we need an embedded time-to-digital converter (TDC) to quantify its variation on pulse width and estimate nonlinearity error according to the derived relationship. However, the pulse width of this digital stream would quite large. For example, an 8-bits 200MS/s DAC with 255 quantization levels, the pulse width of converted digital signal is about 2.55s. Because the ordinary TDC is designed for measuring tiny quantity, the excess hardware cost for measuring so large pulse width is undesirable. On the contrary, the TDC designed for measuring large quantity would lose its accuracy and lead to inaccurate analysis. On purpose of reducing design effort of TDC, we develop the dual under-sampling technique to convert output signal of DAC into digital stream with narrow pulse width. The fundamental concept of the method is shown in Fig. 2(a). It also consists of a sinusoidal carrier generator, two comparators, logic control unit, TDC and an all-pass filter acted as a delay element. The all-pass filter is employed to generate the second sinusoidal carrier with a phase delay t d as shown in Fig. 2(b). The comparators modulate output signal of DAC by both two carriers and result in narrow phase difference between two digital streams representing the nonlinearity variation of DAC output signal. The followed logic unit distinguishes this narrow phase difference from two digital streams and the TDC converts these pulse widths into readable binary codes. We accordingly extract the characteristics of DAC output signal and read them upon digital test equipment or instruments. In order to explain the relationship between the slope of output signal of DAC and two carriers, we enlarge the shadow area of Fig. 2(b) into Fig. 2(c) and Fig. 2(d) which denote fault free and faulty case respectively.

DNL[k ] =

j = mk 1

mk +1 mk + 1

case (mmk +1 > mmk +1 1 > mmk +1 2 )

mk +1 2

DNL[k ] =

j = mk 1

mk +1 mk

The integral nonlinearity (INL) generally can be calculated from DNL and expressed to be: INLestimation [i ] = DNL[k ]
k =1 i

Using this simple expression for INL estimation is intuitive but also lead error in calculation. A little bit of systematic error in DNL estimation will be integrated into an unbelievable error. In our proposed scheme, the systematic error is brought from

DAC Sin. Wave generator

f ( t ) f ( 't )

Comparator

s (t )
Control unit

w(t )

TDC

D (t )

Moreover, to ensure the capture of at least one sample within every quantization level of DAC, we need to define the valid region of the phase delay td between two carriers. The phase delay t d should meet following condition for n-bits DAC: td < Tdac 2 (2 n 1)

All pass Comparator s d (t ) filter f ( 't t d )

(a)
f ( t )
f ( 't ) f ( 't t d )

V1

V2

V3

Through utilizing proposed dual under-sampling technique, the nonlinearity of DAC output signal is represented as narrow pulse width signal. The design effort of required TDC for quantifying pulse width would be greatly reduced; indeed, the practicability of BIST implement is enhanced. IV. EXPERIMENT RESULT

td
s (t )

sd (t )
w(t ) D (t ) W1 = x + w[1] D1
0

W2 = x + w[ 2] D2
0

W3 = x + w[3]
D3

(b)
f ( 't t d ) f ( 't )
V2

f ( t )

f ( 't t d ) f ( 't )

f ( t )
V2 V f

To validate the nonlinearity estimation, we applied the proposed BIST scheme in Fig. 2(a) to an 8-bits 200MS/s DAC. A simple counter drives the DAC to output triangular waveform with normalized amplitude Vdac and period Tdac . For 4 sample points per quantization level, we have to spread 1020 sample points in 255 quantization levels of DAC. Then, the frequency of sinusoidal carrier is designed to be: 2 t f ( ' t ) = 1.555 Vdac sin 2 255 5ns + 0.361 5ns and td = 2.5ns We can calculate the slopes of faulty signal of DAC from 1020 captured samples and then estimate 255 nonlinearity errors by the algorithm we mentioned in previous section. Fig. 3 shows the calculated slopes of faulty signal of DAC and the estimated DNL and INL with the real cases are reported in Fig. 4(a) and Fig. 4(b). We can see that the estimated nonlinearity error match well with the real cases. The maximum estimated error of DNL and INL are less than 0.2LSB and 0.35LSB respectively. The reported experiment results demonstrate that the proposed BIST structure based on dual under-sampling technique can be applied to estimate the nonlinearity error of high speed DAC accurately.
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1 15 29 43 57 71 85 99 113 127 Code 141 155 169 183 197 211 225 239 253

x
td

w
x
y

(c)

(d)

Figure. 2 (a) The fundamental concept of proposed method with dual undersampling technique. (b) The relative signals. (c) The shadow area in Fig. 2(b) of fault free case. (d) The shadow area in Fig. 2(b) of faulty case.

For the ideal fault free case in Fig. 2(c), the slope of output signal of DAC with respect to phase delay td between two carriers can be derived as:
mdac = td x m s [i ] x

, where ms [i ] is the slope of sinusoidal carrier. Because the duration between adjacent sample points is very short, the sinusoidal carrier can be regarded as combination of piece-wise linear segments. However, the quantization level of DAC is not uniform in practice. As the faulty case shown in Fig. 2(d), the displacement of cross point of carrier and DAC output signal appears on the phase difference w . We consequently express the slope of faulty signal as: df (t ) td ( x + w[i ]) = ms [i ] dt x + w[i ]

mf =

Estimated slopes (V/t)

Figure 3. The calculated slopes of faulty signal of an 8-bits 200MS/s DAC.

1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 1 15 29 43 57 71 85 99 113 Code 127 141 155 169 183

estimated

real

[4]

[5]

[6]
197 211 225 239 253

[7]

(a) [8]
0.8 0.6

estimated

real

Estimated INL (LSB)

0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 1 15 29 43 57 71 85 99 113 Code 127 141 155 169 183 197 211 225 239

[9]

S. Rafeeque K.P., V. Vasudevan, A built-in-self-test scheme for segmented and binary weighted DACs, J. of Electronic Testing, Theory & Appl., vol. 20, no. 6, pp. 623638, December 2004. V. Kerzerho et al, A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs, IEEE Design & Test of Computers, vol. 23, issue 23, pp. 234243, 2006. S.J Chang, C.L. Lee, and J.E. Chen, BIST scheme for DAC testing, Electronic Letters, vol. 38, no. 15, pp. 776777, July 2002. G. X. Chen, C.L. Lee, and J.E. Chen, A new BIST scheme based on a summing-into-timing signal principle with self calibration for the DAC, Proc. IEEE Asia Test Symp., pp. 5861, 2004. J.L. Huang, C.K. Ong, and K.T. Cheng, A BIST scheme for on-chip ADC and DAC testing, Proc. IEEE Design Automation & Test in Europe, pp. 216220, 2000. Chun Wei Lin, Sheng Feng Lin, and Shih Fen Luo, A new approach for nonlinearity test of high speed DAC, Proc. IEEE Int. Mixed-Signals, Sensors, and Systems Test Workshop, pp. 15, 2008.

Estimated DNL (LSB)

(b) Figure 4. (a)Estimated result of DNL for the 8-bits 200MS/s DAC. (b)Estimated result of INL for the 8-bits 200MS/s DAC.

V.

CONCLUSION

In this paper, an efficient BIST scheme for testing the nonlinearity error of high speed DAC is presented. Improving proposed under-sampling technique, a dual under-sampling technique modulates the output signal of DAC into two digital streams by two sinusoidal carriers. The nonlinearity error of DAC is hence converted into variation of narrow pulse width which significantly reduces the design effort on designing TDC. The experiment result shows that the estimated DNL and INL are close to the real case with the maximum estimated error are about 0.2LSB and 0.35LSB. In addition, the required operational frequency of test environment or equipment used in proposed scheme is much lower than that of DAC. This is benefit on integrating BIST design into present test process.

ACKNOWLEDGMENT The authors would like to thank National Chip Implementation Center (CIC) for technical support and chip fabrication. REFERENCES
[1] [2] J.L. Huertas, Test and Design-for-Testability in Mixed-Signal Integrated Circuits, Kluwer Academic Publishers, 2004. K. Arabi, B. Kaminska, M. Sawan, On chip testing data converters using static parameters, IEEE Trans. on VLSI System, vol. 6, no. 3, pp. 409418, 1998. J. H. Chun, H.S. Yu, and J. A. Abraham, An efficient linearity test for on-chip high speed ADC and DAC using loop-back, Proc. ACM Great Lakes Symp. on VLSI, pp. 328331, 2004.

[3]