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Chapter 6 - Introduction To Sequential Devices
Chapter 6 - Introduction To Sequential Devices
x1 xn
z1 zm
x1 xn
Combinational logic
z1 zm
y1 yr
Yr Y1
Memory
(b)
Figure 6.1
Block diagram representation: Figure 6.1 State Tables and Diagrams: the functional relationship that exists among the input, output, present state, and next state is illustrated by either the state table or the state diagram. The state diagram is a graphical representation of a sequential circuit in which the states are represented by circles and the state transitions (the transfer from the present state y to the next state Y) are shown by arrows. The state table lists the inputs across the top, the outputs along the left side, with the entries in the table being the next state and output for each input and present state.
Next state x/z Y Input/output Present state y Next state/output (a) (b) y Y/z
Figure 6.2
A B C D
Outputs: z = 0 z=1 The state diagram for this circuit is shown in Fig. 6.3
Now assume the circuit is initially in state A. If an input of x = 0 is applied the next state is D and the output is 0. Consider the application of the following input sequence to the circuit x = 0110101100
The circuit will behave as follows: present state: A D B A D B input: 0 1 1 0 1 0 next state: D B A D B B output: 0 1 0 0 1 1
B 1 B 0
A 1 A 1
C 0 C 1
C C 0 C C 1
Present state
0/1
1/0
B 1/1 0/1
D x/z (b)
Figure 6.3
State diagram
Memory Devices
Memory elements exist indefinitely in one of two possible states, 0 and 1. Binary data are stored in a memory element by placing the element into the 0 state to store a 0 and into the 1 state to store a 1. The output Q of the circuit indicates the present state of the memory. The two memory element types most commonly used in switching circuits are latches and flip-flops. Latches are devices whose excitation inputs control the state of the device. A flip-flop differs from a latch in that it has a control switch called a clock. This means a flip-flop waits for its clock signal before changing states. The final state of a flip-flop is determined by its excitation values at the time the clock signal occurs.
Device 74LS73A 7474 74LS75 7476 74111 74116 74175 74273 74276 74279
Set-reset latch
N1 N1
Q N2 (b) SR latch Q
N1
N2
(d)
Figure 6.7
NAND SR Latch
S S N1 Q S=0 S=1 Q
N2
R=0
R=1 (b)
(a)
Logic diagram
Storage mode
S Q
R
Q R
R (e)
(d)
(c)
Reduced logic
Logic symbol 1
Logic symbol 2
Figure 6.8
The operation of any latch circuit may be described using a timing diagram. The diagram shown in Fig. 6.9 shows that placing logic 1 signals on both the R and S inputs forces both outputs, Q and Q, to logic 0. When the two inputs are returned to logic 0, a race condition is created, and which state the device will assume can not be determined. Consequently, the use of the SR latch is restricted to exclude the input combination S = R = 1. If the R signal is returned to logic 0 before S, the final state of Q will be a logic 1. If S is returned to logic 0 first, the device will be reset to logic 0.
Set (a)
Reset
Set
S R Q Q
Set
Reset
Set
Figure 6.9
(b)
Delay Parameters
Every circuit output requires a nonzero amount of time to respond to changes on its input, as specified by delay parameters tPLH and tPHL . Recall that tPLH designates the delay time between an input change and a corresponding low-to-high transition of an output. tPHL is the delay between an input change and a corresponding highto-low transition. For a latch circuit the delay parameters represent the sum of the propagation delays through the gates between a given latch input and output, with separate delay parameters usually specified for each input/output pair.
For example, Fig. 6.10 illustrates the timing behavior of the SR latch of Fig. 6.7c. Following a change in S from 0 to 1, note that output Q changes from 1 to 0 after propagation delay tPHL through N1. Then the feedback signal causes the Q output to change from 0 to 1 after propagation time tPLH through N2. Thus, output Q always changes before output Q when setting an SR latch built from cross-coupled NOR gates. Therefore, tPHL from input S to output Q involves a single gate delay, whereas tPLH from input S to output Q includes two gate delays.
S R Q Q
Figure 6.10
The logical operation of the SR latch is summarized in the excitation table of Fig. 6.11a. The excitation table is simply the state table of the latch, showing the state transitions for each combination of excitation inputs. The information from the table can be represented as a state diagram, as shown in Fig. 6.11b, and plotted in K-map form, as shown in Fig. 6.11c, where the value of the next state Q* is plotted as a function of the inputs, S and R, and the present state Q. From the K-map the characteristic equation of the SR latch can be derived: Q* = S + RQ.
The characteristic equation is so called because it characterizes the operation of the latch. We can classify the latch operation into three cases:
1. S = R = 0 the state does not change 2. S = 1, R = 0 represents the set operation 3. S = 0, R = 1 represents the reset operation
SR latch characteristics
SR
Excitation inputs S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Present state Q 0 1 0 1 0 1 0 1 (a) Next state Q* 0 1 0 0 1 1 No change Reset Set Not allowed
0d 10 0 01 1
d0
SR Q 00 0 Q 1 0 1 01 0 0 11 -
S 10 1 1
Excitation table
R (c)
Figure 6.11
Gated SR Latch
Often it is desirable to use a special control signal to inhibit state changes in an SR latch while S and R are changing. This device is commonly referred to as a gated SR latch, since the control signal can be thought of as opening a gate through which signals on the S and R inputs propagate to the output. Circuit Structure: In Fig. 6.13a, a control signal C, is added to an SR latch to apply the inputs S and R. The two AND gates apply the control signal S and R during time intervals when the enable signal C is logic 1. When C is logic 0, the inputs are held in the S = R = 0 state.
So the operation of the latch is as follows: when C = 0, no change occurs when C = 1, the SR excitation table of Fig. 6.11a and the characteristic equation describe its function. If the AND gates are changed to NAND gates and cross-coupled NAND gates are used for the SR latch, the circuit of Fig. 6.13b results. The NAND gate implementation of the gated SR latch is shown in Fig. 613.c. The generic logic symbol for the gated SR latch is shown in Fig. 6.13d.
Gated SR Latch
S
Figure 6.13
S
S Q
C R (a) Q
C R (b) Q
S C S C Q R (c) C R
(d)
S
Q
C R Q
logic symbol
Characteristic Equation: The complete excitation table and state diagram of the gated SR latch are given in Figs. 6.14a and b. From the excitation table the characteristic equation is derived: Q* = SC + RQ + CQ Note that when C = 0 this equation reduces to Q* = Q which means that the present state is held. When C = 1 the equation becomes: Q* = S + RQ, the characteristic equation of the simple SR latch, and thus the latch is enabled.
Excitation table
State diagram
Figure 6.14
Delay Latch
When storing data, a memory elements excitation input is simply the data to be stored. A device (which is called a delay latch or D latch) is needed that transfers a logic value on its excitation input D into the cross-coupled storage cell of a latch. The logic symbol of the D latch is shown in Fig. 6.15a. Such a device can be created from a gated SR latch, by assigning S = D and R = D. The D latch excitation table and state diagram is shown in Figs. 6.16 a and b. A NAND implementation of the D latch is shown in 6.15b and NOR is shown in 6.15c.
S Q
C
C (a) Q
Q R (b) SR latch
Logic symbol
NAND implementation
S Q
C Q R SR latch
Figure 6.15
(c)
NOR implementation
D Latch Characteristics
Next state Q* 0 1 0 0 1 1 Hold Store 0 Store 1
Enable input C 0 0 1 1 1 1
Excitation table
Figure 6.16
State diagram
D Latch (continued)
Characteristic equation: this equation can be derived from that of the gated SR latch by substituting D for S and D for R: Q* = DC + CQ When the enable signal is low, (C = 0), the equation reduces to Q* = Q, meaning the latch is placed in hold mode (no change) operating mode with the latch holding the last value of D that was entered. When the enable signal is high (C = 1), Q* = D, the excitation input D is gated directly to output Q (gated or enabled mode). Fig. 6.17 illustrates the timing diagram for D latch operation.
Figure 6.17
D Latch (continued)
Timing Constraints : To ensure that a specific value on excitation input D will determine the final state of the latch, D must not be allowed to change too near the time at which the enable signal makes its transition from high to low. Set up time: denoted tsu is defined as the period of time immediately preceding the enable signal transition during which the excitation input must be stable. That is, the excitation input must be set up at least tsu prior to the enable signal transition and should not change until well after the transition.
D Latch (continued)
Hold time : denoted th is defined as the period of time immediately following the enable signal transition during which D should not change. Therefore, the excitation input must be held constant for at least th following the enable signal transition to ensure the correct value has been latched. Setup and hold times are illustrated in Fig. 6.18 Note the two constraint violations: - the change in D from 0 to 1 too close to the clock edge represents a setup time violation - the change in D from 1 to 0 too soon after the clock edge may result in an unpredictable state.
th
th tsu
tsu
tw
Unknown state
Figure 6.18
Flip-Flops
The latch circuits presented thus far are not appropriate for use in synchronous sequential logic circuits. The possibility of two cascaded combinational circuits feeding each other, generating oscillations and unstable transient behavior can be controlled by using a special timing control signal called a clock. The clock can then be used to restrict the times at which the states of the memory elements may change thus preventing the unstable behavior just described.
Master-Slave SR Flip-Flops
One method to prevent unstable behavior is to employ two latches in a master-slave configuration as shown in Fig. 6.21a. When the clock signal C is low, the master latch is in the gated mode and slave is in the hold mode. Changes on the excitation input signal S and R are gated into the master latch while the slave latch ignores any changes on its inputs. When the clock changes to logic 1, the two latches exchange roles. The slave latch enters the gated mode, sending the output of the master latch to the flip-flop output Q, while the master latch enters the hold mode.
Master-slave SR flip-flop
Master QM S S C R R Q Q S
Slave Q Q
C R Q Q
C (clock)
S C R
Figure 6.21
hold
hold
hold
hold
S R
QM Q
S and R may not change
( c) Timing behavior
C low pulse width C high pulse width (master enabled) (slave enabled)
Figure 6.21
S 0 0 0 0 1 1 1 1
R 0 0 1 1 0 0 1 1
Q 0 1 0 1 0 1 0 1
Q* = S + RQ
Figure 6.22
Master-Slave D Flip-Flops
A master-slave D flip-flop can be built from two D latches as shown in Fig. 6.23a. This flip-flop operates in the same manner as the SR version; the master latch is gated when the clock is low and the slave, when the clock is high. The logic symbol for this pulse-triggered device indicates that the outputs change on the positive edge of a pulse on the clock signal (Fig. 6.23b). The overall behavior of the D flip-flop output Q can be summarized by noting that Q will assume the value of D on the rising edge of the clock C. Therefore, the characteristic equation for a master-slave D flip-flop is : Q* = D
Master-Slave D Flip-Flop
Master D D Q QM D
Slave Q Q D Q
Q C Q (b)
C (clock) (a)
Figure 6.23
D 0 0 1 1
Q 0 1 0 1
Q* 0 0 1 1 Store 0 Store 1
0 0
D 1 1 0
Enabled: C D
QM Q = QS
Figure 6.24
Master-Slave JK Flip-Flops
The JK operates as an SR flip-flop whose inputs are assigned J = S and K = R. However, whereas the S = R = 1 combination is not allowed, the JK uses this special case to incorporate a very useful mode of operation. The additional feature of the JK device is that it state toggles, that is changes from 0 to 1 or from 1 to 0 when J = K = 1. Examination of the state diagram, shown in Fig. 6.25b, indicates that the JK flip-flop will change from the 0 state to the 1 state with an input of J = 1 and K = 0 or J = 1 and K = 1 (toggle). This means that a logic 1 on J will force the device into the 1 condition no matter what value is placed on K. So K is a dont-care in this case.
J 0 0 0 0 1 1 1 1
K 0 0 1 1 0 0 1 1
Q 0 1 0 1 0 1 0 1
Q* 0 1 0 0 1 1 1 0 Hold Reset
0d 0
JK 1d 1 d1
d0
Set Toggle
(b) State diagram
JK Q 0 Q 1 00 0 1 01 0 0 K 11 1 0
J 10 1 1
( c) K-map for Q*
Figure 6.25
JK Flip-Flops (continued)
By plotting the next state Q* on a K-map, as shown in Fig 6.25c, the characteristic equation of the JK flip-flop can be derived: Q* = KQ + JQ From this equation, the logic diagram for the flip-flop can be derived as presented in Fig. 6.26a. The logic symbol for this device is shown in Fig. 6.26 b. Note that the clock input signal is inverted within the device itself so that the slave will change on the falling edge of the clock.
KQ K J JQ C (b) (a) C Q Q Q* D Q Q J C K Q Q
Logic diagram
Logic symbol
Figure 6.26
Figure 6.27 shows the logic symbol of the SN7476. This device packages two flip-flops that operate in the manner displayed in Fig. 6.26. Included in the configuration are asynchronous set signals PRE and reset signals CLR. The PRE and CLR signals override the operation of the pulse-triggered inputs J, K and CLK. This means that if CLR = 0 then the state Q* goes to 0, or if PRE = 0 the state Q* sets to 1, independent of the values of the clock and the excitation inputs.
Figure 6.27
Edge-triggered D Flip-Flops
All the pulse-triggered flip-flops discussed previously, require both a rising and falling edge on the clock for proper operation. Another approach is to design the flip-flop circuitry so that it is sensitive to its excitation inputs only during rising or falling transitions of the clock. A circuit with this design is called positive edge triggered if it responds to a 0 to 1 clock transition, or negative edge triggered if it responds to a 1 to 0 clock transition. The edge-sensitive feature eliminates unstable transients by drastically reducing the period during which the input excitation signals are applied to the internal latches.
Q Q
Q Q
CLR
CLR
(b) generic logic symbol
'74 1PRE 1CLK 1D (4) (3) C1 (2) (1) 1D R (9) 2Q (8) 2Q (6) 1Q S
CLK
(5) 1Q
Figure 6.28
2CLR
Outputs Q H L H H L Q0 Q L H H L H Q0 Mode Set Clear Not allowed Clocked operation Clocked operation Hold
Figure 6.29
To ensure proper operation of any edge-triggered flip-flop, the excitation inputs should not change immediately before or after the clock transition. The value of D for the SN7474 is sampled and transferred to the flipflop output Q at the exact instant the clock reaches its threshold value. One should always make sure that the input is either logic 1 or 0 at this instant in time so that the flip-flops output Q will be the value planned in the system design. Fig.6.30
Value (ns) 25 40 25 40 25 40
th
CLR
Figure 6.30
( c) timing constraints
T Flip-flops
A common building block used in sequential logic circuits that counts pulses on a signal line is the T flip-flop. The T flip-flop has only one excitation input signal T, as shown on the logic symbol for the device pictured in Fig. 6.33a. The function of this device is to change (toggle) its state upon each negative-going transition of its excitation input signal, as shown in the excitation table and state diagram in Figs. 6.34a and b. Therefore, the characteristic equation of the edge-triggered T flip-flop is simply: Q* = Q
Negative-Edge-Triggered T Flip-Flop
VC
C
PRE Q T Q CLR J
PRE Q C K CLR Q
(a)
Logic symbol
(b)
Functional equivalent
Figure 6.33
0 T Q 0 1 (a)
Excitation table
T 1 0 1 (b)
State diagram
0 1
Q* 1 0 Toggle Toggle
Q* = Q
Figure 6.34
Clocked T Flip-flops
Some versions of the T flip-flop operate under clock pulse control, as shown in Fig. 6.35a. In this case, the flip-flop toggles if T = 1 when the clock makes a high-to-low transition and holds its present state if T = 0 when the flip-flop is clocked. The operation of a clocked T flip-flop is described by the excitation table given in Fig. 6.36. The equivalent circuit of the clocked T flip-flop, shown in Fig. 6.35b, is simply a JK flip-flop with inputs J = K = T, and its C input driven by the clock signal. Another variation of the clocked T flip-flop is shown in Fig. 6.37a.
Clocked T Flip-Flop
PRE T C CLR Q Q T J
PRE Q C K CLR Q
(a)
Logic symbol
(b)
Functional equivalent
Figure 6.35
T 0 0 1 1
Q 0 1 0 1
Q* 0 Hold 1 1 Toggle 0
Q* = TQ + TQ
Figure 6.36
Tc Clock T
Clock Tc T Q Q Dt
Figure 6.37
Device SR latch Gated SR latch D latch SR flip-flop D flip-flop JK flip-flop T flip-flop (edge-triggered) T flip-flop (clocked)