DEPARTMENT OF ELECTRONICS AND COMMUNICATION INTERNAL TEST III Degree & Branch : M.E VLSI Date : 07.05.

2013 Subject :CAD for VLSI circuits Semester : II Part A 10 * 2 = 20 Answer All Questions

DEPARTMENT OF ELECTRONICS AND COMMUNICATION INTERNAL TEST III Degree & Branch : M.E VLSI Date : 07.05.2013 Subject :CAD for VLSI circuits Semester : II Part A 10 * 2 = 20 Answer All Questions

1. What is Switching Level Timing Simulator? 2. What is meant by Column Dominance? 3. What is the function of simulation Kernal? 4. Define Logic Synthesis. 5. Give the various delay modeling and define delay model. 6. State transformation involved in size reduction of an ORDD into ROBDD. 7. Define: Variable ordering. 8. Differentiate the inter and intra iteration parallelism. 9. Distinguish between DFG and SFG . 10. Write down the purpose of system clock and tell about multi cycle operation.
Part B 3*10=30

1. What is Switching Level Timing Simulator? 2. What is meant by Column Dominance? 3. What is the function of simulation Kernal? 4. Define Logic Synthesis. 5. Give the various delay modeling and define delay model. 6. State transformation involved in size reduction of an ORDD into ROBDD. 7. Define: Variable ordering. 8. Differentiate the inter and intra iteration parallelism. 9. Distinguish between DFG and SFG . 10. Write down the purpose of system clock and tell about multi cycle operation.
Part B 3*10=30

11. Explain the internal representation for second order FIR filter DFG for scheduling, assignment and allocation.(10) 12. Explain about complier driven and event driven simulation.(10) 13. Explain principles of ROBDD(3). Explain in detail how ROBDD is used for Logic verification and combinatorial Optimization.(7)

11. Explain the internal representation for second order FIR filter DFG for scheduling, assignment and allocation.(10) 12.Explain about complier driven and event driven simulation.(10) 13. Explain principles of ROBDD(3). Explain in detail how ROBDD is used for Logic verification and combinatorial Optimization.(7)