9

XC9536 In-System Programmable CPLD

1 1*

December 4, 1998 (Version 5.0)

Product Specification

Features
5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages

Power Management
Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9536 device.

erform High P

ance

(83)

Typical ICC (mA)

(50)

(50)

ower Low P
(30)

Description
The XC9536 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of two 36V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 for the architecture overview.
0 50 Clock Frequency (MHz) 100
X5920

Figure 1: Typical ICC vs. Frequency For XC9536

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

3 JTAG Port 1 JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18

Function Block 1 Macrocells 1 to 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

X5919

Figure 2: XC9536 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL
Warning:

Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm)

Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260

Units V V V C C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operating Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage

Note 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Data Retention Program/Erase Cycles Parameter Min 20 10,000 Max Units Years Cycles

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol VOH Parameter Output high voltage for 5 V operation Test Conditions Min 2.4 2.4 0.5 0.4 10.0 10.0 10.0 30 (Typ) Max Units V V V V A A pF mA IOH = -4.0 mA VCC = Min Output high voltage for 3.3 V operation IOH = -3.2 mA VCC = Min Output low voltage for 5 V operation IOL = 24 mA VCC = Min Output low voltage for 3.3 V operation IOL = 10 mA VCC = Min Input leakage current VCC = Max VIN = GND or VCC I/O high-Z leakage current VCC = Max VIN = GND or VCC I/O capacitance VIN = GND f = 1.0 MHz Operating Supply Current VI = GND, No load (low power mode, active) f = 1.0 MHz

VOL

IIL IIH CIN ICC

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC9536-5 5.0 3.5 0.0 4.0 100.0 100.0 0.5 3.0 7.0 5.0 5.0 9.0 9.0 4.0 4.0 100.0 100.0 0.5 3.0 7.0 5.0 5.0 9.0 9.0 4.0 3.5 0.0 4.0 83.3 83.3 0.5 4.0 8.5 5.5 5.5 9.5 9.5 4.5 XC9536-6 6.0 4.5 0.0 4.5 66.7 66.7 2.0 4.0 10.0 6.0 6.0 10.0 10.0 5.5 XC9536-7 XC9536-10 XC9536-15 7.5 6.0 0.0 6.0 55.6 55.6 4.0 4.0 12.0 11.0 11.0 14.0 14.0 10.0 8.0 0.0 8.0 15.0 Min Max Min Max Min Max Min Max Min Max Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

Note: 1. fCNT is the fastest 16-bit counter frequency available.

fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Min Max Min Max Min Max Min Max Min Max 1.5 1.5 4.0 5.0 2.0 0.0 3.0 1.0 5.5 0.5 2.5 1.0 0.5 6.0 5.0 1.0 9.0 6.0 0.8 3.5 5.0 1.0 9.0 6.0 0.8 3.5 2.5 1.0 0.5 6.0 7.5 2.0 10.0 8.0 1.0 4.0 1.5 1.5 4.0 5.0 2.0 0.0 3.0 1.0 5.5 1.5 1.5 3.0 0.5 6.5 10.0 2.5 11.0 9.5 1.0 4.5 2.5 1.5 4.5 5.5 2.5 0.0 3.0 2.0 4.5 0.5 2.5 3.5 0.5 7.0 10.0 3.0 11.5 11.0 1.0 5.0 3.5 2.5 6.0 6.0 3.0 0.0 3.0 2.5 3.5 1.0 3.5 4.5 0.5 8.0 4.5 3.0 7.5 11.0 4.5 0.0 2.5 3.0 5.0 3.0 Units

Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feeback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD XC9536 I/O Pins

Function Macrocell Block PC44 VQ44 CS48 BScan Notes Order Function Macrocell Block PC44 VQ44 CS48 BScan Notes Order

1 1 2 1 2 3 1 3 5 1 4 4 1 5 6 1 6 8 1 7 7 1 8 9 1 9 11 1 10 12 1 11 13 1 12 14 1 13 18 1 14 19 1 15 20 1 16 22 1 17 24 1 18 Note: [1] Global control pin

40 41 43 42 44 2 1 3 5 6 7 8 12 13 14 16 18

D6 C7 B7 C6 B6 A6 A7 C5 B5 A4 B4 A3 B2 B1 C2 C3 D2 -

105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54

[1] [1] [1]

2 1 1 2 2 44 2 3 42 2 4 43 2 5 40 2 6 39 2 7 38 2 8 37 2 9 36 2 10 35 2 11 34 2 12 33 2 13 29 2 14 28 2 15 27 2 16 26 2 17 25 2 18 Note: [1] Global control pin

39 38 36 37 34 33 32 31 30 29 28 27 23 22 21 20 19 -

D7 E5 E6 E7 F6 G7 G6 F5 G5 F4 G4 E3 F2 G1 F1 E2 E1 -

51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

[1] [1] [1]

XC9536 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND No Connects PC44 5 6 7 42 40 39 17 15 30 16 21,41 32 23,10,31 VQ44 43 44 1 36 34 33 11 9 24 10 15,35 26 17,4,25 CS48 B7 B6 A7 E6 F6 G7 A1 B3 G2 A2 C1,F7 G3 A5, D1, F3 C4, D3, D4, E4

December 4, 1998 (Version 5.0)

XC9536 In-System Programmable CPLD

Ordering Information XC9536 -5 PC 44 C

Device Type Speed Temperature Range Number of Pins Package Type
Speed Options -15 -10 -7 -6 -5 15 ns pin-to-pin delay 10 ns pin-to-pin delay 7.5 ns pin-to-pin delay 6 ns pin-to-pin delay 5 ns pin-to-pin delay Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier (PLCC) VQ44 44-Pin Thin Quad Pack (VQFP) CS48 48-Pin Chip Scale Package (CSP) Temperature Options C = Commercial (0C to +70C) I = Industrial (40C to +85C)

Component Availability
Pins Type Code 15 10 7 6 5 Plastic PLCC PC44 C,I C,I C,I C C 44 Plastic VQFP VQ44 C,I C,I C,I C C 48 Plastic CSP CS48 C C C

XC9536

C = Commercial (0C to +70C), I = Industrial (40C to +85C)

Revision Control
Date 6/3/98 11/2/98 12/04/98 Reason Revise datasheet to reflect new CSP package pinouts & ordering code. Revise datasheet to reflect new AC characteristics and Internal Timing Parameters. Revise datasheet to remove PCI compliancy statement and remove tLF.

December 4, 1998 (Version 5.0)