MUNCHEN TECHNISCHE UNIVERSITAT Lehrstuhl f ur Integrierte Systeme

Chip Multicore Processors Tutorial 6

June 5, 2013

Task 6.1: Cache Misses

Explain the 3 Cs of cache misses. How do they relate?

Task 6.2: Multilevel Caches and separated instruction and data caches
In this tutorial we focus on the impact of the cache hierarchy on the performance of the system. a) You have a simple system with a processor core, no caches and an external memory. The on-chip interconnect between the processor core and the memory requires 3 + x cycles for the transfer of x data words. The memory requires 46 cycles to access data. By using a benchmark you nd that on average each fth instruction accesses data. Your processor has a CPI of 1.8. What is the CPI of your whole syste? b) You are using a direct-mapped cache of 32 kB and with cache blocks of 4 words (each 32 bit). The cache is accessed in one clock cycle. For your application you measure a miss rate of 5%. How does the CPI change? c) Impressed by the improvement you add a second instance of this cache. How does the CPI change? d) Alternatively, you can use two other caches, each of total 256 kB. One of the caches is 2-way associative and has an access time of 4 cycles. The other cache is 4-way associative and has an access time of 6 cycles. The global miss rate is 4% for the rst cache and 3% for the second cache. Which cache should be chosen? e) Explain the meaning of spatial and temporal locality in the context of instructions and data.

f) Based on your previous ndings, exchange the level one cache with separate caches for instructions and data. The miss rate for instructions is 3% and for data 8%. Use the level 2 cache from d) and calculate the CPI value.