Intel 810 Celeron Document For Troubleshooting

8
INTEL(R) CELERON(TM) PROCESSOR (PPGA)/INTEL(R) 810 CHIPSET UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS
REVISION 1.3
D D
TITLE
PAGE
Cover Sheet Block Diagram 370-Pin Socket GTL Termination Clock Synthesizer GMCH Frame Buffer DIMM Sockets ICH0 FWH Super I/O PCI Connectors ATA33 IDE Connectors USB Connectors Parallel Port Serial/Game Ports Keyboard/Mouse/Floppy Disk Digital Video Out (TBD) Graphics Connectors AC97 Riser Connector LAN System Voltage Regulators Processor Voltage Regulator System Pullup Resistors and Unused Gates Decoupling
1 2 3,4 5 6 7,8,9 10 11,12 13,14 15 16 17,18 19 20 21 22 23 24 25 26 27,28 29 30 31,32 33 34,35
** PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE
TH ESE SC HEM AT IC S ARE PRO VIDED AS IS W ITH N O W ARRANT IES W HATSO EVER, INCLUDIN G ANY W AR RANT Y O F M ERCH ANT ABILIT Y, FIT NESS FO R ANY PART ICULAR PUR PO SE, O R ANY W ARR ANT Y O THERW ISE ARISING O UT O F PR O PO SAL, SPECIFIC AT IO N O R SAM PLES. Inform ation in this docum ent is provided in connection with Intel products. No license, express or im plied, by estoppel or otherwise, to any intellectual property rights is granted by this docum ent. Except as provided in Intel's T erm s and Conditions of Sale for such products, Intel assum es no liability whatsoever, and Intel disclaim s any express or im plied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, m erchantability, or infringem ent of any patent, copyright or other intellectual property right. Intel products are not intended for use in m edical, life saving, or life sustaining applications. Intel m ay m ake changes to specifications and product descriptions at any tim e, without notice. The Intel Celeron TM processor and Intel 810 chipset m ay contain design defects or errors known as errata which m ay cause the product to deviate from published specifications. Current characterized errata are available on request. Copyright Intel Corporation 1998. *Third-party brands and nam es are the property of their respective owners.
B
TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
REV:
COVER SHEET
DRAWN BY:
R
1.3
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION LAST REVISED: PROJECT: INTEL(R) 810 CHIPSET SHEET:
PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD
FOLSOM, CALIFORNIA 95630 2
5-26-1999_17:09
1
OF
40
Block Diagram
D
Device Table
VRM 370-Pin Socket Processor DATA CTRL ADDR ADDR Clock
Term DATA CTRL
Display Cache Memory GMCH Digital Video Out Device
2 DIMM Modules
IDE Primary IDE Secondary
UltraDMA/33 PCI CNTRL ICH0 PCI ADDR/DATA PCI CONN 1 PCI CONN 2 PCI CONN 3
USB Port 1 USB Port 2
USB
AMC97 Audio/Modem
B
AC97 Link
PCI CNTRL PCI ADDR/DATA SIO LAN
REFERENCE DESIGNATOR U12 U16,U17 U15 U3 U1 U2 U14 U7 U13 U8,U9 U10 U6 U18 U4 U5 U11 VR2,VR3 VR4 VR1 VR5
DEVICE TYPE 74lvc14a gd75232 lpc47b27_a 74lvc06a ck-whitney 82810-DC100 82801AB sii-dfp 82559 1x16sdram 74lvc08a qst3384 93c46 74ls132 74lvc07a 74lvc07a lt1587ad lt1117_3 ltc1753 lt1585ad
GATES USED A,B,C,D
A,B,C,D
A,B
A,B A,B,C A,B,C
SHEET NUMBER 32 22 16 29,32 6 7,8,9 13,14 24 27 10 32 25 27 29,32 29,31 19,31 29 29 30 29
LPC Bus
FirmWare Hub
Keyboard Mouse
Floppy
Parallel Serial 1
Game Conn
REV:
BLOCK DIAGRAM
DRAWN BY:
R
1.3
INTEL CORPORATION
11-23-1998_13:43
1
OF
40
7
VCCVID
370PGA Socket Part 1

5,7 HD#[63:0] HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 W1 T4 N1 M6 U1 S3 T6 J1 S1 P6 Q3 M4 Q1 L1 N3 U3 H4 R4 P4 H6 L3 G1 F8 G3 K6 E3 E1 F12 A5 A3 J3 C5 F6 C1 C7 B2 C9 A9 D8 D10 C15 D14 D12 A7 A11 C11 A21 A15 A17 C13 C25 A13 D16 A23 C21 C19 C27 A19 C23 C17 A25 A27 E25 F16
AM12
AM16
AM20
AM24
AM28
AM32
AH32
AK34
AJ13
AJ17
AJ21
AJ25
AJ29
AM4
AM8
AK2
AB2
AE5
AA5
D20
D24
D28
R32
AF2
B10
E13
B14
E17
B18
B30
V32
B26
F22
F26
F30
AJ5
AJ9
Z32
W5
C3
N5
D6
P2
K2
E5
S5
B6
E9
T2
F4
F2
J5
X2
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61
HA#[31:3]
VCC52
5,7
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21
AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 AL35 AM36 AL37 AJ37 AH26 AH22 AK28 AK18 AH16 AH18 AL19 AL17 AH20 AH4 A29 A31 A33 AA33 AA35 AC1 AC37 AF4 AK16 AK24 AK30 AL11 AL13 AL21 AN11 AN13
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 VID[3:0] VID0 VID1 VID2 VID3 RS#[2:0] RS#0 RS#1 RS#2 HREQ#[4:0] HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 7 7 30
HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58
370-Pin Socket Part 1
HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 VID0 VID1 VID2 VID3 RS#0 RS#1 RS#2 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 RSRVD1 RSRVD2 RSRVD3 RSRVD4 RSRVD5 RSRVD6 RSRVD7 RSRVD8 RSRVD9 RSRVD10 RSRVD11 RSRVD12 RSRVD13 RSRVD14 RSRVD15 RSRVD16 RSRVD17
HD#59 HD#60 HD#61 HD#62 HD#63
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
HD#63
GND9
HD#62
GND50
RSRVD18
REV:
AL3
B12
B16
B20
E11
E15
E19
B24
D26
B28
E7
V2
Y5
B4
Q5
G5
B8
AG5
AJ11
AJ15
AJ19
AJ23
AJ27
AM18
AM34
AM22
AM10
AM14
AM30
AM26
AH2
AD2
AM2
AC5
AK4
AM6
D30
D18
D22
H2
D2
L5
M2
D4
U5
F20
AJ7
F24
F28
Z2
370-PIN SOCKET, PART 1

DRAWN BY:
R
1.3
INTEL CORPORATION
PLATFORM COMPONENTS DIVISION LAST REVISED: PROJECT: INTEL(R) 810 CHIPSET SHEET: OF
11-23-1998_13:44 3
1
40
5
VTT1_5 4,33 VCMOS VCC2_5
4
2
VCC2_5
370PGA Socket Part 2

VTT1_5 VCMOS
4,33 VCMOS
GTLREF
ITP Test Port Option
4,33
VCCVID
R9 220
RP2 R8 1K CPURST# R_TCK R_TMS

11 13 15 17 19 21 23 25 27
R7 AD36 AH36 AD32 AH24 AB36 AK12 AK22 AB34 H32 R36 H36 D36 D32 E33 X34 P34 K34 B34 B22 V36 K32 Y35 Z36 F18 T34 F34 F14
D
JP1 M32 R6 K4 V6 330
1 2 3 4
J2
2
R1 R2 0K
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VREF0
VREF1
VREF2
VREF3
VREF4
VREF5
VREF6
32 4 4
DBRESET# 240
V_CMOS
VREF7
VCC75
V1_5
V2_5
4,5,7
ITP_RST 1
R_DBRST# 3 5 7
X2
AA37
AF34
150
AD6
4 6 8 10 12 14 16 18 20 22 24 26 28 30 R_ITPRDY#
JP1 is a Test Option Only. AH14 AN17 AN25 AN19 AK20 AN27 AL23 AL25 AL27 AN31 AE37 AJ33 AN29 AL31 AL29 AH28 AE33 AG35 AH30 AJ35 M36 L37 AG33 AC35 AG37 AE35 W33 U33
PLL1 PLL2
TDI TDO TRST# 4 ITPREQ# 4 R_TCK R_TMS R4 47 R3 47

TCK
AN35 AN37 AN33 AL33

TMS AK32
TDI TDO TRST# TCK TMS PREQ# PRDY# BP2# BP3# BPM0# BPM1# RSRVD19 RSRVD20 RSRVD21 RSRVD22 RSRVD23 RSRVD24 RSRVD25 RSRVD26 RSRVD27 RSRVD28 RSRVD29 RSRVD30 RSRVD31 RSRVD32 RSRVD33 RSRVD34 RSRVD35 RSRVD36 RSRVD37 RSRVD38 RSRVD39 PICD0 PICD1 PICCLK BCLK PWRGOOD RESET# EDGCTRL CPUPRES# GND51 GND52 GND53 GND54 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80
BNR# BPRI# TRDY# DEFER# LOCK# DRDY# HITM# HIT# DBSY# ADS# FLUSH# BSEL#
BNR# BPRI# HTRDY# DEFER# HLOCK# DRDY# HITM# HIT# DBSY# HADS#
5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7
ITP_PON9
J37 A35 G33 E37 C35 E35 AN15 AN21 AN23 B36 C29 C31 C33 E23 E29 E31
4,5 R21 240 ITPRDY# 4,5
ITPRDY#
ITPCLK
29
FREQSEL BR0#
6,9 5
370-Pin Socket Part 2
BR0# THRMDP THRMDN THERMTRIP# A20M# STPCLK# SLP# SMI# LINT0/INTR LINT1/NMI INIT# FERR# IGNNE# IERR# PLL1 PLL2
A20M# STPCLK# CPUSLP# SMI# INTR NMI INIT# FERR# IGNNE#
13,33 13,33 13,33 13,33 13,33 13,33 13,15,33 13,33 13,33 VCCVID L22
VTT1_5
F10 G35
GTLREF Generation Circuit

R102 75 1%
G37 L33 N33
Use 0603 Packages and distribute within 500 mils of Mendocino GTLREF Inputs (1 cap for every 2 inputs). GTLREF
4
N35 N37 Q33 Q35 Q37 S33 13,33 13,33 6 6 VCCVID 32 4,5,7 R76 51 APICD0 APICD1 APICCLK_CPU CPUHCLK PWRGOOD CPURST#
EDGCTRL
C123
2
+ 1
B
R104 150 1% C206 0.1UF C209 0.1UF C204 0.1UF C207 0.1UF
RSRVD40 RSRVD41 RSRVD42 RSRVD43 RSRVD44 RSRVD45 RSRVD46 RSRVD47 RSRVD48 RSRVD49 RSRVD50 RSRVD51 RSRVD52
S37 U35 U37 V4 W3 W35 X6 Y1 E21 E27 R2 S35 X2
33UF 20%
4.7UH VCC3_3
J35 L35 J33 W37 AK26 X4 AG1 C37
R171 220
VCOREDET SLEWCTRL RTTCTRL 33 33
VCMOS Decoupling
VCMOS
4,33
Place 0603 Package Near VCMOS Processor Pin. C6
H34
D34
R34
M34
X36
X32
P32
B32
V34
P36
K36
A37
AL1
Y37
AF32
AB32
AK36
AF36
Z34
AH34
AD34
AC33
R5 Do Not Stuff C114 C114 Place Site w/in 0.5" of clock pin (W37).18PF 680
0.1UF
AJ31
AJ3
AN3
Y33
T32
F32
T36
F36
REV:
370-PIN SOCKET, PART 2

DRAWN BY:
R
1.3
INTEL CORPORATION
5-26-1999_17:09
1
OF
40
GTL Termination
VTT1_5 VTT1_5 VTT1_5 VTT1_5
RP19
1 2 3 4 8 7 6 5
RP6
HA#17 HA#22 HA#31 HA#19 HA#[31:3]
1 8 7 6 5
RP22
BPRI# HREQ#4 HLOCK# RS#1 4,7 3,7 4,7 3,7
1 2 3 4 8 7 6 5
RP38
HD#15 HD#1 HD#0 HD#6
1 2 3 4 8 7 6 5
HD#[63:0] HD#54 HD#55 HD#52 HD#40
3,7
3,7
2 3 4
56 RP18
1 2 3 4 8 7 6 5
56 RP9
HA#18 HA#21 HA#25 HA#10
1 2 3 4 8 7 6 5
56 RP23
HTRDY# RS#0 DRDY# DBSY# 4,7 3,7 4,7 4,7
1 2 3 4 8 7 6 5
56 RP33
HD#8 HD#5 HD#9 HD#4
1 2 3 4 8 7 6 5
HD#56 HD#61 HD#62 HD#46
56 C
1 2 3 4
56 RP5
1 8 7 6 5 8 7 6 5
56 RP35
HITM# HIT# RS#2 HADS# 4,7 4,7 3,7 4,7
1 2 3 4 8 7 6 5
56 RP32
HD#16 HD#23 HD#21 HD#24
1 2 3 4 8 7 6 5
RP8
HA#15 HA#12 HA#3 HA#6
HD#60 HD#50 HD#53 HD#58
2 3 4
56 56 RP20
1 2 3 4 8 7 6 5 1
56 RP24
8 7 6 5
56 RP36
8 7 6 5
RP10
HREQ#0 DEFER# HREQ#3 HREQ#2 HA#30 HA#24 HA#20 HA#23 3,7 4,7 3,7 3,7
1 2 3 4 2 3 4
HD#3 HD#12 HD#10 HD#17
1 2 3 4
8 7 6 5
HD#57 HD#63 HD#59 HD#48
56 RP12
1 2 3 4 8 7 6 5 1
56 RP3
8 7 6 5
56 RP26
ITPRDY# 4
1 2 3 8 7 6 5
56 RP39
HD#30 HD#7 HD#11 HD#20
1 2 3 4 8 7 6 5
HD#47 HD#27 HD#44 HD#45
HA#28 HA#13 HA#16 HA#5
2 3 4
BR0#
56 56 B
1 2 3 4
56 RP25
1 8 7 6 5
56 RP37
HD#13 HD#18 HD#14 HD#2
1 2 3 4 8 7 6 5
RP7
8 7 6 5
HD#49 HD#51 HD#41 HD#42
HA#9 HA#11 HA#7 HREQ#1 3,7
2 3 4
56 RP11
1 2 3 4 8 7 6 5 1
56 RP43
8 7 6 5
56 RP40
HD#31 HD#32 HD#25 HD#26
1 2 3 4 8 7 6 5
HD#36 HD#22 HD#43 HD#34
HA#8 HA#4 BNR# HA#14 4,7
2 3 4
56 56 RP21
1 2 3 4 8 7 6 5 1
56 RP42
8 7 6 5
RP41
HD#29 HD#19 HD#35 HD#33
1 2 3 4
8 7 6 5
HD#39 HD#37 HD#38 HD#28
CPURST# HA#26 HA#29 HA#27
4,7
2 3 4
A 56
56
56
REV:
GTL TERMINATION
DRAWN BY:
R
1.3
INTEL CORPORATION
PROJECT: INTEL(R) 810 CHIPSET SHEET:
PLATFORM COMPONENTS DIVISION LAST REVISED:
11-23-1998_13:44
1
OF
38
4
VCC3_3
Clock Synthesizer
C55 VCC3_3
L13 1
L17 USBV3 1 2
C50 0.1UF
L16
22UF
VCC3_3
D
1
2 PCIV3 MEMV3
C158
C38
C37 .001UF
C39
C40
C386
C388
C385 .001UF
C387 0.1UF
C60 .001UF
C63 0.1UF
C64 .001UF
C61 0.1UF
2
C48
22UF
0.1UF
0.1UF
.001UF
0.1UF
.001UF
22UF
Notes:
- Place all decoupling caps as close to VCC/GND pins as possible - PCI_0/ICH pin has to go to the ICH. (This clock cannot be turned off through SMBus)
10 21 27 33 38
VDD3_3[0] VDD3_3[1] VDD3_3[2] VDD3_3[3] VDD3_3[4] VDD3_3[5] VDD3_3[6] VDD3_3[7]
R41
SEL1_PU
8.2K
- CPU_ITP pin has to go to the ITP. It is the only CPU CLK that can be shut off through the SMBUS interface.
U1
C51 12PF Y1
XTAL 2
44
XTAL_IN
XTAL_IN
C
16 14 SIO_CLK14 ICH_CLK14 R184 10 R48 10 14 8 13 16 17 17 VCC3_3 18 27 15
2 L18
14.318MHZ
XTAL_OUT
APIC REF
APIC_0 APIC_1
55 54 52 50 49 46 45 43 42 40 39 37 36 34 32 31 30 29 28
APIC_0 APIC_1
R34 33
APICCLK_CPU R25 33 33 APICCLK_ICH CPUHCLK R35 33 GMCHHCLK ITPCLK MEMCLK0 MEMCLK1 MEMCLK2 MEMCLK3 MEMCLK4 MEMCLK5 MEMCLK6 MEMCLK7 DCLK_WR CK_PWRDN# CK_SMBCLK CK_SMBDATA FREQSEL VCC2_5 MEMCLK[7:0]
4 13 4 7 4 11,12
C49 12PF REFCLK ICH_3V66 GMCH_3V66 R49 22 PCLK_0/ICH PCLK_1 PCLK_2 PCLK_3 PCLK_4 PCLK_5 PCLK_6 R50 33 R52 33 R51 33 R42 22
4 1 7 8 11 12 13 15 16 18 19 20 25 26
XTAL_OUT
CPU_0
CPU_0_1
R32 R26 33
CPU
REF0
CPU_1 CPU_2/ITP
CPU_2
3V66_0 3V66_1
3V66_0 3V66_1
3V66
SDRAM_0 SDRAM_1
DRAM_0 DRAM_1 DRAM_2 DRAM_3 DRAM_4 DRAM_5 DRAM_6 DRAM_7
R43 33 R44 33 R45 33 R46 33
PCI_0 PCI_1 PCI_2 PCI_3 PCI_4 PCI_5 PCI_6
ICS9250-10
PCI_0/ICH PCI_1 PCI_2 PCI_3 PCI_4 PCI_5 PCI_6 PCI_7
SDRAM_2 SDRAM_3
R27 22 R28 22 R29 22 R30 22
R36 22 R37 22 R38 22 R39 22
CK-Whitney
PCI
Memory
SDRAM_4 SDRAM_5 SDRAM_6 SDRAM_7
DCLK
DCLK
R40 22
8 32
PWRDWN#
B
1 L_CKVDDA
DOTCLK
R47 22
USB_1
USB_1
USB
14
USBCLK
R53 33
USB_0
USB_0
SCLK SDATA SEL1 SEL0
25 25 4,9
L_VCC2_5
L15
C52
C53
22
VDD_A VDD2_5[0]
51 53 56 48 .001UF 0.1UF
2
0.1UF
.001UF
VDD2_5[1]
23
VSS_A VSS3_3[0] VSS3_3[1] VSS3_3[2] VSS3_3[3] VSS3_3[4] VSS3_3[5] VSS3_3[6] VSS3_3[7] VSS2_5[1] VSS2_5[0]
C46
C47
C56
4.7UF
Minimize Stub Length from 14 17 24 35 41 CLK14 trace to JP6. JP6 47 5 6
APIC Clk Strap 16MHz 33MHz
JP6 in out*
JP1
A
R23 10K
REV:
CLOCK SYNTHESIZER
DRAWN BY:
R
1.3
INTEL CORPORATION
12-8-1998_13:05
1
OF
40
8
VTT1_5
5
VCC1_8
82810-DC100, PART 1: HOST INTERFACE

U2
U18
B20
V17
V16
V15
V14
V10
F17
F16
F14
F10
P6
V9
V8
V7
F8
F7
VCC_CORE[0]
VCC_CORE[1]
VCC_CORE[2]
VCC_CORE[3]
VCC_CORE[4]
VCC_CORE[5]
VCC_CORE[6]
VCC_CORE[7]
VCC_CORE[8]
VCC_CORE[9]
VCC_CORE[10]
VCC_CORE[11]
VCC_CORE[12]
VCC_CORE[13]
VCC1_8[0]
VCC1_8[1]
VCC1_8[2]
R80 75 1%
HD0# HD1# HD2# HD3# HD4# HD5#
Y5 W5 W8 AA6 AB6 Y6 AA5 AA9 V5 AC7 AB7 AC8 AA7 Y8 W7 AC6 W9 AC9 Y7 AA10 AB8 AC10 AB13 AB10 AB9 AB11 Y10 AB16 AB12 Y11 Y9 AC12 W11 AC11 W12 AA11 AA13 Y13 Y12 AC14 AA15 AC15 Y14 AC13 AA14 AB14 Y17 Y15 AC17 AC16 AA18 AB15 W15 AB18 W17 AA17 W18 W16 AC19 Y16 AB19 Y18 AC18 AB17
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
HD#[63:0]
3,5
D
R81 150 1% 0.1UF .001UF C166 C167 6 13,17,18,24,27 4,5 4,5 4,5 4,5 4,5 4,5 4,5 4,5 4,5 4,5 4,5 3,5
GMCHGTLREF
M5 W13
GTLREFA GTLREFB
GMCHHCLK PCIRST# CPURST# HLOCK# DEFER# HADS# BNR# BPRI# DBSY# DRDY# HIT# HITM# HTRDY# HA#[31:3] HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HREQ#[4:0] HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 RS#[2:0] RS#0 RS#1 RS#2
V6 M2 AB4 P5 R3 N3 T3 T1 M4 N1 P1 R1 N4
HTCLK RESETB CPURST# HLOCK# DEFER# ADS# BNR# BPRI# DBSY# DRDY# HIT# HITM# HTRDY#
HD6# HD7# HD8# HD9# HD10# HD11# HD12#
INTEL 82810-DC100 PART1 HOST INTERFACE
HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49#
U5 U1 V4 V1 T4 U2 U3 W1 U4 W3 W4 T5 W2 V2 AC2 AA2 Y3 AB3 AA1 AB2 AC3 AA3 Y2 AB5 AC4 Y1 AC5 Y4 AB1
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#
R4 T2 P4 R2 R5
HD50# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] HD61# HD62# HD63# VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9]
N5 P2 N2
RS0# RS1# RS2#
M14
M13
M12
M11
M10
Do Not Stuff C161 C161 Place Site w/in 0.5" of clock ball (V6). 18PF
N22
C19
N14
Y19
E22
K14
K13
K12
N13
Y22
V18
J22
K11
K10
L14
L13
L12
L11
L10
REV:
82810-DC100 : HOST INTERFACE

DRAWN BY:
R
1.3
INTEL CORPORATION
11-23-1998_13:44
1
OF
40
6
VCC1_8
5
VCC3SBY VCC3_3
82810-DC100 PART 2: SYSTEM MEMORY AND HUB INTERFACE

SM_MAA[11:0] 11,12 SM_MAA0 SM_MAA1 SM_MAA2 SM_MAA3 SM_MAA4 SM_MAA5 SM_MAA6 SM_MAA7 SM_MAA8 RP70 and RP71 should be placed within 0.5" of the GMCH balls. SM_MAA9 SM_MAA10 SM_MAA11 SM_MAB[7:4]# Place HUBREF Generation Circuit in middle of VCC1_8 GMCH and ICH. C300
HUBREF_CV 8 7 6 5 RP70
Place Resistor as Close

G3 D4 C7 K6
U2
B2
F9
F6
L3
as possible to GMCH
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCC3_3[15]
VCC3_3[0]
VCC3_3[1]
VCC3_3[2]
VCC3_3[3]
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]
VCC3_3[7]
VCC3_3[8]
VCC3_3[9]
R82 40 1%
G21
C11
C15
R18
F15
F18
L21
J18
SMD0 SMD1 SMD2 SMD3 SMD4 SMD5 SMD6 SMD7 SMD8 SMD9 SMD10
E17 C16 D15 D17 C17 A17 A16 B16 A15 C14 B14 A14 D13 C13 A13 A12 E1 F2 G4 G1 D3 H2 H1 J4 J1 K2 K1 K3 L1 L2 M3 K4 D16 E15 D14 E14 E13 E12 D12 B15 B12 C12 D11 D10 E10 E9 E8 C8 F3 F1 G2 H3 E4 E3 F4 J3 F5 G5 H5 H4 H6 J5 K5 L5
SM_MD0 SM_MD1 SM_MD2 SM_MD3 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29 SM_MD30 SM_MD31 SM_MD32 SM_MD33 SM_MD34 SM_MD35 SM_MD36 SM_MD37 SM_MD38 SM_MD39 SM_MD40 SM_MD41 SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD50 SM_MD51 SM_MD52 SM_MD53 SM_MD54 SM_MD55 SM_MD56 SM_MD57 SM_MD58 SM_MD59 SM_MD60 SM_MD61 SM_MD62 SM_MD63
SM_MD[63:0] 11,12
C9 E7 A9 D7
1 2 3 4 R_MAA4 R_MAA5 R_MAA6 R_MAA7
SMAA0 SMAA1 SMAA2 SMAA3 SMAA4 SMAA5 SMAA6 SMAA7 SMAA8 SMAA9 SMAA10 SMAA11
B8 A8 B7 A7 D6 C6 D5 A5
10 OHMS
INTEL 82810-DC100 PART 2 SYSTEM MEMORY AND HUB INTERFACE
SMD11 SMD12 SMD13 SMD14 SMD15 SMD16 SMD17 SMD18 SMD19 SMD20 SMD21 SMD22 SMD23 SMD24 SMD25 SMD26 SMD27 SMD28
12
SM_MAB4# SM_MAB5# SM_MAB6# SM_MAB7#
8 7 6 5 RP71
1 2 3 4
R_MAB#4 R_MAB#5 R_MAB#6 R_MAB#7
B6 A6 B4 A4
SMAB4# SMAB5# SMAB6# SMAB7#
SM_DQM[7:0] 11,12 470PF
10 OHMS SM_DQM0 SM_DQM1 SM_DQM2

C10 A10 B1 D1 B10 D9 C1 D2 SDQM0 SDQM1 SDQM2 SDQM3 SDQM4 SDQM5 SDQM6 SDQM7
R177 56
R130 301 1% HUBREF 8,13
SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7
R176 56 C299
R131 301 1%
SM_BS[1:0] 11,12
SM_BS0 SM_BS1
C5 E5
SBS0 SBS1
SMD29 SMD30
SM_CS#[3:0] 11,12
SM_CS#0 SM_CS#1 SM_CS#2 SM_CS#3
C4 C3 B3 C2
SCS0# SCS1# SCS2# SCS3#
SMD31 SMD32 SMD33 SMD34 SMD35 SMD36 SMD37 SMD38 SMD39 SMD40 SMD41 SMD42 SMD43
HUBREF_CG
470PF
11,12 11,12 11,12 11,12 6 DCLK_WR R31 C168 6,8 13 0K
SM_RAS# SM_CAS# SM_WE# SM_CKE[1:0] SM_CKE0 SM_CKE1 SCLK GMCH_3V66 HL[10:0]
D8 A11 B11
SRAS# SCAS# SWE#
A3 A2 E6
SCKE0 SCKE1 SCLK
D19
SMD44 HLCLK HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HUBREF HLSTB HLSTB# HCOMP VSS[43] VSS[44] VSS[41] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[42] VSS[45] SMD45 SMD46 SMD47 SMD48 SMD49 SMD50
HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10
C21 B23 B22 A23 B19 B18 C18 A18 A22 C20 A19 D20 A21 A20
GHCOMP D18
22PF
HUB I/F
SMD51 SMD52 SMD53 SMD54 SMD55 SMD56 SMD57 SMD58 SMD59 SMD60 SMD61 SMD62 SMD63
HUBREF 8,13 HLSTB HLSTB#
8,13
C241 Place C241 as close as possible to GMCH
0.1UF
C236
AA12 AA16 V3 N12 N11 N10 W10 W14 P14 P13 P12 P11 P10 AC1 W6 P3 M1 AA4 AA8 R6 L4 J2
REV:
18PF
82810-DC100: SYSTEM MEMORY AND HUB

DRAWN BY:
R
1.3
INTEL CORPORATION
5-26-1999_17:13
1
OF
40
6
VCC1_8
3
VCC1_8 L24
33UF 20%
82810-DC100, PART 3: DISPLAY CACHE AND VIDEO INTERFACE

U2
10 DC_CS# DC_DQM[3:0] 10 DC_DQM0 DC_DQM1 DC_DQM2 DC_DQM3
L20
VCCDACA
68NH-0.3A
AC20
AB23
AB21
C217
C216 0.01UF
C222
0.1UF
E19
U6
VCCBA
VCCDACA1
LCS#
VCCDACA2
VCCHA
VCCDA
P21 R23 C23 F20 K19 K20 J19
LDQM0 LDQM1 LDQM2 LDQM3 LRAS# LCAS# LWE# LMA0 LMA1 LMA2 LMA3 LMA4 LMA5 LMA6 LMA7 LMA8 LMA9 LMA10 LMA11 LMD0 LMD1 LMD2 LMD3 LMD4 LMD5 LMD6 LMD7 LMD8 LMD9 LMD10 LMD11 LMD12 LMD13 LMD14 LMD15 LMD16 LMD17 LMD18 LMD19 LMD20 LMD21 LMD22 LMD23 LMD24 LMD25 LMD26 LMD27 LMD28 LMD29 LMD30 LMD31 LTCLK
LTVDATA0 LTVDATA1 LTVDATA2 LTVDATA3 LTVDATA4
Y21 Y20 W23 W22 W21 V23 U23 U22 U21 T23 T22 T21 V19 U20 V21 V22 V20 U19
FTD0 FTD1 FTD2 FTD3 FTD4 FTD5 FTD6 FTD7 FTD8 FTD9 FTD10 FTD11
FTD[11:0]
D
24
GMCH RESET STRAPS

10 4 4,6 VCOREDET FREQSEL 10 VCC3_3 10 10
DC_RAS# DC_CAS# DC_WE# DC_MA[11:0] DC_MA0 DC_MA1 DC_MA2 DC_MA3 DC_MA4 DC_MA5 DC_MA6 DC_MA7 DC_MA8 DC_MA9
VIDEO DIGITAL OUT INTERFACE
LTVDATA5 LTVDATA6 LTVDATA7 LTVDATA8 LTVDATA9 LTVDATA10 LTVDATA11 BLANK#
M19 P19 P20 N19 J21 H19 H20 H18 G19 F19 M20 L19 M22 M21 L23 L22 K21 K23 R19 R20 R22 R21 P23 P22 N23 N21 N20 M23 F23 E20 E21 E23 D22 D23 D21 C22 H21 H22 H23 G20 G22 G23 F21 F22 K22
FTBLNK# SL_STALL FTCLK0 FTCLK1 FTVSYNC FTHSYNC 3VFTSCL 3VFTSDA
24 24 24 24 24 24 24,25 24,25
RP46
RP48
INTEL 82810-DC100 PART3 DISPLAY CACHE AND VIDEO INTERFACE
TVCLKIN/SL_STALL CLKOUT0 CLKOUT1 TVVSYNC TVHSYNC
10K
10K
DC_MA10 DC_MA11
LTVCL LTVDA
T19 T20
GRS_PU28
GRS_PU26
GRS_PU31
GRS_PU30
10
DC_MD[31:0]
DC_MD0 DC_MD1 DC_MD2
JP16 JP15
DC_MD31 DC_MD30 DC_MD29
9,10 9,10 9,10 9,10 9,10 9,10
DC_MD3 DC_MD4 DC_MD5 DC_MD6 DC_MD7 DC_MD8 DC_MD9 DC_MD10 DC_MD11 DC_MD12 DC_MD13 DC_MD14 DC_MD15 DC_MD16 DC_MD17 DC_MD18 DC_MD19 DC_MD20 DC_MD21 DC_MD22 DC_MD23 DC_MD24 DC_MD25 DC_MD26 DC_MD27 DC_MD28 DC_MD29 DC_MD30 DC_MD31
JP14
DC_MD28 DC_MD27
JP13
DC_MD26
Function XOR
B
Jumper JP16 JP15 N/A JP14
Tri-State System Bus Frequency IOQD VCORE Detect RESVD
Function IN=XOR TREE OUT=NORMAL* IN=TriState Mode OUT=NORMAL* READS System Bus Frequency
DISPLAY CACHE INTERFACE
DDCDA DDCCL
W19 W20
3VDDCDA 3VDDCCL DOTCLK
25 25 6
DCLKREF IWASTE IREF
AA21 Y23 AA23

IREFPD
IN=IO Queue Depth 1 OUT=IO Queue Depth 4* Detects Type of Processor N/A I/O Buffers JP13 TBD
10 DC_CLK R128
OCLK_FB
GRAPHICS INTERFACE
VSYNC HSYNC RED GREEN BLUE
AA20 AB20 AC21 AC22 AC23
CRT_VSYNC CRT_HSYNC VID_RED VID_GREEN VID_BLUE
25 25 25 25 25
R127 22
R_LTCLK
RCLK
J20 J23
R125 Place as close as 174 Possible to GMCH 1% and via straight to VSS plane.
C379 18PF
0K
R129
LRCLK LOCLK VSSDACA VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61]
Do Not Stuff C379 Place Site w/in 0.5" of clock ball (AA21).
OCLK
33 Place R129 within 0.5" of the GMCH Ball.

VSSHA
C238 Do Not Populate C238 22PF
VSSDA
VSSBA
TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD G6 J6 AA19 AA22 AB22 G18 E18 E11 B13 E16 B17 B21 K18 P18 T18 T6 E2 A1 B5 B9
REV:
82810-DC100: DISPLAY CACHE AND VIDEO

DRAWN BY:
R
1.3
INTEL CORPORATION
5-26-1999_17:09
OF
40
4MB Display Cache
VCC3_3
VCC3_3
25
13
38
25
13
38
VDD_1
VDD_2
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
DC_MA[11:0] 9 DC_MA0 VCC3_3 DC_MA1 DC_MA2 DC_MA3

21 22 23 24 27 28 29 30 31 32 20 19 A0 A1 A2 A3 A4 A5 A6 A7 A8
44
U8
1 VDD_1
44
U9
1
DC_MD[31:0] 9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49
VDD_2
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49
DC_MD0 DC_MD1 DC_MD2 DC_MD3 DC_MD4 DC_MD5 DC_MD6 DC_MD7 DC_MD8 DC_MD9 DC_MD10 DC_MD11 DC_MD12 DC_MD13 DC_MD14 DC_MD15 9 DC_DQM1 DC_DQM0 9 9 9 9 10
9 9 9 9 9 9 9 9 9 9 9 9 DC_CLK DC_CKE DC_CS# DC_RAS# DC_CAS# DC_WE#
DC_MA0 DC_MA1 DC_MA2 DC_MA3 DC_MA4 DC_MA5 DC_MA6 DC_MA7 DC_MA8 DC_MA9 DC_MA10 DC_MA11
21 22 23 24 27 28 29 30 31 32 20 19
A0 A1 A2 A3 A4 A5 A6 A7 A8
DC_MD16 DC_MD17 DC_MD18 DC_MD19 DC_MD20 DC_MD21 DC_MD22 DC_MD23 DC_MD24 DC_MD25 DC_MD26 DC_MD27 DC_MD28 DC_MD29 DC_MD30 DC_MD31 DC_DQM3 DC_DQM2
DC_DQM[3:0] 9
DC_MA4 DC_MA5 DC_MA6 DC_MA7 R114 4.7K DC_MA8 DC_MA9 DC_MA10 DC_MA11 DC_CLK DC_CKE DC_CS# DC_RAS# DC_CAS# DC_WE#
SDRAM 50-PIN TSOP
SDRAM 50-PIN TSOP
A9 A10 A11
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
A9 A10 A11
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
35 34
35 34
CLK CKE
CLK CKE
9 9 9 9
18 17 16 15
18 17 16 15
CS# RAS# CAS# WE# UDQM LDQM 36 14
CS# RAS# CAS# WE# UDQM LDQM 36 14
33 37
33 NC_1 VSSQ_4 VSSQ_3 VSSQ_2 VSSQ_1 NC_2 VSS_2 VSS_1 37
NC_1 VSSQ_4 VSSQ_3 VSSQ_2 VSSQ_1 VSS_2 VSS_1 NC_2
10
41
47
26
10
41
47
26
50
50
REV:
DISPLAY CACHE
DRAWN BY:
R
1.3
INTEL CORPORATION
11-23-1998_13:44
1
10 OF
40
A 8
SYSTEM MEMORY
8
8 8,12 SM_BS[1:0] VCC3SBY SM_MD[63:0]
18 26 40 41 90 49 59 73 84 102 110 124 133 143 157 168 6
8 MEMCLK[7:0] SM_DQM[7:0] J11

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 9 10 11 13 14 15 16 17 19 20 55 56 57 58 60 65 DQ22 DQ23 DQ24 66 67 69 DQ25 DQ26 DQ27 DQ28 DQ29 DQMB4 DQMB5 DQMB6 131 DQMB7 DQ30 DQ31 DQ32 DQ33 70 71 72 74 75 76 77 86 87 30 114 45 129 27 111 115 S0# S1# S2# S3# WE# CAS# RAS# DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 88 89 91 92 93 94 95 97 128 63 CKE0 CKE1 DQ42 DQ43 DQ44 82 83 SMBDATA SMBCLK DQ45 DQ46 DQ47 147 165 166 167 81 24 SAO_PU 25 31 44 REGE SA0 SA1 SA2 WP DQ53 NC1 NC2 NC3 NC4 48 DQ54 DQ55 DQ56 DQ57 DQ48 DQ49 DQ50 DQ51 DQ52 98 99 100 101 103 104 139 140 141 142 144 149 150 151 153 154 8 7 5 4 3 2
8 SM_MAA[11:0] SM_MD0 SM_MD1 SM_MD2 SM_MD3 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10 SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15
7
42 CLK0 CLK1 CLK2 CLK3 125 79 163
MEMCLK0 MEMCLK1 MEMCLK2 MEMCLK3
SM_MAA0
33 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 117 34 118 35 119 36 120 37 121 38 123 126 132
SM_MAA1 SM_MAA2 SM_MAA3 SM_MAA4 SM_MAA5 SM_MAA6 SM_MAA7 SM_MAA8
DIMM0
SLAVE ADDRESS = 1010000B
6
SM_MAA10 SM_MAA11 8 SM_BS0
122 BA0 BA1 39
SM_MAA9
SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22 SM_MD23 SM_MD24 SM_MD25 SM_MD26 SM_MD27 SM_MD28 SM_MD29
12,14,25,28,33 SM_BS1 SM_DQM0

28 DQMB0 DQMB1 DQMB2 DQMB3 29 46 47 112 113 130
12,14,25,28,33 SM_WE# SM_RAS# SM_CAS# SM_CS#[3:0] SM_CKE[1:0] SMBDATA SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4
SMBCLK
5
SM_DQM6 SM_DQM7 SM_CS#0 SM_CS#1 SM_CKE0 SM_CKE1
SM_DQM5
4 3
12
50 51 61 62 80 108
R
NC5 NC6 NC7 NC8 NC9 NC10 NC11 109 134 135 145 146 164 NC12 NC13 NC14 NC15 NC16 NC17 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7
155 156 158 159 160 161 21 22 52 53 105 106 136
SM_MD58 SM_MD59 SM_MD60 SM_MD61 SM_MD62 SM_MD63
PCD PLATFORM DESIGN
1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 2

137
85
96
12
23
32
43
54
64
68
78
107
116
127
138
148
152
162
SYSTEM MEMORY: DIMM0

DRAWN BY:
INTEL CORPORATION
12-8-1998_13:14
1
OF
11
40
1.3
REV:
A 8
SYSTEM MEMORY
8
8,11 8 8 8 8 6 VCC3SBY SM_BS[1:0] MEMCLK[7:0] SM_DQM[7:0] SM_MAB[7:4]# SM_MAA[11:0] SM_MD[63:0]
7
18 26 40 41 90 49 59 73 84 102 110 124 133 143 157 168 6
J13
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 42 CLK0 CLK1 CLK2 CLK3 125 79 163
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 55 56 57 58 60 65 DQ22 66
SM_MD0 SM_MD1 SM_MD2 SM_MD3 SM_MD4 SM_MD5 SM_MD6 SM_MD7 SM_MD8 SM_MD9 SM_MD10
MEMCLK4 MEMCLK5 MEMCLK6 MEMCLK7
SM_MAA0
33 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 117 34 118 35 119 36 120
SM_MAA1 SM_MAA2 SM_MAA3
DIMM1
SLAVE ADDRESS = 1010001B
6
SM_MAB5# SM_MAB6# SM_MAB7# SM_MAA8
37 121 38 123 126 132
SM_MAB4#
SM_MD11 SM_MD12 SM_MD13 SM_MD14 SM_MD15 SM_MD16 SM_MD17 SM_MD18 SM_MD19 SM_MD20 SM_MD21 SM_MD22
SM_MAA9 SM_MAA10 SM_MAA11
SM_BS0
122 39
11,14,25,28,33
BA0 BA1
8 8 8 8 SM_BS1 SM_DQM0 SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7
11,14,25,28,33
DQ23 DQ24
67 69 28 29 46 47 112 113 130 131 DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 30 114 S0# S1# DQ34 DQ35 70 71 72 74 75 76 77 86 87 88 89
SM_MD23 SM_MD24
5
SM_CS#[3:0] SM_CKE[1:0] SMBCLK SM_CS#2 SM_CS#3 SM_WE# SM_RAS# SM_CAS# SMBDATA
45 129 27 S2# S3# WE# 111 115 CAS# RAS# DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 91 92 93 94 95 97
SM_MD36 SM_MD37 SM_MD38
4
SM_CKE0 SM_CKE1
128 63 82 83 147 165 166 167 81 24 25 31 44 48 50
R
SM_MD39 SM_MD40 SM_MD41

CKE0 CKE1 DQ42 DQ43 DQ44 SMBDATA SMBCLK DQ45 DQ46 DQ47 REGE SA0 SA1 SA2 WP DQ53 NC1 NC2 NC3 NC4 NC5 NC6 51 61 62 80 108 109 134 135 145 146 164 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 DQ48 DQ49 DQ50 DQ51 DQ52 98 99 100 101 103 104 139 140 141 142 144 149 150 151 153 154 155 156 158 159 160 161 21 22
SM_MD42 SM_MD43 SM_MD44 SM_MD45 SM_MD46 SM_MD47 SM_MD48 SM_MD49 SM_MD50

SAO_PU
SM_MD51 SM_MD52
3
PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 2
52 53 105 106 136 137
SYSTEM MEMORY: DIMM1

DRAWN BY:
85
96
12
23
32
43
54
64
68
78
107
116
127
138
148
152
162
R60 2.2K
INTEL CORPORATION
12-8-1998_13:14
1
OF
VCC3SBY
12
40
1.3
REV:
6
VCC3_3
4
VCC1_8
ICH0, Part 1
U14
M14
G13
G15
U10
R13
C11
D16
N13
H14
H16 VCC1_8_6
E13
K14
T16
L15
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCC1_8_5
VCC1_8_7
J16
G5
C8
N5
E3
P6
A5
E6
E5
T7
D
17,18,27 AD[31:0] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16
G2 G4 F2 F3 F4 F5 E1 E2 D1 D3 E4 C2 C1 B1 D4 C3 A4 B4 C5 C6 B5 E7 A6 B6 D7 B8 A7 A8 B7 C9 D8 C7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
D
F13 E12 F15 B17 E15 E14 B16 F14 A17 A15 B15
A20M# CPUSLP# FERR# IGNNE# INIT#
A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE HL[10:0] HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HLSTB HLSTB#
IHCOMP_PU
4,33 4,33 4,33 4,33 4,15,33 4,33 4,33 4,33 4,33 16,33 16,33 8 VCC1_8
CPU
INTR NMI SMI# STPCLK# RCIN# A20GATE
INTEL 82801AB PART 1

PCI HUB I/F
HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HLSTB HLSTB# HCOMP HUBREF
D17 E17 F17 G16 J15 K16 K17 L17 H15 J17 J14 G17 H17 M17 J13
AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C_BE#[3:0] C_BE#0 C_BE#1 C_BE#2 C_BE#3 PCLK_0/ICH FRAME# DEVSEL# IRDY# TRDY# STOP# PCIRST# PLOCK# PAR SERR# PCI_PME# PCPCI_REQ#A PCPCI_GNT#A REQ#B/GPIO1 GNT#B/GPIO17
R182 40, 1% Place R182 as close as possible to ICH0. 8 8 HUBREF PIRQ#A PIRQ#B PIRQ#C PIRQ#D IRQ14 IRQ15 APICCLK_ICH APICD1 APICD0 SERIRQ PREQ#0 PREQ#1 PREQ#2 PREQ#3 PGNT#0 PGNT#1 PGNT#2 PGNT#3 R174 R175 8.2K 8.2K 8
PIRQ#A PIRQ#B PIRQ#C PIRQ#D
D10 A10 B10 C10
17,18,27,33 17,18,33 17,18,33 17,18,33 19,33 19,33 6 4,33 4,33 16,18,33 17,33 17,33 18,33 27,33 17,33 17,33 18,33 27,33
C302 0.1UF Place C302 as close as possible to ICH0.
17,18,27
D2 B2 A3 D6
C_BE#0 C_BE#1 C_BE#2 C_BE#3
IRQ
IRQ14 IRQ15 APICCLK APICD1 APICD0
P11 N14 C16 C17 E16 R4
B
6 17,18,27,33 17,18,27,33 17,18,27,33 17,18,27,33 17,18,27,33 7,15,16,17,18,19,24,27 17,18,33 17,18,27 17,18,27,33 17,18,27 18,33 18 33 33
C14 B3 D9 A2 C4 D5 J5 B9 A9 A1 K1
PCICLK FRAME# DEVSEL# IRDY# TRDY# STOP# PCIRST# PLOCK# PAR SERR# PME#
SERIRQ
REQ#0 REQ#1 REQ#2
A14 B13 B12 D12 A13 C13 A12 C12
PCI
REQ#3 GNT#0 GNT#1 GNT#2 GNT#3
VCC3_3
N6 P5 P4 R5
REQ#A/GPIO0 GNT#A/GPIO16 REQ#B/GPIO1/REQ5# GNT#B/GPIO17/GNT5# VSS10 VSS11 VSS12 VSS13 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
GNT4# REQ4#
A11 B11 F16
RESV0PU RESV1PU RESV2PD
PC/PCI
R181 0K
Dont Stuff R181 For Test/Debug
HL11
J8
J9
H10
G14
J10
G3
K10
K15
K8
R2
H8
H9
K9
REV:
ICH0, PART 1
DRAWN BY:
R
1.3
INTEL CORPORATION
2-22-1999_10:37
1
13
OF
40
6
VCC3SBY
4
VCC3SBY
2
VCC3_3
1
VCC5
ICH0
VCC3SBY
VRTC ICH5VREF BAT17 A
PART 2
CR13
A BAT17 C R85 and R203 for Test/Debug
CR11 C290 C294 0.1UF
R173
C
C15
G1
N1
VCCSUS2
VCCSUS1
VCCRTC
1K
5VREF
R206
R85
R203
L1
10K
10K
U14
1.0UF
1K
C349 1.0UF
33
THERM# SLP_S3#
SLP_S5#
D14 K3 K2 J3 M2 L3 F1 L4
THRM# SLP_S3/GPIO24 SLP_S5 PWROK PWRBTN# RI# RSMRST# SUSSTAT#/GPIO25
JP20 Config 1-2 Normal 2-3 Clear CMOS

JP20 VBATC_DLY 1 2 RTCRST# JP24_PD 3
29,32 28,32 31 22 28,32 28 11,12,25,28,33 11,12,25,28,33 33 33
PWROK PWRBTN# ICH_RI# RSMRST# SUS_STAT# SMBDATA SMBCLK SMBALERT# INTRUDER# ICH_CLK14 USBCLK ICH_3V66
VBIAS
PDCS#1 SDCS#1 PDCS#3 SDCS#3
N12 L14 U13 L16
PDCS#1 SDCS#1 PDCS#3 SDCS#3 PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 PDREQ SDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDD[15:0] PDD[15:0] SDA[2:0] PDA[2:0]
19 19 19 19 19
VBATC
R219 CR14 8.2K

1
PDA0 PDA1
R12 T12 P12 M16 M15 L13
C BAT17
C364
J1 J2 M1
SMBDATA SMBCLK SMBALERT#/GPIO11
SYSTEM
PDA2 SDA0 SDA1 SDA2
2.2UF
19
R216 R202
VBAT
1K
R_VBIAS
1K
J4 U6 U2 A16 H2 H3 H4 H1
INTRUDER#/GPIO10 CLK14 CLK48 CLK66 VBIAS RTCX1 RTCX2 RTCRST#
C347 2200PF
6 6 6
PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW#
U11 P17 U12 M13 R11 N16 T11 N15 N11 N17
19 19 19 19 19 19 19 19 19 19 19
C
R197 10M 26 R220 X3
2 1
RTCX1 RTCX2
AC_RST# AC_SYNC AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 ICH_SPKR LPC_SMI# LPC_PME# GPIO7 GPIO12 GPIO13 GPIO21 GPIO22 GPIO23_FPLED GPIO26_FPLED GPIO27 GPIO28 LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LFRAME#/FWH4 LDRQ#0 LDRQ#1 USBP1P USBP1N USBP0P USBP0N OC#0
T1 T3 R3 T2 U1 P3 U3
AC_RST# AC_SYNC AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1/GPIO9 SPKR
26 26 Y3 14,26
2
10M
Socketed CR2032
AC97
INTEL 82801AB PART 2

IDE
SDIOW# PIORDY SIORDY
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5
R10 N9 R9 U9 R8 U8 R7 U7 P7 N7 T8 P8 T9 P9 T10 P10
26,33 26,33 14,31 C366 12PF 16,33 16,33 18,33 33 33 18,33 33
C346 12PF
32.768KHZ
D11 E11 E9 N4 L2 B14 D13 D15 K4 M5 L5
GPIO5 GPIO6 GPIO7/PERR# GPIO12 GPIO13 GPIO21 GPIO22 GPIO23 GPIO26/SUSCLK GPIO27 GPIO28
PDD6 PDD7 PDD8 PDD9
GPIO
PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
31 31 28 28
JP17 S TRA P (S PK R) IN No Reboot on 2nd watc hdog tim eout OUT Reboot on 2nd watc hdog tim eout JP18 IN OUT
14,31 ICH_SPKR
15,16 15,16 15,16 15,16 15,16 16 33
R6 U5 T5 T4 U4 T6 N3
LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 LFRAME#/FWH4 LDRQ#0 LDRQ#1/GPIO8
SDD0 SDD1 SDD2
P15 R16 T17 U16 U15 R14 P13 T13 U14 T14 P14 T15 U17 R15 R17 P16
19
(A C_S DOUT) Forc e CP U freq strap to safe m ode (1111) Use CPU freq s trap in ICH regis ter
VCC3_3
LPC
SDD3 SDD4 SDD5 SDD6 SDD7 SDD8
JP17
20 20 20 10K
JP13_PD
R1 P2 P1 N2 M4
USBP1P USBP1N USBP0P USBP0N OC#1 OC#0
SDD9
USB
SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
20 20 Minimize Stub Length to Jumpers
R187
JP14_PU
M3
R209 10K JP18
C293 18PF AC_SDOUT

REV:
ICH0, PART 2
14,26
DRAWN BY:
R
1.3
INTEL CORPORATION
5-26-1999_17:09
14
OF
40
FirmWare Hub (FWH) Socket

NOTE: This is a Socketed Implementation
D
VCC3_3
VCC3_3
C211 0.1UF VCC3_3
C355 0.1UF
C361 0.1UF
C259 0.1UF
Distribute close to each power pin. X4

1 2 NC1 IC NC3 NC4 NC5 NC6 FGPI4 NC8 CLK VCC10 VPP RST# NC13 NC14 FGPI3 FGPI2 FGPI1 FGPI0 WP# TBL#
40PIN_TSOP_SKT
GNDA VCCA FWH4 INIT# RFU36 RFU35 RFU34 RFU33 RFU32 VCC31 GND30 GND29 FWH3 FWH2 FWH1 FWH0 ID0 ID1 ID2 ID3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
C353 0.1UF
C36 0.1UF
3 4 5 6 7 8
LFRAME#/FWH4 INIT#
14 4,13,33
6 R218 0K 13,17,18,24,27
PCLK_6
9 10 R_VPP 11 12 13 14
PCIRST#
LAD3/FWH3 LAD2/FWH2 LAD1/FWH1 LAD0/FWH0 FWH_ID0 FWH_ID1 FWH_ID2 FWH_ID3
14,16 14,16 14,16 14,16
VCC3_3
VCC3_3 S66DETECT P66DETECT
15 16
19 19
17 18 19
JP21 CONFIG IN Unlocked OUT Locked Default
JP21
FGPI4_PD FGPI3_PD FGPI2_PD
20
WPROT
4.7K
4 3 2 1 4 3 2 1
TBLK_LCK 8.2K R223 4.7K RP63 0K RP64 RP64 for Test/Debug

5 6 7 8 5 6 7 8
IC_PD
R222
REV:
FIRMWARE HUB (FWH)

DRAWN BY:
R
1.3
INTEL CORPORATION
2-22-1999_10:37
1
15
OF
40
6
VCC3_3
5
VCC5
4
VCC3_3
Super I/O
44 18 53 65 VCC2 VREF VCC1
VCC3_3
Decoupling
VCC5
D
Place near VREF pin
1 +
14 14,15 14,15 14,15 14,15 14 13,17,18,24,27 14,33
LFRAME#/FWH4 LAD3/FWH3 LAD2/FWH2 LAD1/FWH1 LAD0/FWH0 LDRQ#0 PCIRST#

SUSSTAT_PU
24 23 22 21 20 25 26 27 17 30 29
VCC3
VTR
93
R183 4.7K
U15
LFRAME# LAD3 LAD2 LAD1 LAD0 LDRQ# LRESET# LPCPD# PME# SERIRQ PCI_CLK INIT# SLCTIN# PD7 PD6 66 67 75 74 73 72 71 70 69 68 77 78 79 80 81 82 83
PAR_INIT# PDR7 PDR6 PDR5 PDR4 PDR3 PDR2 PDR1 PDR0 SLCT# PE BUSY ACK# ERROR# ALF# STROBE# SLCTIN# PDR[7:0]
D
21 21 21
C99 2.2UF
C287 0.1UF
C246 0.1UF
C297 0.1UF
C229 0.1UF
C323 0.1UF
LPC I/F
PD5 PD4
PARALLEL PORT I/F
PD3 PD2 PD1
LPC_PME# SERIRQ PCLK_1 KDAT KCLK MDAT MCLK RCIN# A20GATE
Place 1 0.1UF cap near each power pin
13,18,33 6
SIO
LPC47B27X
PD0 SLCT# PE BUSY ACK#
23 23 23 23 13,33 13,33
56 57 58 59 63 64
KDAT KCLK MDAT MCLK KBDRST A20GATE
21 21 21 21 21 21 21
KYBD/MSE I/F
ERROR# ALF# STROBE#
C
31 31
IRRX IRTX RXD#0 TXD0 DSR#0 RTS#0 CTS#0 DTR#0 RI#0 DCD#0
61 62
IRRX2/GP34 IRTX2/GP35
FAN2/GP32
54 55
PWM2 PWM1 SIO_GP43
INFRARED I/F
31 31
FAN1/GP33
C356 470PF
C371 470PF
22 22 22 22 22 22 22 22
84 85 86 87 88 89 90 91
RXD1 TXD1 DSR1# RTS1# CTS1# DTR1# RI1# DCD1#
FDC_PP/DDRC/GP43
28
SERIAL PORT 1
Test/Debug Header Unused GPIOs

J23
1 3 5 2 4 6
22 22 22 22 22 22 22 22
RXD#1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 DRVDEN#1 DRVDEN#0 MTR#0 DS#0 DIR# STEP# WDATA# WGATE# HDSEL# INDEX# TRK#0 WRTPRT# RDATA# DSKCHG#
95 96 97 98 99 100 92 94
RXD2_IRRX TXD2_IRTX DSR2# RTS2# CTS2# DTR2# RI2# DCD2#
SERIAL PORT 2
GP60/LED1 GP61/LED2 GP27/IO_SMI# GP30/FAN_TACH2 GP31/FAN_TACH1 48 49 50 51 52 46 47
SIO_GP60 SIO_GP61 LPC_SMI# TACH2 TACH1 MIDI_IN MIDI_OUT J1BUTTON1 J1BUTTON2 J2BUTTON1 J2BUTTON2 JOY1X JOY1Y JOY2X JOY2Y KEYLOCK# SIO_GP21 SIO_GP22 14,33 31 31 23 23 23 23 23 23 23 23 23 23 31
23 23 23 23 23 23 23 23 23 23 23 23 23 23
2 1 3 5 8 9 10 11 12 13 14 15 16 4
DRVDEN1 DRVDEN0 MTR0# DS0# DIR# STEP# WDATA# WGATE# HDSEL# INDEX# TRK0# WRTPRT# RDATA# DSKCHG#
GP25/MIDI_IN GP26/MIDI_OUT
GP10/J1B1 GP11/J1B2 GP12/J2B1 GP13/J2B2
32 33 34 35 36 37 38 39 41 42 43
FDC I/F
GP14/J1X GP15/J1Y GP16/J2X GP17/J2Y GP20/P17 GP21/P16 GP22/P12
A
6 CLKI32 CLOCKI GND1 GND2 GND3 GND4 AVSS
CLOCKS
GP24/SYSOPT
45
SYSOPT Pulldown on SYSOPT for IO address of 0x02E
SIO_CLK14
19
R180 4.7K
REV:
31
60
76
40
SUPER I/O
DRAWN BY:
R
1.3
INTEL CORPORATION
11-23-1998_13:44
1
16
OF
40
2
VCC3SBY VCC12M VCC5 VCC3_3 VCC5 VCC12
PCI Connector 0 (DEV Ah)

VCC3_3
VCC3SBY VCC12M VCC5 VCC3_3 VCC5 VCC12
PCI Connector 1 (DEV Bh)

17,18 PTCK PTRST# PTMS PTDI PIRQ#A PIRQ#C 17,18 17,18,33 17,18,33 13,17,18,27,33 13,17,18,33 13,17,18,33 13,17,18,27,33 18 18 PIRQ#C PIRQ#A PRSNT#21 PRSNT#22
VCC3_3
J16
PCI3_CON B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
key
J17
PCI3_CON B1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
key
PTRST# PTMS PTDI PIRQ#B PIRQ#D
17,18 17,18,33 17,18,33 13,17,18,33 13,17,18,33
17,18
PTCK
B2 B3 B4 B5 B6
13,17,18,33 13,17,18,33 18 18
PIRQ#B PIRQ#D PRSNT#11 PRSNT#12
B7 B8 B9 B10 B11 B12 B13 B14 B15
PCIRST# PGNT#1 PCI_PME# AD[31:0]
7,13,15,16,17,18,19,24,27 13,33 13,17,18,27 13,17,18,27
6 PCIRST# PGNT#0 PCI_PME# AD[31:0] 7,13,15,16,17,18,19,24,27 13,33 13,17,18,27 13,17,18,27 13,33 13,17,18,27
PCLK_3 PREQ#1 AD[31:0] AD31 AD29 AD27 AD25 C_BE#[3:0] C_BE#3 AD23
B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28
6 13,33
PCLK_2 PREQ#0 AD[31:0] AD31 AD29 AD27 AD25 C_BE#[3:0] C_BE#3 AD23 AD21 AD19 AD17 C_BE#2 IRDY# DEVSEL# PLOCK# PERR# SERR# C_BE#1 AD14 AD12 AD10
B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34
AD30 AD28 AD26 AD24 R_AD17 AD22 AD20 AD18 AD16
13,17,18,27
AD30 AD28 AD26
C
R191 100
13,17,18,27 AD24 R_AD16 AD22 AD20 AD18 AD16 13,17,18,27,33 FRAME# TRDY# STOP# SDONEP1 SBOP1 PAR AD15 AD13 AD11 AD9 13,17,18,27,33 13,17,18,27,33 13,17,18,27,33 33 33 13,17,18,27 13,17,18,27,33 13,17,18,33 17,18,27 13,17,18,27,33 IRDY# DEVSEL# PLOCK# PERR# SERR# R168 100 AD16 13,17,18,27
AD17
13,17,18,27
13,17,18,27
AD21 AD19 AD17 C_BE#2
B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43
FRAME# TRDY# STOP# SDONEP2 SBOP2 PAR AD15 AD13 AD11 AD9
13,17,18,27,33 13,17,18,27,33 13,17,18,27,33 33 33 13,17,18,27
13,17,18,27,33 13,17,18,27,33 13,17,18,33 17,18,27 13,17,18,27,33
B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
C_BE#1 AD14 AD12 AD10
B44 B45 B46 B47 B48 B49
AD8 AD7
B52 B53 B54
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
C_BE#0 AD6 AD4 AD2 AD0 PU2_REQ64#
13,17,18,27
AD8 AD7 AD5 AD3
B52 B53 B54 B55 B56 B57
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
C_BE#0 AD6 AD4 AD2 AD0 PU1_REQ64#
13,17,18,27
AD5 AD3 AD1 PU2_ACK64#
B55 B56 B57 B58 B59
AD1 PU1_ACK64#
B58 B59
33
B60 B61 B62
33
33
B60 B61 B62
33
REV:
PCI CONNECTORS 1 AND 2

DRAWN BY:
R
1.3
INTEL CORPORATION
11-23-1998_13:44
1
17
OF
40
PCI Connector 2 (DEV 6h)

VCC12M VCC5 VCC3_3
B1
Layout Note: Should be in Slot 0 Position (Outside Edge of Board Furthest from CPU)
VCC3_3 VCC5 VCC12
J22
PCI3_CON A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 R_GNT#A A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
key VAUX3 R185 0K
PTRST# PTMS PTDI PIRQ#C PIRQ#A
17,18 17,33 17,33 13,17,33 13,17,27,33
17,18
PTRST#
R189 5.6K
17,18
PTCK
B2 B3 B4 B5 B6
17,18
PTCK
R190 5.6K
13,17,33 13,17,33 18 14,33 18
PIRQ#D PIRQ#B PRSNT#31 GPIO21 PRSNT#32 R194 0K

R_GPO21
B7 B8 B9 B10 B11 B12
18 VCC3SBY PCPCI_GNT#A For Debug Only R193 PCIRST# PGNT#2 PCI_PME# AD[31:0] 7,13,15,16,17,19,24,27 13,33 13,17,27 13,17,18,27 0K Do Not Stuff R192 0K R192 PCPCI_REQ#A For Debug Only 13 18 17 17 17 17
PRSNT#32 PRSNT#31 PRSNT#22 PRSNT#21 PRSNT#12 PRSNT#11
For Debug Only
R195 13,16,33 6 13,33 13,17,18,27 SERIRQ 0K PCLK_4 PREQ#2 AD[31:0] AD31 AD29 AD27 AD25 C_BE#[3:0] 13,17,27 C_BE#3 AD23 AD21 AD19 AD17 C_BE#2 IRDY# DEVSEL# PLOCK# PERR# SERR# C_BE#1 AD14 AD12 AD10
R_SERIRQ
B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34
For Debug Only
13,33
C336 0.1UF
C337 0.1UF
C267 0.1UF
C284 0.1UF
C335 0.1UF
C342 0.1UF
AD30 AD28 AD26 AD24 R_AD22 AD22 AD20 AD18 AD16
R167 100
AD22
13,17,18,27
FRAME# TRDY# STOP# SDONEP3 SBOP3 PAR AD15 AD13 AD11 AD9
13,17,27,33 13,17,27,33 13,17,27,33 33 33 13,17,27
13,17,27,33 13,17,27,33 13,17,33
B35 B36 B37 B38 B39 B40 B41
JP19
1
PERR#_PU GPIO7
17,18,27 13,17,27,33
33 14,33
17,18,27
PERR#
2 3
B42 B43 B44 B45 B46 B47 B48 B49
JP19 - ICH/ICH0 Compatibility 1-2 ICH0 Default 2-3 ICH

C_BE#0 13,17,27
AD8 AD7 AD5 AD3 AD1 PU3_ACK64#
B52 B53 B54 B55 B56 B57
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
AD6 AD4 AD2 AD0
A
33
B58 B59 B60 B61 B62
A
PU3_REQ64# 33
REV:
PCI CONNECTOR 3
DRAWN BY:
R
1.3
INTEL CORPORATION
11-23-1998_13:44
1
18
OF
40
ULTRAATA/33 IDE CONNECTORS

VCC5
D
PDD[15:0] 14 R133 PCIRST_BUF# R140
R_RSTP#
PRIMARY IDE CONN.

SDD[15:0] 14
VCC5
SECONDARY IDE CONN.
R100
1K
1 3 5 7 9 11 13 15 17 19
J15
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 R_P66DET
19
33
19 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
PCIRST_BUF#
R139
R_RSTS#
1K
1 3 5 7 9 11 13 15 17 19
J12
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 R_S66DET
PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0
33
SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0
SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
14 14 14
PDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDA1 PDA0 PDCS#1 IDEACTP# PDA[2:0] PDA2
21 23 25 27 29 31 33 35 37 39
14 For Host-Side 80-Conductor Cable Detection: Populate R96 and R221, DePopulate C187 For Drive-Side 80-Conductor Cable Detection: Populate C187, DePopulate R96 and R221 R96 0K PDCS#3 14 14 31 14 C187 R221 0.047UF 15K 14 14 14 14 13,33 P66DETECT 15
SDREQ SDIOW# SDIOR# SIORDY SDDACK# IRQ15 SDA1 SDA0 SDCS#1 IDEACTS# SDA[2:0] SDA2
21 23 25 27 29 31 33 35 37 39
14 14 13,33
PRI_PD1
PRI_SD1
For Host-Side 80-Conductor Cable Detection: Populate R94 and R95, DePopulate C186 For Drive-Side 80-Conductor Cable Detection: Populate C186, DePopulate R94 and R95 R95 0K SDCS#3 14 S66DETECT 15
14 31 14
R135 5.6K
R138 10K
R101 470
R134 5.6K
R137 10K
R132 470
C186 0.047UF R94 15K
VCC3_3
B
VCC3_3
R141
U11 VCC
8.2K
6
13,17,18,24,27
PCIRST#
14
5 7
PCIRST_BUF#
19
GND SN74LVC07A
REV:
ULTRAATA/33 CONNECTORS
DRAWN BY:
R
1.3
INTEL CORPORATION
2-22-1999_10:37
1
19
OF
40
USB Connectors
VCC3_3
VCC5 Do Not Stuff 26 POLYSWITCH RUSB250 F3 2.5A

1
AC97_USB- R149 0K AC97_USB+ R148 0K
26
R147 330K
D
L23
USBV5 1 1 2
26
AC97_OC#
C202 68UF
2
C12 0.1UF
R146 0K Do Not Stuff
R72 470K USBV0 USBP0N USBP0P R204 15 R205 15

R_USBP0P
14
OC#0
14 14 R201 560K
R_USBP0N
R13 0K R15 0K
USBD0N USBD0P USBG0
C124 .001UF
R11 C348 C359 15K
R14 15K C15 L11 470PF

1 1 2 3 4 5 USB-CON2 VCC1 DATA1DATA1+ GND1 VCC2 DATA2DATA2+ GND2 2
47PF
47PF
J3
Place R204, R205, C348, and C359 within 1" of ICH0
L9
1 2
6 7 8
C201 68UF
2
C9 0.1UF
2 - USB Stacked
USBV1 14 14 USBP1N USBP1P R214 15 USBD1N R211 15 USBD1P USBG1
C358 47PF
C357 47PF
R12 15K
R63 15K
2
C13 47PF C14 470PF L10 C16 47PF
C8 47PF C98 47PF Place CAPs as close as possible to connector.
Place R214, R211, C357, and C358 within 1" of ICH0
REV:
USB CONNECTORS
DRAWN BY:
R
1.3
INTEL CORPORATION
11-23-1998_13:44
1
20
OF
40
Parallel Port Header
VCC5
CR1
A C PARV5
1N4148
6 3
R224 2.2K
RP28 2.2K
1 2 3 4
RP17 2.2K
1 2 3 4
RP13 2.2K
1 2 3 4
RP14 2.2K
1 2 4
16
ERROR# RP16
16 16 16 16
SLCTIN# PAR_INIT# ALF# STROBE#
1 2 3 4
8 7 6 5
R_SLCTIN# R_PARINIT# R_ALF# R_STROBE#
16
PDR[7:0]
33 RP15 PDR0 PDR1 PDR2 PDR3

1 2 3 4 8 7 6 5 7 R_PDR0 1 R_PDR1 3 R_PDR2 5
J5
2 4 6 8 10 12 14 16 18 20 22 24 26
33 RP27 PDR4 PDR5 PDR6 PDR7

1 2 3 4 8 7 6 5
R_PDR3 R_PDR4 R_PDR5 R_PDR6 R_PDR7
9 11 13 15 17 19 21
33 16 ACK#
23 25
16 16 16
BUSY C197 180PF PE SLCT# C194 180PF C192 180PF C189 180PF C96 180PF C92 180PF C88 180PF C93 180PF C91 180PF J5 Pinned Out for IDC (Flow Through) Ribbon Cable Connector
C196 180PF
C193 180PF
C190 180PF
C97 180PF
C94 180PF
C90 180PF
C89 180PF
C95 180PF
REV:
PARALLEL PORT
DRAWN BY:
R
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INTEL CORPORATION
2-22-1999_11:02
1
21 OF
40
Serial Port/COM Headers

VCC12VCC5 VCC12 J19 and J21 pinned out for IDC (Flow Through) Ribbon Cable Connector U17
D
20 VCC VCC12 1 2 3 4 5 6 7 8 9 10
D
DCD#0_C RXD#0_C DSR#0_C DTR#0_C TXD#0_C CTS#0_C RTS#0_C RI#0_C
1 3 5 7 9 J21 2 4 6 8 10
16 16 16 16 16 16 16
RXD#0 DSR#0 DTR#0 TXD0 CTS#0 RTS#0 RI#0
18 17 16 15 14 13 12 11
RY1 RY2 DA0 DA1 RY3 DA2 RY4 GND
GD75232
16
DCD#0
19
RY0
RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4 VCC-12
C325 100PF VCC3SBY C326 100PF
C327 100PF C328 100PF
C329 100PF C330 100PF
C368 COM1 and COM2 are 2x5 pin Headers for a cabled port. 100PF C369 100PF Place Close to Header
C
R230 10K RI#_CR_C 14 ICH_RI#
3 CR15 BAT54C 1 2
D 3 2N7002LT1 S
Q10
R227
47K
1 2
G ICHRI#_C
VCC12VCC5 R229
C374
2nd COM Header Option

If not populated at all, remove CR14 and short RI#0_C to RI#CR
VCC12
47K
1.0UF 20
U16
VCC VCC12 1 2 3 4 5 6 7 8 9 10
GD75232
16
DCD#1 RXD#1 DSR#1 DTR#1 TXD1 CTS#1 RTS#1 RI#1
19 18 17 16 15 14 13 12 11
RY0 RY1 RY2 DA0 DA1 RY3 DA2 RY4 GND
RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4 VCC-12
DCD#1_C RXD#1_C DSR#1_C DTR#1_C TXD#1_C CTS#1_C RTS#1_C RI#1_C

1 3 5 7 9 J19 2 4 6 8 10
NOTE: If Wake from S3 on Serial Modem is not supported do not stuff CR15 and Q10.
16 16 16 16 16 16 16
C316 100PF C312 100PF
C314 100PF C313 100PF
C315 100PF C309 100PF
C311 100PF C310 100PF Place Close to Header
REV:
SERIAL AND GAME PORTS

DRAWN BY:
R
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INTEL CORPORATION
2-22-1999_11:02
22
OF
40
KEYBOARD/MOUSE PORTS
VCC5 L3
2 1 PS2V5_F 2 PS2V5
FLOPPY DISK HEADER

VCC5
F2
1
1.25A
D
RP31
1 2 8 7 6 5 8 7 6 5
RP1 4.7K
STACKED PS2 CONNECTOR 1 2 3 4
3 4
1K
L5 16 KDAT
1 2 L_KDAT
J1 1 PS/2 Kybd 2 3 R143 1K J14

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
L4 16 KCLK
1 2 L_KCLK
4 5 6
16 16 17 PS/2 Mse 16 15 14 13 16 16 L1
2 PS2GND
DRVDEN#0 DRVDEN#1 INDEX# MTR#0 DS#0 DIR# STEP# WDATA# WGATE# TRK#0 WRTPRT# RDATA# HDSEL# DSKCHG#
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
L7 16 MDAT
1 2 L_MDAT
7 8 9
16 16 16
L6
10
2 L_MCLK
C
16
MCLK
11 12
C3 470PF
C4 470PF
C5 470PF
C2 470PF
C1 0.1UF
16 16 16 16 16 16 16
PS2_PD
L2
GAME PORT HEADER

J7 Pinned Out for IDC (Flow Through) Ribbon Cable Connector RP29 VCC5
R_JOY1X R_JOY1Y R_JOY2Y R_JOY2X 1 2 3 4 8 7 6 5
JOY1X JOY1Y JOY2Y JOY2X
16 16 16 16
2.2K C199 VCC5 VCC5

11 13 15 3 5 7 1 9
C198 0.01UF
C191 0.01UF
C195 0.01UF
0.01UF
J7
8 7 6 3 10 12 14 16 2 4 6 8 5 4
R89 4.7K
R178 4.7K
RP30 1K
1 2
J1BUTTON1 J1BUTTON2 J2BUTTON2 J2BUTTON1 16 16 MIDI_OUT MIDI_IN R88 47 R179 47 C177 470PF C176
R_MIDIOUT
16 16 16 16
C179
R_MIDIIN
C178 47PF
C79 47PF
C182 47PF
REV:
47PF
470PF
R
KEYBOARD/MOUSE/FLOPPYGAME PORTS
DRAWN BY:
1.3
INTEL CORPORATION
2-22-1999_11:02
1
23
OF
40
7
VCC3_3
L26 2 1 FPP1V3
Digital Video Out
C275 C280
C281
+
100PF
100PF
VCC3_3
VCC3_3
10UF
2 L25 FPDV3 24 2 1
2 L27
FPAV3
C282
C276 C277 100PF 100PF
C231 100PF
C271 C272 100PF 100PF

2
C230 10UF
VCC1_8
10UF
1K
R116
VCC1_8
24
FTVREF R126 R165

29 23 49 18 33 12 3 1
R122
1K
Place C226 near U28, pin 3 U7 C226 100PF
C228
400
4.7K Do Not Stuff R126
0.01UF
VREF
PVCC1
PVCC0
VCC2
VCC1
AVCC1
AVCC0
VCC0
1%
C
TXCTXC+ 21 22
36 37 38 39 40 41 42 43 44 45
D23 D22 D21 D20 D19 D18 D17 D16/PFEN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TXCTXC+
25 25
FLAT PANEL TRANSMITTER SII154
TX0TX0+
24 25
TX0TX0+
25 25
TX1TX1+
27 28
TX1TX1+
25 25
FTD[11:0] 9 FTD11 FTD10 FTD9 FTD8 FTD7 FTD6
46 47 50 51 52 53 54 55 58 59 60 61 62 63
TX2TX2+
30 31
TX2TX2+
25 25
EXT_RS
19 EXTRS_PU
FTD5 FTD4 FTD3 FTD2 FTD1 FTD0 FTCLK0 FTCLK1 FTBLNK# FTHSYNC FTVSYNC
DKEN/RST TEST BSEL/SCL DSEL/SDA ISEL MSEN PD
35 34 15 14 13 11 10 9 8 7 6 A1_PD A2_PD A3_PD TEST_PD
PCIRST# 3VFTSCL 3VFTSDA SL_STALL 3VHTPLG
B
13,17,18,24,27 9,24,25 9,24,25 9,24 25
9,24 9,24 9,24 9,24 9,24
56 57 2 4 5
IDCLKIDCLK+
EDGE/CHG CTL1/A1/DK1
DE CTL2/A2/DK2 HS CTL3/A3/DK3 VS AGND2 AGND1 AGND0 PGND GND2 GND1 GND0
32
26
20
17
64
48
16
R113 1K
R118 1K
R121 1K
A
R124 R124 is for Test Only TEST pin may be tied direct to GND 4.7K
Do Not Stuff
A
FPDV3 24
REV:
DIGITAL VIDEO OUT

DRAWN BY:
R
1.3
INTEL CORPORATION
5-26-1999_17:13
24
OF
40
Video Connectors
D
20 Pin Flat Panel Connector

VCC5
VGA Connector
VCC5
BLM11B750S is rated at 75Ohms at 100MHz
L21 VCC5 J8 24 24 TX1+ TX11 2 3 4 11 12 13 C 14 15 16 17 18 19 20 CON_FTSDA CON_FTSCL CON_HTPLG R75 2.2K De-Bounce Circuit 1N5821 CR7 1 BAT54S 3 +
VID_RED VCC1_8
2 BLM11B750S
F1 C111 3.3PF R65 1K 2.5A

1 CRT5V_F
TX2+ TX2-
C109 24 24
Protection Circuit for 20V Tolerance 2
R74 1K
R69 75 1%
3.3PF
L12
J6
6
24 24
TXC+ TXC-
5 6 7 8 9 10
TX0+ TX0-
24 24
CR10
1
6 1 11
L_RED 5VHTPLG 25 9 VID_GREEN VCC1_8 C105 R67

2 Populate if DFP Device is also populated. R105 R103 0K 0K 1 BAT54S 3 1
1 11 7
Place R66,R67,&R69 Close to VGA Connector L20

1 2 BLM11B750S
MONOPU L_GREEN
2 12
C203 0.01UF
C200 10UF
2
C106 3.3PF L_BLUE L_HSYNC FUSE_5 MON2PU L_VSYNC
8 3 13 9 4 14 10 5 5 10 15
75 1%
3.3PF
5VFTSDA 5VFTSCL
24,25 24,25 25 25 5VDDCDA 5VHSYNC
CR9
R71 VCC5 0K C122 3.3PF

2
15
VCC5
C119 3.3PF
CR4
QS4_3V 8 7 6 C 5 A 1N4148
1 BAT54S
Do Not Stuff C119 and C122
R115
C227
0.1UF
4.7K
5V to 3.3V Translation/Isolation
RP34
25 25
5VDDCCL 5VVSYNC VCC5
CR5 R64 0K C102 3.3PF
2.2K
1 2 3 4
B
U6
B
C100 3.3PF C112 C208 10PF C116 10PF C101 10PF
QST3384
VCC 24 2 5 6 9 10 15 16 19 QSSDA 20 QSSCLR120 23 12 0K 2
9 9 9 9 24 9,24 9,24 6 6
3VDDCDA 3VDDCCL CRT_HSYNC CRT_VSYNC 3VHTPLG 3VFTSDA 3VFTSCL CK_SMBDATA CK_SMBCLK
3 4 7 8 11 14 17 18 21 22 1 13
1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 BEA# BEB#
1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 GND
5VDDCDA 5VDDCCL 5VHSYNC 5VVSYNC 5VHTPLG 5VFTSDA 5VFTSCL R119

0K
25 25 25 25 25 24,25 24,25 11,12,14,28,33 11,12,14,28,33

2 1 BAT54S 3
1 BAT54S
10PF Do Not Stuff C100 and C102 L19
CR6 9 VID_BLUE VCC1_8 R66 75 1%

1 2 BLM11B750S
C104 3.3PF
C103 3.3PF
SMBDATA SMBCLK
CR8
2.2K
R59
2.2K
R58 Do Not Populate
REV:
VIDEO CONNECTORS
DRAWN BY:
R
1.3
INTEL CORPORATION
11-23-1998_13:44
1
25
OF
40
AUDIO/MODEM RISER
VCC12 VCC5 VCC3_3 VCC12VCC5 VCC3SBY
J18
B1 B2
AUDIO_MUTE# GND[0] (ISOLATED)
AUDIO_PWRDWN MONO_PHONE RESV[5] RESV[6] RESV[7] GND[7] +5VDUAL/5VSBY USB_OC GND[8] USB+
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
31
AC97SPKR
B3 B4 B5
MONO_OUT/PC_BEEP RESV[1] RESV[2] PRIMARY_DN# -12V GND[1] +12V GND[2] +5VD KEY KEY
B6 B7 B8 B9 B10 B11
C
AC97_OC# AC97_USB+ AC97_USB20 20 20
AC97_RISER
AMR_CONNECTOR
USBKEY KEY GND[9] S/P_DIF_IN GND[10] +3VDUAL/3VSBY GND[11] AC97_SYNC GND[12] AC97_SDATA_IN1 GND[13] AC97_SDATA_IN0 GND[14] AC97_BITCLK
B12 B13 B14 B15 B16
GND[3] RESV[3] RESV[4] +3.3VD GND[4] AC97_SDATA_OUT AC97_RESET# AC97_SDATA_IN3 GND[5] AC97_SDATA_IN2 GND[6] AC97_MSTRCLK
A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23
14 14
AC_SDOUT AC_RST#
B17 B18 B19 B20 B21 B22 B23
AC_SYNC AC_SDIN1 AC_SDIN0 AC_BITCLK
14 14,33 14,33 14
REV:
AUDIO/MODEM RISER
DRAWN BY:
R
1.3
INTEL CORPORATION
11-23-1998_13:44
1
26
OF
40
7
VCC5
6
VCC3SBY VCC3SBY VCC3SBY
5
VCC3SBY
2
VCC3SBY
LAN
13,17,18 AD[31:0] AD0 AD1 AD2 LAN Decoupling AD3 AD4 AD5 AD6 AD7 AD8 AD9 C261 0.1UF C184 0.1UF C165 0.1UF AD10 AD11 AD12 AD13 VCC3SBY AD14 AD15 AD16 AD17 C334 0.1UF VCC3SBY C180 0.1UF C257 0.1UF AD18 AD19 AD20 AD21 AD22 AD23 AD24
1 1
G13
K13
P12
A11
E12
K10
K11
4.7K 5%
N7 M7 P6 P5 N5 M5 P4 N4 P3 N3 N2 M1 M2 M3 L1 L2 K1 E3 D1 D2 D3 C1 B1 B2 B4 A5 B5 B6 C6 C7 A8 B8 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
VCC[0]
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCCPP[0]
VCCPP[1]
VCCPP[2]
VCCPP[3]
VCCPP[4]
VCCPP[5]
VCC[20]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCCPL[0]
VCCPL[1]
VCCPL[2]
VCCPL[3]
VCC[25]
VCCPT
L10
J10
J11
G5
G6
N8
N6
H5
H6
H7
H8
A3
A7
E1
K3
P2
K4
K5
K6
K7
K8
K9
R159
L4
L5
L9
J5
J6
J7
J8
J9
U13
LILED ACTLED SPEEDLED TDP TDN RDP RDN SMBALRT# CSTSCHG PME# FLA0/PCIMODE# FLA1/AUXPWR FLA2 FLA3 FLA4 FLA5 FLA6
A12 C11 B11 C13 C14 E13 E14 B10 C5 A6 J13 J12 K14 L14 L13 L12 M14 M13 N14 P13 N13 M12 M11 P10 N10 M10 P9 F14 F13 F12 G12 H14 H13 FLD5_PD H12 FLD6_PD J14 P7 N9 M8 M9 C8 LANCLKRUN A13 LAN_TEST D13 D14 D12 B12 B14 RBIAS10 B13 RBIAS100 C12 D10 G4 A14 J4 L7 P1 D9 L8 P14 H4 A1
LANAPWR
LILED ACTLED SPEEDLED TDP TDN RDP RDN
28 28 28 28 28 28 28
D
VCC3SBY
Distribute aroung Power Pins Close to 82559.
PCI_PME# R164 3K
13,17,18
82559
FLA7 FLA8/IOCHRDY FLA9/MRST FLA10/MRING# FLA11/MINT FLA12/MCNTSM# FLA13/EEDI FLA14/EEDO FLA15/EESK FLA16 FLD0 FLD1 FLD2 FLD3
VCC3SBY
C
C68
+
U18
93C46 8 VCC EEDI EEDO EESK EECS GND 5 NC2 NC1 7 6
C255
+
Place C68/C255 Close to Ball A10
AD25 AD26 AD27 AD28 AD29 AD30 AD31
EEDI EEDO EESK
3 4 2 1
4.7UF
4.7UF
13,17,18
C_BE#[3:0]
C_BE#0 C_BE#1 C_BE#2 C_BE#3
M4 L3 F3 C4
C/BE0# C/BE1# C/BE2# C/BE3#
FLD4 FLD5 FLD6 FLD7 EECS
Do Not Stuff R162 619 R163 619 EECS
13,17,18,33 13,17,18,33 13,17,18,33 13,17,18,33
FRAME# IRDY# TRDY# DEVSEL# STOP# PAR PIRQ#A PERR# SERR# AD20 PREQ#3 PGNT#3 PCIRST# PCLK_5 LAN_ISOLATE# LAN_RST# L_SMBCLK L_SMBD R153 100
R_LANIDS
F2 F1 G3 H3 H1 J1 H2 J2 A2 A4 C3 J3 C2 G1
FRAME# IRDY# TRDY# DEVSEL# STOP# PAR INTA# PERR# SERR# IDSEL REQ# GNT# RST# CLK
FLCS# FLOE# FLWE# CLKRUN# TEST TEXEC TCK TI TO RBIAS10 RBIAS100 VREF NC11 NC10 NC9
13,17,18,33 13,17,18 13,17,18,33 17,18 13,17,18,33 13,17,18,27 13,33 13,33 7,13,15,16,17,18,19,24 6 28 28 28 28
R154 62K
R152 4.7K
R156 549 R155 619
B9 A9
ISOLATE# ALTRST#
NC8 NC7 NC6
A10 C9
SMBCLK SMBD
NC5 NC4 NC3
VIO
G2
VIO
NC2 NC1
A
LAN_XTAL1
N11
VSSPP[0]
VSSPP[1]
VSSPP[2]
VSSPP[3]
VSSPP[4]
VSSPP[5]
VSSPL[0]
VSSPL[1]
VSSPL[2]
VSSPL[3]
X1
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30] L6
Y2
LAN_XTAL2
P11
X2
C331 25MHZ 22PF
C269 22PF
C265
G7 G8 F10 C10 N12 D11 F11 G9 F4 F5 F6 F7 F8 F9 H10 G14 G10 G11 H11 K12 E10 E11 E4 E5 E6 P8 B3 B7 E2 K2 E7 E8 M6 E9 L11 N1 D4 D7 D8 D5 D6 H9 TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD
REV:
VSS[31]
VSSPT
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[9]
0.1UF
R
LAN
DRAWN BY:
1.3
INTEL CORPORATION
11-23-1998_13:44 1
27
OF
40
5
VCC3SBY
LAN
VCC3SBY
R111 330
D
J9 27 27 27 27
TDP TDN RDP RDN 10 12 9 7 TD+ TDRD+ RJ-45 RD16 RJMAG 15 LI_CR ACT_CR
D
R108 330
JP7_PU JP18_PU
R144 330
JP23_PU
R145 330
R112 330
ACTLED LILED
27,28 JP7 27,28 JP11
JP12
13 14
Place Termination near 82559
R157 50
TD_PD
R158 50
R160 50
RD_PD
R161 50
5 6 3 4
RJ-4 RJ-5 RJ-7 RJ-8 SHLD1 SHLD2
SPEEDLED
27,28 27,28 27,28 LILED ACTLED SPEEDLED
RDC
RXC
TDC
TXC
C266 Do Not Stuff 0.1UF
C268
RJ45_PD
27,28
17
18
0.1UF
RJ78_PD
11 TDC
RXC_PD
C
TXC_PD
RDC
R107 75
R110 75
R106 75
R109 75
C213 0.1UF Do Not Stuff
C212 0.1UF
RJMAG_CONN
VCC3SBY C210 Default Config: Do Not Stuff For EST Testing 470PF-1500V
Note: Chassis Ground, use plane for this signal R215 4.7K JP8
1 2 JP8_SMBC R151 0K
Note: Chassis Ground, use plane for this signal
11,12,14,25,33 14
SMBCLK GPIO27
L_SMBCLK
27
VCC3SBY
Select JP8/JP9 ICH0 1-2 Default ICH 2-3

14 SUS_STAT# R210 0K PWROK R198 0K Do Not Stuff R198 LAN_ISOLATE# R186 4.7K JP9 27 11,12,14,25,33 14 SMBDATA GPIO28
1 2 3 JP9_SMBD R150 0K
14,29,32
L_SMBD
27
JP10 14,32 RSMRST#

1 2 3
LAN DISABLE - JP10 Normal 1-2 Default Disable 2-3

LAN_RST# 27
Note: This circuit is for debug purpose only.
REV:
LAN
DRAWN BY:
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1
28
OF
40
Voltage Regulators
1 +
VCC3_3
V3SB
VCC3SBY
1N5822 A C
VCC 3.3V Standby VOLTAGE SWITCH

D
C174
2
C75
2
CR2
NDS356AP
Q5
G
This generates 3.3V Standby Power which is on in S0,S1,S3,S4,&S5. It passes 3.3V from the ATX supply in S0/S1, and 3.3VSB (generated by VR2 below) in S3/S4/S5.
47UF
47UF
D S D S
Do Not Populate
1 1 2 +
C173
+
C375
NDS356AP D D S
VCC12
S
1200UF
1200UF
4.7K
SN74LVC07A has 5V input and output tolerance.
VCC5SBY
VCC3SBY R87
PLANE_CTL1 4 3
Q9
SI4410DY 5 6 7 8
10K U4
74LS132 1 2 7 GND SN74LVC07A E 14 VCC 3
U5
PCTL_IN 1 7
Q7
VCC 14 2 PLANE_CTL0
C 2 3 MMBT3904LT1 1
VCC5SBY
R61
Q6
VTT 1.5V VOLTAGE REGULATOR

VCC3_3 VTT1_5
14,32 28,32
SLP_S3# PWROK
R83 0K
V_GQ6
1 2
GND
VR5
Q8
SI4410DY 4 3 2 1 5 6 3
LT1587-1_5
VOUT VIN ADJ
7 1 1 100UF-TANT 8 1 2
C43 1.0UF
C270
2
100UF-TANT
C225
2
VCC 3.3VSB Regulator

VCC5SBY V3SB VCC3_3
VCC 1.8 VOLTAGE REGULATOR

VCC1_8
VCC 2.5 VOLTAGE REGULATOR

VCC5 VCC2_5
VR2
LT1587ADJ
VR3
LT1587ADJ 2
VR4
LT1117-3_3 VOUT 3 IN GND 1 100UF-TANT 1 22UF-TANT OUT 2 1 100UF-TANT 3 VIN ADJ 1 1 VR1_ADJ
R55 1% 301
3 VOUT 2
R56 1%
VR5_ADJ +
240
1
C159
VIN ADJ 1
100UF-TANT
C71
2
C76
2
R54 1.0UF 1%
2
C65 Place C159 at the Regulator 0.1UF 1%
R57 240
Place C76 at the Regulator
130
22UF-TANT
C59
C74
2
C57
2
R
REV:
VOLTAGE REGULATORS
DRAWN BY:
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INTEL CORPORATION
11-23-1998_13:44
29
OF
40
4
VCC3_3
3
VCC5
Processor Voltage Regulator

VCC12 VCC5
R33 R22 1.0UH-6.8A 220
R18 5.6K VRM_PWRGD 32
D
L8
5.1
C21
5VIN
1.0UF
1 1 1
R17
10K
C22
2
1 2 +
C27
+
C30
+
C26
+
C29
+
C7
0.1UF
10UF
1200UF
1200UF
1200UF
1200UF
C20
PV12
R20
5 6 7 8 5 D4 6 D3 7 D2 8 D1 D4 D3 D2 D1
0.01UF
5 2
2.7K
VR1
3 VID[3:0] VID0 VID1 VID2 VID3
4 3 2 1 5 6 7 8 14
Place CAPs Close to FETs C24 C25 VCCVID
Q1 SI4410DY
Q2 SI4410DY
VCC
RP4
OUTEN R_VID0 R_VID1 R_VID2 R_VID3
19 18 17 16 15
OUTEN VID0 VID1 VID2 VID3
IMAX PVCC PWRGD FAULT# G1 IFB SENSE
7 13
IMAX
G1
G1
S3
S2
S1
S3
S2
S1
12 20 8 1 11
FAULT#_PU G1 R_VCCVID G2 VFB_PD
1.0UF R19 20
5 6 7 8 5 6 7 8 L_VCCVID
1.0UF L14 0.8UH-20A
COMP
SGND
GND
0K The LTC1753 incorporates internal pull-ups on VID[4:0]. If your VR IC does not incorporate these, they must go on the motherboard.
VID4
G2 VFB
SS
D4
D3
D2
D1
D4
D3
D2
D1
LTC1753
10
Q3 SI4410DY
Q4 SI4410DY
VRCOMP_PD SS_PD G1 4 S3 3 S2 2 S1 1
G1 4
S3 3
S2 2
S1 1
JP2
JP3
JP4
JP5 C18 150PF

R_VRCOMP
R16 8.2K C17 C19 C35 0.01UF 0.1UF 220PF
B
VID Override Jumpers
1 + 2
C147 Do Not Stuff C147 0.1UF
C31 2700UF
C58 2700UF
C28 2700UF
C128 2700UF
C54 2700UF
Refer to VR Supplier for Layout Guidelines
REV:
VRM 8.4
DRAWN BY:
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2-22-1999_11:02
1
30
OF
40
4
VCC3_3
3
VCC5
SYSTEM
ICH has internal pullup and debounce on PWRBTN#
D
R225 14 PWRBTN# 0K
VCC3SBY
C292
2
No stuff. For test only

R226 1M
R217
100K
10UF
16V
C279
D J20
1
0.1UF 16 16 SW2
1 2 4 PBSWITCH PBTN_IN
IRRX IRTX R213 4.7K R212 82

2 R_IRTX 3 4 5 6 7 8 KEY
No stuff. For test only
C370 1.0UF
INFRARED
VCC5
VCC5
VCC3_3
VCC3_3
VCC3_3
POWER SW.
R228 R136 10K 19 IDEACTP# R93 10K R231

14
9 10
470 U11
3 7 VCC 4
11 12
10K
IDE_ACTIVE U11
1 7 VCC 14 2
13 14
KEY
H.D. LED
GND SN74LVC07A
FP_PD
VCC5
15 16 17 KEY
19
IDEACTS#
C
KEY
GND SN74LVC07A
R232
PWRLED
18 19 20 21 22 23
POWER LED
220 16 KEYLOCK#
KEY
KEYLOCK
26
AC97SPKR
24 SPKR_IN 1
KEY
SPEAKER VCC5
R233 68
25 R_SPKRIN 26 FNT_PNL_CONN
JP22
VCC3_3 14
RP62
Q11
SPKR
ICH_SPKR
2 3
R234 R235 2.2K

3 SPKR_Q1G B 1 2 E 2N3904
68 C378 C373 C258

SPKR_NEG 1 2
SP1
+ POS NEG
5 4.7K 4
6 3
7 2
8 1
0.1UF
470PF
470PF
FAN Headers
Speaker Circuit
B
VCC12
VCC12
VCC3SBY
VCC3SBY
VCC3SBY C23 J24

1 2 2 V3SBLED 3
R97
R98
VCC3SBY C363 J26

1 2 3
VCC3SBY 330
0.1UF
0.1UF U5 R188 14 330

CR12 On-Board LED indicates the Standby Well is on to prevent Hot-Swapping Memory. VCC 14 4 GP23LED GND SN74LVC07A 1 2 GP26LED GND SN74LVC07A 6 VCC 14
330
U5
5 7
GPIO23_FPLED
3 7
GPIO26_FPLED 14
16
TACH1
16 VCC12
TACH2 VCC12
CR3 R172 4.7K
A
C362 J27
1 2 3
A
C365 J25
1 2 3
0.1UF
0.1UF
REV:
SYSTEM, PART 1
DRAWN BY:
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16
PWM1
16
PWM2
11-23-1998_13:44
1
31
OF
40
SYSTEM
Power Connector and Reset Control
D
ITP RESET CIRCUIT - FOR DEBUG ONLY VCC3SBY VCC3SBY R99 240
Power Good Circuit

VCC5SBY VCC5 VCC_5VCC12VCC5SBY VCC12 VCC3_3
DBRESET#
1 APOK_ST 2 14 U10 3 7 SN74LVC08A DBRST
VCC2_5 VCC3SBY
U12
14 2 7
ST23
U12
14 4 7
1
74LVC14A
3
74LVC14A
R90 0K VCC5SBY
R10
SN74LVC06A has 5V input tolerance U3 1 7 GND
330
14 VCC 2
VCC3SBY
R62 4.7K
11 12
J4
3_3V11 -12V GND13 PS_0N GND15 GND16 GND17 -5V 5V19 5V20 ATX 3_3V1 3_3V2 GND3 5V4 GND5 5V6 GND7 PW_OK 5VSB 12V 1 2 3 4
74LVC14A is 5V input tolerant
PWRGOOD
DBRPOK
32
SN74LVC06A
U3
14 5
13 VCC 6 5VPSON 14 15 16 17 18 19 20
14,32
SLP_S3#
R91
ATX_PWOK
R92 0K
U4
74LS132 4 DBRPOK_DLY 5 7 14 VCC 6 PWROK#
VCC3SBY
7 GND SN74LVC06A
5 6 7 8 9 10
SN74LVC06A is 5V output tolerance
0K
VCC3SBY
GND
C
R200 4.7K
U3 3 7 GND SN74LVC06A Do Not Stuff For Debug Only
C183 Do Not Stuff C183 1.0UF

14 VCC 4
PWROK
14,28,29
R199 1M
30
VRM_PWRGD
220 Ohm Pull-up to 3.3V is on VRM Sheet
Reset Button
SW1
1 2
R24
3 PBSWITCH 4 RST_PD
22
1
C45 JP23
Place JP23 Near Front Panel Header (J20)
C185 10UF
Resume Reset Circuitry

Schmitt Trigger Logic using a 22msec delay
VCC3SBY VCC3SBY VCC3SBY
0.01UF
CLOCK POWERDOWN CONTROL

14,29,32 SLP_S3# VCC3SBY R86 8.2K
22K R142
U12
V3RSMRST
14 6 7
ST69
U12
9
14 8 7
5
74LVC14A
RSMRST#
14,28
74LVC14A
C264 1.0UF
R196 1M
Do Not Stuff For Debug Only
A
32 DBRPOK
4 5 7 SN74LVC08A 14 U10 6 CK_PWRD
A
R84 0K Do Not Stuff R84 - For Test Only: If R84 is Populated, R86 Must Be De-Populated
REV:
CK_PWRDN#
SYSTEM, PART 2
DRAWN BY:
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12-6-1998_12:54
32
OF
40
PULL-UP RESISTORS AND UNUSED GATES PCI BUS

RP59
18 PERR#_PU SERR# PLOCK# STOP# DEVSEL# TRDY# IRDY# FRAME#
2 3 4 5 6 7 8 9 10
VCC5
ICH0
VCC3SBY RP61 14 14 14 SMBALERT# LDRQ#1 GPIO12 GPIO13
1 2 3 4 8 7 6 5
CPU
4,33
VCC5 RP47 17 17 17 SDONEP1 SDONEP2 SBOP1 SBOP2

1 2 3 4 8 7 6 5
13,17,18,27 13,17,18 13,17,18,27 13,17,18,27 13,17,18,27 13,17,18,27 13,17,18,27
D
VCMOS RP50 4,13 4,13 VCC3_3 4,13 4,13 NMI CPUSLP# STPCLK# SMI#
1 2 3 4 8 7 6 5
2.7K
17
5.6K VCC5
4,13 4,13
APICD0 APICD1 R6 150
R73 150
14
4.7K RP58
9 PULLUP/DOWN RESISTOR PAK
RP60
8 7 6 5
18 18 VCC5 17,18 17,18
SDONEP3 SBOP3 PTDI PTMS
1 2 3 4
11,12,14,25,28 11,12,14,25,28 14 VCC5
SMBDATA SMBCLK INTRUDER#
1 2 3 4
8 7 6 5
RP45
13,17,18 13,17,18 13,17,18 13,17,18,27 13,27 13,18 13,17 13,17 PIRQ#D PIRQ#C PIRQ#B PIRQ#A PREQ#3 PREQ#2 PREQ#1 PREQ#0
2 3 4 5 6 7 8 9 10 9 PULLUP/DOWN RESISTOR PAK
5.6K
4.7K
2.7K
150 RP51 17 17 17 VCC3_3 17 PU1_ACK64# PU1_REQ64# PU2_ACK64# PU2_REQ64#

1 2 3 4 8 7 6 5
RP56 13 13 13,16,18 REQ#B/GPIO1 GNT#B/GPIO17 SERIRQ

1 2 3 4 8 7 6 5
RP49 4,13 4,13,15 4,13 4,13 INTR INIT# IGNNE# A20M#

1 2 3 4 8 7 6 5
2.7K R208 2.7K R207 2.7K PCPCI_REQ#A THERM# RCIN# A20GATE

1 2 3 4
8.2K RP52 13,18 14 13,16 13,16

8 7 6 5
150
RP57 13,17 13,17 13,18 13,27 PGNT#0 PGNT#1 PGNT#2 PGNT#3

1 2 3 4 8 7 6 5
18 18
PU3_ACK64# PU3_REQ64#
4,13
FERR#
R169 150
8.2K 14,16 14,18 LPC_SMI# GPIO7

1 2 3 4
8.2K RP53
8 7 6 5
For Future Compatibility Upgrade
VCC3SBY
UNUSED GATES
B
VCC3_3 VCC3SBY
8.2K RP54
1 8 7 6 5
4 4
RTTCTRL SLEWCTRL R70 110, 1%
R68 110, 1%
VCC3SBY 14
9 14 U10 8
GPIO22 LPC_PME# GPIO21
2 3 4
14,16 14,18
U12
11
10
14 10 7
7 SN74LVC08A
8.2K VCC5
74LVC14A
U11
9 7
VCC 14 8
U5
9 7
VCC 14 8
12
14
U10 11
RP55
1 2 8 7 6 5
U12
13
14 12 7
13 7 SN74LVC08A
GND SN74LVC07A SN74LVC07A
GND
13,19 13,19
IRQ14 IRQ15
3 4
74LVC14A
U11
11 7
VCC 14 10
U5
11 7
VCC 14 10
VCC3SBY
VCC5SBY AC_SDIN0 AC_SDIN1 R166 10K
8.2K
GND
14,26 U4
U3 74LS132 9 14 VCC 10 7 GND 10 7 SN74LVC06A GND 14 VCC 8
R170 10K
14,26
U11
13 7
VCC 14 12
U5
13 7
VCC 14 12 11
GND
A
U4
U3 13 7 GND SN74LVC06A 14 VCC 12 74LS132 12 13 7 GND REV: 14 VCC 11
PULLUP/PULLDOWN RESISTORS
DRAWN BY:
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INTEL CORPORATION
5-26-1999_17:09
33
OF
40
370-pin Socket Decoupling

VCCVID Decoupling
D
Place in 370 PGA Socket Cavity VCCVID Bulk Decoupling
1206 Packages
C125
C152
C136
C117
C110
C115
C153
C146
C126
C139
C155
C140
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
VCCVID High Frequency Decoupling

0805 Package
C
C121 C142 C118 C113 C120 C149 C145 C107 C154 C156 C148 C135 C132 C137 C138 C151 C108 C141 C143 C134
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
VTT Decoupling
0603 Package placed within 200mils of VTT Termination R-packs One Capacitor for every 2 R-Packs
B
VTT1_5
C384 +
C33
C34
C129
C11
C32
C133
C144
C150
C157
C218
C220
C219
C205
C221
C42
22UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
REV:
VRM DECOUPLING
DRAWN BY:
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INTEL CORPORATION
12-8-1998_14:04
34
OF
40
DRAM, CHIPSET, and BULK POWER DECOUPLING

GMCH Decoupling
D
VCC1_8 VCC3_3 Distribute near the power pins of both SDRAM components. VCC3_3
Display Cache Decoupling
ICH0 Decoupling
Distribute near the 1.8V power pins of the ICH0. Distribute near the VCCSUS power pins of the ICH0. VCC3SBY
ICH0 3.3V Plane Decoupling: Place 1 .1uF/.01uF pair in each corner, and 2 on opposite sides close to component if they fit.
VCC1_8
10UF +
0.1UF 2
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF 10UF 10UF 2 2
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
C130
C239
C382
C215
C163
C381
C273 +
C286 +
C244
C243
C247
C232
C251
C252
C223
C249
C319
C307
C295
C296
C10
C345
C332
C308
C304
C41
C305
1 1 1 C289 0.01UF C263 0.1UF C303 0.1UF C171 0.1UF C44
C372
C67 0.1UF
2.2UF
VCC1_8
GMCH Core Plane Decoupling: Place 1 .1uF/.01uF pair in each corner, and 2 on opposite sides close to component if they fit.
C
C131 0.01UF C164 0.01UF C242 0.01UF C237 0.01UF C214 0.01UF C233 0.01UF C380 0.01UF C383 0.01UF
System Memory Decoupling

VCC3SBY
Bulk Power Decoupling

VCC3_3 VCC5 VCC_5VCC12 VCC12-
VCC3_3
GMCH 3.3V IO Decoupling: Place near GMCH Display Cache Quadrant
C82 0.1UF
C83 0.1UF
C85
DIMM0 Decoupling: Distribute near DIMM0 Power Pins.
C86 0.1UF
C87 0.1UF
C66 0.1UF
C72 0.1UF
C70
22UF
C62
C360 0.1UF
C333 0.1UF
C367 0.1UF
C321 0.1UF
22UF
C81 0.1UF
C80 0.1UF
C324 0.1UF
C317 0.1UF
C260 0.1UF
C245 0.1UF
C248 0.1UF
C254 0.1UF
C181 0.1UF
C175 0.1UF
C234 0.1UF
C343 0.1UF
C341 0.1UF
C350 0.1UF
C278 0.1UF
C288 2 0.1UF
3 VOLT Decoupling
B
VCC3SBY Distribute as close as possible to GMCH System Memory Quadrant
22UF + C170 0.01UF C169 0.01UF C262 0.01UF C377 2 0.01UF 1 C77 0.1UF C253 0.1UF C73 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C188
22UF +
22UF
22UF
C69
22UF
+ C84
VCC3SBY
1 C162
VCC3_3
DIMM1 Decoupling: Distribute near DIMM1 Power Pins.
C352
C298
C283
C291
C354
C285
C339
C160
C250
C78
C340
C318
C172
C376
C320
C240
C256
C127
C338
C322
REV:
DRAM, ICH, AND GMCH DECOUPLING

DRAWN BY:
R
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INTEL CORPORATION
5-26-1999_17:09
35
OF
40
Revision History (Changes from Rev 0.7)

She e t De s cription A LL Cosmetic changes to all pages (Re-names nets, re-organized symbol arrangement, etc.) 4
D
She e t De s cription 10 Ganged the tw o CKEs of f of one 4.7K Pull-Up to 3.3V . 11 12 Fixed Symbol Pinout Fixed Symbol Pinout Removed SMBUS pullups f rom this page. There are pullups on page 32. Removed Reset Straps f rom MD lines. 13 Updated Ballout Changed C172 to 0.1UF Cap (HUBREF decoupling) A dded Resistor Site to Pull F16 to GND f or test/debug. 14 Updated Ballout Routed PME# and SMI# to GPIO[13:12] respectively to support w ake events f rom S1. Pull RTCRST# signal f rom input node of f irst RC delay rather than output node (just other side of diode). Moved Clear CMOS to RTCRST# signal and A dded 1K resistor to GND on pin 3 of jumper.
C D
Changed FB1 (f errite bead f or PLL analog isolation) to Inductor L2. Changed value of R36 to 10 ohms. Replaced R21-R23 w ith 1K R-pack (RP50). Replaced R24-26 and R34 w ith RP44. Changed R184 value to 220 ohms Changed Pull-Up/Dow n Resistor V alues on signals to ITP interf ace and grouped into Rpacks/Discretes to make true populate/de-populate Mf g. Option. Floated THERMTRIP# Signal Generate GTLREF w ith 1% resistors. Move f rom page 5 to page 4. Changed BR0# Pull-Dow n to 56Ohm to use existing GTL Term Rpack Slot on sheet 5 A dded Jumper Test Option to GND BSEL line. Change R35 f rom 51Ohm, 1% to 51Ohm, 5% A dded V CMOS Decoupling
Changed V DDA (pin22) of CK-Whitney to 3.3V Supply pet 0.5 Spec. A dded/Modif ied Decoupling and Pow er Isolation Ganged CPU and GMCH Clock Lines Isolated USB/DotCLK pow er (pin 27) f rom SDRA M pow er Changed Pow erDow n control signal to NA ND of SLP_S3# and PWR_OK Change C146 and C147 f rom 10pF to 12pF
Change RTC Circuit to pow er V bias straight f rom positive terminal of battery (BA T1). Was charged f rom V CCRTC input. Changed A C_SY NC pull-dow n strap (CPU Saf e Mode Jumper JP14) to A C_SDOUT pullup strap. Change C8 and C9 to 12pF caps. Tied OC#0 and OC#1 together. A dd jumper straps to SPKR and A C_SY NC Remove Pull-up f rom SLP_S3# signal 15 Updated FWH pinout and labelled symbol as a TSOP Socket. Updated FWH (Socket) Symbol to include FGPI[4:0], routed A TA 66 cable detect to GPI[1:0] and pulled rest dow n through 8.2K. Cominbed Decoupling Caps and reduced to appropriate amount. Changed JP4 to a 2 pole instead of 3 pole jumper. Replace discrete resistors w ith R-packs. Replaced R84-87 w ith RP42. 16 Updated Pinout. Connected new V REF pin to 5V . A dded Decoupling to IRRX/IRTX lines. Routed PME# and SMI# to GPIO[13:12] respectively to support w ake events f rom S1. Routed Game Port to game port header, 2nd Serial Port to serial header, PWM/Tach signals to f an headers, and unused signals to test header. Routed Unused GPIOs signals to test header. Removed JP6 and Grounded CLOCKI. Connected V TR to V CC3.3 (removed f rom V CC3SB w ell) and added pow er decoupling. Pulled SY SOPT pin dow n to GND through 4.7K resistor. Moved Keylock pull-up sheet 31.
REV:
Updated GMCH BallOut Changed GTLREF divider to 1% resistors and GTLREF Decoupling to a 0.1uF (C2) and 0.001UF (C72) in parallel Updated GMCH BallOut HUBREF Generated f rom tw o 1% resistors w ith 0.1uF (C171) at GMCH HUBREF pin. Changed C3 to 20pF Cap Decoupled System Memory 3.3V balls f rom Local Memory 3.3V balls. System Memory quadrant connects to 3.3V sb plane and Local Memory connects to 3.3V plane. Updated GMCH BallOut Connected V CCDA CA and V CCDA signals to 1.8V through f iltering circuitry. Connected V SSDA CA and V SSDA to Digital GND. A dded Reset Strap jumpers to LMD[31:26].
Added Oscillator to DotCLK for Test/Debug option

A
Connected Digital V ideo Out signals Changed R70 to 33Ohm and C4 to 20pF.
REVISION HISTORY, PART 1

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Revision History (Changes from Rev 0.7)

Sheet Description 17 C hanged device num ers (ID SEL w iring) for s lots to AD 16, AD 17, and AD 22. R outed additional s ignals required to AD 22 s lot to s upport ISA bridge tes t card. 18 C hanged device num ers (ID SEL w iring) for s lots to AD 16, AD 17, and AD 22. R outed additional s ignals through 0K res is tors to AD 22 s lot to s upport ISA bridge tes t card. Added Jum per to route PER R # to IC H /IC H 0 if IC H is populated. 19 C onnected pin 34 of each connector to P66D ETEC T and S66D ETEC T(FWH _GPI0 and FWH _GPI1 res pectively). Buffered PC IR ST# s ignal going to pin 1 of ID E connectors to is olate cable loading. R em oved Series Term inations from IR Q lines (pulled into IC H 0). 20 Is olated each VC C input to U SB s tacked connector through dedicated filtering circuitry. Added 47pF EMI caps on U SB data lines . C onnect U SB through Audio/Modem R is er through 0K res is tors . Make OC detect circuitry unique to each port and update polyfus e value. 21 R eplaced D B25 connector w ith 2x13 header s o w e can cable out. SMB R em oved Series Term ination R es is tors from Ack# and Bus y# s ignals . C hanged Pull-ups to 2.2K Added 2nd s erial port and connected both through 2x5 headers to cable out (R em oved 1 D B9 C onnector). Added dis crete s olution to level trans late and route R ing Indicate from Serial ports to IC H for Wake from S3 on s erial m odem . Added MID I/Gam e Port circuitry connected through 2x8 header to cable out. Increas ed C ap values on Keybd/Mous e lines from 100pF to 470pF. C hanged the keyboard and m ous e s ym bols to a PS/2 s tacked connector. C hanged R GB PI filter caps from 22pF to 3.3pF. Added Quick Sw itch to level trans late the C R T Sync, C R T D D C , and Flat Panel D D C Signals . Is olated C K-Whitney from SMBU S in Pow er D ow n through Voltage trans lation Quick Sw itch. C hanged VGA C onnector s ym bol. Added EMI C aps on SYN C and D D C Signals . R outed U SB up the AMR C onnector. R an 5V (ins tead of 5VSB) to Audio Modem R is er. Added s tuffing option AC 97 debug port 34 35 30 Sheet 27 C hanged 93C 46 Pinout. 28 Description
R eplaced R J45 connector and dis crete m agnetics w ith integrated R J45/m agnetics part and connected accordingly. Added LAN D is able Jum per. Added IC H /IC H 0 s calability jum pers .
29
Moved Pow er C onnector to Sheet 32 R eplaced old VC C 5dual circuit, w ith VC C 3Sby C ircuit w hich generates s upply for devices w hich m us t s tay pow ered in S3. R em oved LT1585-3.3 (U 36 on rev0.7). C hanged U 27 from LT1585-1.5 to LT1587-1.5 and changed dis cretes . Added V3SB regulator (generated V3SB from V5SB from ATX pow er s upply). C hanged 1.8V R egulator des ign from LT1585AD J to LT1587AD J and change d dis cretes . C hanged 2.5V R egulator des ign from LT1585AD J to LT1587AD J and changed dis cretes . Added VR M Override Jum pers to VID bus . C hange VR D es ign to VR M8.4 com pliant des ign. U s e LTC 1753 per Linear App N ote. Moved R es et and Pow er circuitry to s heet 32 Added Infrared, Pow er Sw itch, H ard D rive/Pow er LED s , Keylock, and Speaker C ircuitry to C om m on Sys tem H eader. Added 12V Fan H eaders (2 s upporting TAC H outputs , and 2 s upport PWM inputs ). Added D ebug LED to m onitor 3.3VSBY Plane Moved Pull-ups to s heet 33. U pdated new PWR OK/PWR GOOD Generation, R ESET, R SMR ST# circtuitry. Pulled-U p SMBU S interface to 3.3VSby ins tead of 3.3V. R em oved R 164 (FLU SH #) and R 168 (TH ER MTR IP#) pull-ups . R em oved pull-up on PWR GOOD (pulled up on s heet 32). Grouped rem aining pull-ups to 1 1K R pack. C hanged all PC I 3.3V pull-ups to 8.2K per PC I s pec. C om bined like pullups into R -packs w here pos s ible. Added 8.2K pull-ups to SER IR Q and IC H 0 unus ed GPIOs . Added Pull-U p Sites for FLU SH # and 370PGA Socket Pin W35 to VC MOS for future com patibility upgrade. U pdated Proces s or D ecoupling per lates t Guidelines for 370PGA s ocket. Added Sys tem D ecoupling
REV:
31
22
23
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25
32 32 33
26
A

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Revision History (Changes from Rev0.9 to Rev0.95)

De s c r ip t io n Sh e e t 2 Ch a n g e d "V id e o En c o d e r " b o x o n B lo c k Dia g r a m to " Dig ita l V id e o O u t De v ic e " B o x . A d d e d De v ic e Ta b le 3 4
D
De s c r ip t io n Sh e e t 20 Ch a n g e d R1 1 7 ,R1 1 8 ,R1 2 1 ,R1 2 2 f r o m 2 7 o h m to 1 5 o h m- 1 % Re s is to r s 22 23 25 Ch a n g e R2 0 7 f r o m 4 7 K to 1 0 K Mo v e d RP3 1 f r o m p g . 1 6 to p u ll- u p Ke y /Mo u s e lin e s to f ilte r e d V CC5 . A d d e d 4 7 0 p F Ca p s o n MIDI lin e s ( C3 2 7 ,C3 2 8 ) . Mo v e d R6 7 ,R6 8 ,R6 9 f r o m S h e e t 9 . Cle a n e d Up V G A Co n n e c to r S c h e ma tic
D
Ch a n g e d Re f e r e n c e De s ig n a to r o n 3 7 0 - p in S o c ke t f r o m J2 0 to X 1 Ch a n g e d Re f e r e n c e De s ig n a to r o n 3 7 0 - p in S o c ke t f r o m J2 0 to X 1 Ch a n g e d C1 f r o m 2 2 u F,3 0 % to 4 7 u F,1 0 % Ch a n g e d S e r ie s Te r min a tio n Re s is to r V a lu e s f r o m 2 2 O h ms to : R3 7 ,R3 8 ,R5 5 ,R5 6 ,R5 7 =4 3 o h m,2 % ; R3 9 ,R4 0 ,R4 1 ,R4 2 ,R4 3 ,R4 6 ,R4 7 ,R5 8 ,R5 9 ,R6 0 ,R6 1 =3 3 o h m,2 % ; R4 5 ,R4 8 ,R4 9 ,R5 0 ,R5 1 ,R5 2 ,R5 3 ,R5 4 ,R6 3 =3 3 o h m,5 % ; R4 4 ,R2 2 6 =1 0 o h m,5 % Te d REFCL K a n d a d d e d R2 2 6 ( to s e p a r a te te r min a tio n to ICH a n d S IO) . Re n a me d CL K 1 4 to S IO_ CL K 1 4 a n d ICH_ CL K 1 4 f o r e a c h n e w NET o u t o f th e T. Ch a n g e d C1 4 4 a n d C1 8 5 f r o m 4 .7 u F to 2 2 u F. A d d e d Ca p S ite to G MCH Hu b Clk A d d e d 0 K Re s is to r ( R2 3 1 ) in s e r ie s w ith DCL K _ W R
A d d e d Pr o v is io n s to a d d PI Filte r s o n V S Y NC a n d HSY NC L in e s Ch a n g e d 5 V S u p p ly to Q u ic k S w itc h to p u ll- d o w n o n DIO DE o u tp u t. A ls o p u lle d DDC lin e s u p to th e s a me s u p p ly p o w e r in g th e Qu ic k S w itc h . Ch a n g e R1 3 2 ,R1 3 3 f r o m 8 .2 K to 1 K Pu ll- Up s 26 27 28 29 Re mo v e d A C9 7 De b u g Co n n e c to r ( J5 ) Ch a n g e d R4 p u ll- u p f r o m 6 2 K to 4 .7 K a n d a d d e d 0 .1 u F De c o u p lin g to V IO p in ( C2 6 2 ) . A d d e d De c o u p lin g f o r L A N Po w e r ( C3 3 6 - C3 4 1 ) Ch a n g e R1 4 0 /R1 4 1 to 4 .7 K Re s is to r s Mo d if ie d CK _ PW RDW N# G e n e r a tio n Cir c u itr y to p u ll o f f U3 3 NA ND g a te a n d in v e r t th r o u g h U1 3 to g e t c o r r e c t lo g ic le v e l. Pr e v io u s ly it w a s ta p p e d o f f th e b a s e o f B JT Q 6 . Th is w o u ld h a v e ke p t CK _ PW RDW N# f r o m c h a r g in g h ig h e r th a n 0 .7 V ( d r o p a c r o s s B E ju n c tio Ch a n g e d R1 9 1 to 1 0 K , R1 9 2 to 0 K , a n d R1 9 3 to 4 .7 K Ch a n g e d Re f e r e n c e De s ig n a to r o n U1 5 a n d U2 5 to Q9 a n d Q 1 0 r e s p e c tiv e ly . Ch a n g e d Re f e r e n c e De s ig n a to r o n U8 to V R5 , U1 1 to V R3 , a n d U2 7 to V R4 Ch a n g e d C2 6 8 a n d C2 5 9 to 1 .0 u F,X 7 R c a p s A d d e d 2 mo r e S i4 4 1 0 DY FETs in p a r a lle l w ith tw o th e r e ( Q 7 /Q 8 ) Ch a n g e d C1 6 0 - C1 6 3 to 2 7 0 0 u F a n d a d d e d o n e mo r e ( C3 4 2 ) in p a r a lle l. Ch a n g e C1 5 3 to 2 2 0 p F Ch a n g e d c o n n e c tio n s o f COMP a n d S S to s h o w th e m r e tu r n in g d ir e c tly to S G ND p in . A d d e d In d u c to r ( L 1 3 ) to f ilte r 5 V in p u t to V RM 31 Ch a n g e r e f e r e n c e d e s ig n a to r S 1 to S W 1 Ch a n g e C7 9 to 1 .0 u F A d d Fr o n t Pa n e l Du a l L ED Cir c u it c o n tr o lle d b y ICH G PIO s 32 Ch a n g e A TX c o n n e c to r Re f e r e n c e De s ig n a to r f r o m U6 to J2 9 . Ch a n g e r e f e r e n c e d e s ig n a to r S 2 to S W 2 33 Re mo v e d Pu ll- Up s f r o m GPIO 2 3 /GPIO 2 6 Pu lle d L DRQ # 1 Up to 3 .3 V S b y ( in s te a d o f 3 .3 V ) . Ch a n g e d PCI Pu ll- Up Re s is to r ( R9 9 ,R1 0 0 ,RP5 3 ,RP4 6 ,RP4 7 ) v a lu e s f r o m 8 .2 K to 2 .7 K a n d c o n n e c te d to 5 V . A ls o c o n n e c te d RP4 0 a n d RP4 3 to 5 V ( f r o m 3 .3 V ) to ma in ta in c o mp a tib ility w ith mo r e 5 V PCI c a r d s . Re mo v e d RP4 9 ( V ID Pu ll- Up s ) S in c e in te r n a l to L TC1 7 5 3 35 A LL A d d e d a d d itio n a l De c o u p lin g f o r V a r io u s Co mp o n e n ts ( C3 4 3 - C3 8 9 ) Ch a n g e d C2 1 7 - C2 2 0 f r o m 0 .1 u F to 0 .0 1 u F Ch a n g e d Re f e r e n c e De s ig n a to r s o n A ll Fe r r ite B e a d s f r o m FB * to L *.
REV:
8 9
Ch a n g e d Re f e r e n c e De s ig n a to r o n O s c illa to r S o c ke t f r o m U3 4 to X 2 Co r r e c te d Co n n e c tio n o f De b u g O s c illa to r f r o m DDCS DA to DOTCL K NET. Up d a te d Pin Nu mb e r s to ma tc h G MCH 0 .7 EDS B a llo u t A d d e d 0 K Re s is to r ( R2 3 2 ) in s e r ie s w ith L RCL K
A d d e d Ca p S ite to ICH Hu b Clk Re p la c e Be a d FB 2 1 w ith In d u c to r ( L 4 ) - 6 8 n H to c r e a te L C f ilte r ( <1 3 0 kHz ) A d d e d L C f ilte r to 1 .8 V p la n e c o n n e c te d to b a lls U6 a n d E1 9 . Ch a n g e d Te s t O s c illa to r Cir c u it ( U3 4 ) to r e mo v e s h o r te d ju mp e r a n d a d d d e c o u p lin g . Ch a n g e d p in n a me s o n 4 8 MHz o s c illa to r s y mb o l. Mo v e d R6 7 ,R6 8 ,R6 9 to S h e e t 2 5 . 14 Re n a me NET CL K 1 4 to ICH_ CL K 1 4 Re n a me Pin L 1 to V CCSUS 1 a n d Pin N1 to V CCS US2 Re n a me NET G PIO 2 3 to G PIO 2 3 _ FPL ED, a n d NET G PIO2 6 to G PIO 2 6 _ FPL ED Ro u te d L PC_ SMI# a n d L PC_ PME# to G PIO [5 :6 ] r e s p e c tiv e ly f r o m G PIO[1 2 :1 3 ] r e s p e c tiv e ly .
B
30
Ch a n g e d V a lu e o f C1 1 f r o m 0 .1 u F to 1 .0 u F 15 15 16 16 16 17 Ch a n g e d Re f e r e n c e De s ig n a to r o n U9 to X 3 A d d e d 0 K RPA CK ( RP6 8 ) in s e r ie s to G ROUND o n FW H ID lin e s f o r Te s t/De b u g . Ch a n g e d Pin 8 7 Na me f r o m RTS 1 # _ S Y S OP to RTS 1 # a n d Pin 5 0 n a me f r o m G P2 7 /IO _ S MI# /TES T to S P2 7 /IO_ S MI# Re n a me NET CL K 1 4 to S IO _ CL K 1 4 Mo v e d RP3 1 to p g . 2 3 to p u ll- u p K e y /Mo u s e lin e s to f ilte r e d V CC5 . S w a p p e d A CK 6 4 # a n d REQ6 4 # to r o u te to c o r r e c t p in s p e r PCI s p e c .
18
A
S w a p p e d A CK 6 4 # a n d REQ6 4 # to r o u te to c o r r e c t p in s p e r PCI s p e c . Re p la c e d JP6 Ju mp e r w ith 0 K Re s is to r S tu f f in g O p tio n ( R2 3 3 , R2 3 4 ) In s e r te d 0 K S tu f f in g Re s is to r s in S e r ie s w ith A TA 6 6 Ca b le De te c t ( R2 3 5 ,R2 3 6 ) S w a p p e d 7 4 L S 0 7 o u t f o r 7 4 L V C0 7 A a n d c o n n e c te d to 3 .3 V .
19 19

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Revision History (Changes from Rev0.95 to Rev0.99)

S he e t De scrip tio n 4 Changed C1 to 33uF and L2 to 4.7uH. S he e t De scrip tio n Change C330 to a 100pF c ap and S c aled B ac k Dec oupling on power planes 24 to U28.. Connec ted E 21 to V CC_DE T P ull-Up S wapped Connec tivity of F TCLK 0 and F TCLK 1. A dded 0603 Cap S ite on CP UHCLK 25 F ix ed Connec tivity of CR2, CR4, CR5, CR6 and CR7. In all c as es P ins 1 and 2 were s wapped. Rem oved RP 50 and routed TCK and TM S to 330ohm pull-ups in RP 44. Change L8,L9,L10 P art Num ber to B LM 11B 750S Changed Rpac k c onnec tions per Lay out B ac k A nnotation Changed F 3 from 2.0A F us e to 2.5A F us e. Changed R39-R43,R46,R47,R58-R61 to 33ohm , 5% (from 2% ) 27 Rem oved P ull-up from LA NTCK (U29.D14) and m ade No Connec t. R136 m oved to S heet 16 to P ull-up LP CP D (U16.27). Routed CK _P W RDN# to Cloc k Chip (S LP _S 3# thru 8.2K res is tor by default). Rem oved C338,C339,C340,C341 and Changed C336,C337 to 4.7uF P olariz ed Capac itors . A dded 0603 Cap S ite on G M CHHCLK Changed INTA # (U29.H2) from P IRQ #D to P IRQ #A and Changed LA N IDS E L (R142.1) from A D19 to A D20. Changed HUB RE F V oltage Divider Res is tor V alues (R182 and R185) from 1K 28 M ade C74 a 470pF -1500V c ap and added "F or E S T Tes ting" Note. 1% to 301ohm -1% and added A C Dec ouping Dis c rete S ites (C394,C395,R245, R246) A dded 22ohm s eries term (R242) to LTCLK Net (U22.K 22). Changed J28.14 c onnec tion from A CTLE D to S P E E DLE D and Changed R219.1 c onnec tion from V CC3S B Y to A CTLE D M oved C323, C324 to page 34 and m ade C324 0.01uF . A dded P rovis ion for Is olating 82559 either on S US _S TA T# or P W RO K Rem oved L5 and C325. Change C5 to 33uF . Connec t U22.U6 and U22.E 19 29 Changed Referenc e Des ignator U14 to Q 10 and U16 to Q 11. direc t to V CC1_8 P lane. Change U22.A B 21 and U22.A B 23 to c onnec t to V CC1_8. Rem oved S eries Term s on Digital V ideo O ut P ort Renam ed NE T CK _P W RD to IN_U5, and Deleted c onnec tion to U13 pin 9 A dded 0K (R31) in s eries with Debug O s c illator Rem oved CK _P W RDW N# NE T, R240 Routed DC_M D27 (c ore detec t S trap) to 10K to 220 pull-up on V CCDE T net. 14
B
5 6
7 8
C
30
16 19
20
22
Changed C148 from 2.2uF M onolithic to 2.2uF P olariz ed Changed Referenc e Des ignator on B A T1 to X4 (it is a s oc k et footprint ). P ulled Up S US S TA T to 3.3V through 4.7K (R136, whic h was rem oved from LA N page) res is tor and dis c onnec ted from ICH0. Changes to P 66DE TE CT and S 66DE TE CT NE Ts to s upport both Drive and Hos t S ided 80 c onduc tor c able detec tion: A dded C392 and C393 (0.047uF , X7R, 16V , 10% ) to G ND, 0ohm Res is tors in S eries (R235,R236), and 15K P ulldowns (R243,R244) to G ND. F ix ed Connec t ivity of Res is tor R124. US B V 5 Net now Connec t s direc tly to L26 term inal 1, and R124 dis c onnec ted from L26 t erm inal 1. E lim inated unwanted res is tor divider on 5V power pins at US B port. A dded S eries Res is tors (0K ) to dec ouple ICH US B s ignals from s tac k ed c onnec tor if rout ed up A M R c onnec tor. Changed Net Nam e G _ICHRI# to ICHRI#_C
31 32
Connec ted Q 4.{5-8}/Q 7.{5-8}, C193, R150 to Net 5V IN ins tead of direc t to V CC5. A dded 0K Rpac k (RP 69) in S eries to V ID[3:0] pins of V R3. Changed S wit c h S y m bol to 4-pin devic e to m atc h phy s ic al devic e. Changed RefDes U6 to J29. Changed S wit c h S y m bol to 4-pin devic e to m atc h phy s ic al devic e.
A dded provis ion for s ending early powerok to Cloc k P D# pin for c lean P owerup 33 S wapped S IP Rpac k s on CP U and ICH pull-ups to 4-E lem ent Rpac k s per Lay out B ac k A nnot ation Change RP 48 from 1K Rpac k to 330ohm Rpac k , and R202, and R203 from 1K res is tors to 330ohm res is t ors for future upgrade c om patibility . A dded A ddit ional Dec oupling on V CC12- and V CC12
REV:
35

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Revision History:Changes from Rev0.99 and On

Changes from Rev0.99 to Rev1.0
D
- Back Annotated from Layout (Reference Designator Changes/Rpack Routing Swaps) - Changed Series Term Values on CPU and APIC Clocks to 33ohm (Sheet 6) - Changed Series Term Values on Memory, Hub, and DOT Clocks to 22ohm (Sheet 6) - Added 10K Pull-Ups on SLP_S3# and SLP_S5# (Sheet 14) - Added 2 1200uF Caps on VCC3_3SBY Plane (Sheet 29)

- Removed X1, R77, R78, R79 (Debug Oscillator Socket) from Sheet 9 - Connected C377 to VCC3_3SBY Plane - Corrected Pinout of 2x5 Com Port Headers (Sheet 22) - Added 2x1 Header (JP23) to sheet 32 for Chasses Reset Button

- Added RP70 and RP71 to Sheet 8 (SM_MA Series Terms) - Removed 330Ohm Pull-Ups from FLUSH# and TestHi (W35 on 370-Pin Socket) - Added 110Ohm, 1% Pull-Downs to pins S35 and E27 of 370-pin Socket (RTTCTRL and SLEWCTRL) - Changed C347 from a 2200pF Cap to a 0.047uF Cap

B
- Changed VCCDET Net name to VCOREDET - Changed Value of R125 to 174ohm, 1% (from 178ohm, 1%) - Changed value of C347 back to 2200pF Cap (from 0.047uF Cap) - Designated R126 as No Stuff per SiI 154 Specification - Removed R123 pull-up and connected SiI154 pin 13 to reset. - Changed RP50, RP49, and R169 from 330ohm to 150ohm
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Intel 810 Celeron Document For Troubleshooting

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1 2 3,4 5 6 7,8,9 10 11,12 13,14 15 16 17,18 19 20 21 22 23 24 25 26 27,28 29 30 31,32 33 34,35

** PLEASE NOTE THESE SCHEMATICS ARE SUBJECT TO CHANGE

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

FOLSOM, CALIFORNIA 95630 2

Term DATA CTRL

Display Cache Memory GMCH Digital Video Out Device

IDE Primary IDE Secondary

USB Port 1 USB Port 2

PCI CNTRL PCI ADDR/DATA SIO LAN

GATES USED A,B,C,D

A,B A,B,C A,B,C

SHEET NUMBER 32 22 16 29,32 6 7,8,9 13,14 24 27 10 32 25 27 29,32 29,31 19,31 29 29 30 29

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

FOLSOM, CALIFORNIA 95630 2

370PGA Socket Part 1

370-Pin Socket Part 1

HD#59 HD#60 HD#61 HD#62 HD#63

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

370-PIN SOCKET, PART 1

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

FOLSOM, CALIFORNIA 95630 2

370PGA Socket Part 2

ITP Test Port Option

RP2 R8 1K CPURST# R_TCK R_TMS

TDI TDO TRST# 4 ITPREQ# 4 R_TCK R_TMS R4 47 R3 47

AN35 AN37 AN33 AL33

4,5 R21 240 ITPRDY# 4,5

370-Pin Socket Part 2

A20M# STPCLK# CPUSLP# SMI# INTR NMI INIT# FERR# IGNNE#

GTLREF Generation Circuit

G37 L33 N33

S37 U35 U37 V4 W3 W35 X6 Y1 E21 E27 R2 S35 X2

J35 L35 J33 W37 AK26 X4 AG1 C37

VCOREDET SLEWCTRL RTTCTRL 33 33

Place 0603 Package Near VCMOS Processor Pin. C6

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

370-PIN SOCKET, PART 2

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

FOLSOM, CALIFORNIA 95630 2

HD#[63:0] HD#54 HD#55 HD#52 HD#40

HD#56 HD#61 HD#62 HD#46

HD#60 HD#50 HD#53 HD#58

HD#3 HD#12 HD#10 HD#17

HD#57 HD#63 HD#59 HD#48

HD#47 HD#27 HD#44 HD#45

HA#28 HA#13 HA#16 HA#5

HD#49 HD#51 HD#41 HD#42

HA#9 HA#11 HA#7 HREQ#1 3,7

HD#36 HD#22 HD#43 HD#34

HA#8 HA#4 BNR# HA#14 4,7

HD#39 HD#37 HD#38 HD#28

CPURST# HA#26 HA#29 HA#27

TITLE: INTEL(R) 810 CHIPSET CUSTOMER REFERENCE BOARD

PCD PLATFORM DESIGN 1900 PRAIRIE CITY ROAD

PLATFORM COMPONENTS DIVISION LAST REVISED:

FOLSOM, CALIFORNIA 95630 2

DRAM_0 DRAM_1 DRAM_2 DRAM_3 DRAM_4 DRAM_5 DRAM_6 DRAM_7

R43 33 R44 33 R45 33 R46 33

PCI_0 PCI_1 PCI_2 PCI_3 PCI_4 PCI_5 PCI_6

R27 22 R28 22 R29 22 R30 22