Dell Inspiron 17 5755 Compal LA-C142P r1.0 AMD

5 4 3 2 1
PROJECT NAME : Tulip 14",15", 17" / Van Gogh 14", 15"

PCB NO : LA-C142PR04
Vinafix.com
D D
Dell / Compal Confidential

C C
Schematic Document
AMD Carrizo / Carizo-L
AMD EXO XT S3(23 X 23mm)+DDR3L x4
B
2015-02-12 Rev: 1.0 B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/06/10 Deciphered Date 2015/06/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Tulip AAL12 LA-C142P
Date: Friday, February 13, 2015 Sheet 1 of 56
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D 64bit AMD EXO XT D
VRAM 256M*16 FCBGA631 PEG 2.0 x4

DDR3L *4 Page 38,39 25W 23x23mm
Page 33~37
Memory Bus (DDR3L) DDRIII-DIMM X2
One Channel
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
1.35V DDR3L 1600 MHz
Page 13~14
DP0 eDP 8GB
eDP Conn.
Page 16
USB 3.0 Port 1

DP1 DDI AMD USB 3.0 Conn. 1
HDMI Conn. Port 6
Page 17 CARRIZO & "L" Page 23
Processor USB2.0
DP to VGA Port 1 USB 2.0 Conn. 1
CRT Conn. DDI
Page 31 RTD2168
Page 31
BGA 968 On IO/B
Page 25
C
Port 2 USB 2.0 Conn. 2 C
PCI-E On IO/B
x1 x1 Page 25
Port 1 Port 0
Port 4 NGFF 2230
NGFF 2230 Ethernet WiFi/BT4.0
RTL8106E/RTL8111G Page 20
WiFi/BT4.0 10/100 /Giga
Page 20 Page 19
Port 7 Digital Camera
(With Digital MIC) Page 16
Port 5
Touch Screen
Page 16
Port 0 Card Reader

RTS5170 Page 21
Port 3 I2C I2C

SATA HDD Conn. Port 0 SATA Rediver SATA3.0
Page 22 CY7C65211 Page 24
Page 22
Digital Mic.
B B
SATA ODD Conn. Port 1 SATA3.0

Page 22 HD Audio Audio Codec Headphone Jack /
ALC3234 Mic. Jack combo Page 25
Page 18
On IO/B
SPI ROM SPI

8MB Page 10 Page 6~12 Int. Speaker R / L
Page 18
LPC Bus
33MHz
I2C
Int.KBD ENE KBC PS/2

with KBBL KB9022QD Touch Pad
Page 24 Page 27 Page 24
A A

Block diagram
0.3
5 4 3 2 1
5 4 3 2 1
Q2516 ,Q2507 Q135, Q12513 AO3416L

Platform Power Sequence 8 U4 AO4304L
S5_MUX_CTRL
DMN66
U2 LM393
Q2515 , Q2514 AO3416L
+VDDCR_FCH_ALW
0.95VS_PWR_EN#
+0.95Valw ->+0.95VS
LA-C142PR01 UI5/UI7 SY6288
Vinafix.com+5V_USB_PWR1 UL3 SY6288C
D
2014/09/14 A2
+5V_USB_PWR2 +3ALW ->+LAN_VDD33
RTC_CLK
3 AH8
AD8
GFX_VR_ON
D
WOL_EN
USB_EN#
ACIN AG7
PWRGD_VGA
12a
VGATE @ BC17
B5
9c 10a
POK +3VGS
APU_FCH_POK ADD APU_FCH_PWRGD_R 12
A1
A3 BC9 U74 ,AP2821
AC A3 B5 +3VALW 34 110 84 99 98 32 U61
7 +5VALW 10 PXS_PWREN
MODE +19V_VIN 2 BB6
A2
PU703 PU100
+1.8VGS
ISL95520HRZ +19VB APW8822 A2 B4
+17.4V_BATT+
6,20 3,13 APU PU1200 ,APL5930
+3VLP,VL 2 EC_RSMRST#
100 AE4 UC1
PXS_PWREN
DC 8 +VGA_CORE 12a
MODE 4 PBTN_OUT#
B1 122 AE1 PU1100 ,ISL62771
B2 PWRGD_VGA
+17.4V_BATT+ PQ717 +19VB A5 B7 112 UE1 6 PM_SLP_S3#
6 AK7 9 PWROK PGOOD 20
AON6414A EC_ON
EC9022QD PM_SLP_S5#
A4 B6 14 5 AH5
C
6a KB_RST# PWRGD_VGA C
ON/OFF 114 2 AY15
10d PLT_RST# R662

CZ@ AJ3 PR1112
13
APU_RST#_EC Level APU_RST# 1 +1.35V_MEM_GFX
118 U63 D15
DGPU_PWROK 10e PU1400 ,SYX198
18 10b
0.775PW_EN APU_PWRGD_EC Level APU_PWRGD C19 12 DGPU_PWROK
PU800, APL5336 3 17 108 U62 PXS_PWREN
AH1 BB12 AN7 AR14 U15,APE8990
+0.775VALW LDO 10c 12a
PQ801 0.95_1.8VALW_PWREN Ch1 +0.95VSDGPU
121 74 116 95 127 8 SUSP#
R663 Ch2 +1.8VS 8c
PLT_RST#
CZ@
B7
VGATE
7
VR_ON
7a 8e A5
SYSON
11
8 +1.8V_ALW PLT_RST_VGA#
PU200 ,RT8207 7 PXS_RST#
9 SUSP# PU600 ,SY8003 AND Gate AL27
7 +1.35V,+0.675VS
APU_PCIE_RST# UV2 DGPU
B 10d B
9d SUSP#
U2301, APE8990 3
+0.95VALW
+5VS PU300 , RT8237
8a 8b
+3VS
8
9 9c
47K PU500 , ISL62771 +APU_CORE_GFX
VR_ON EN_GFX ENABLE_GFX
8 +APU_CORE_GFX
SUSP# PU400, APL5930 PR532 PR509 VGATE
+1.5VS LDO 8d PGOOD 20 9d
APU_PWRGD
GFX_VR_ON 9c 9 PWROK
+APU_CORE
9a
PU1001
9 ENABLE_APU ISL62771
PR1085 8 +APU_CORE_NB
10c 9b
APU_PWRGD APU_PWRGD_BUF JHDT1 APU_PWRGD
D31 9c 9 PWROK VGATE
A Debug connector PGOOD 20 9d A

Power Sequence diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Tulip AAL12 LA-C142P
5 4 3 2 1
5 4 3 2 1
Board ID Table for AD channel

Vcc 3.3V +/- 1%
Ra 100K +/- 1% BOARD ID Table
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3
Board ID USB3.0
0 0 0.000V 0.000V 0.300V 0x00 - 0x0B
0 Tulip EVT UMA
1
2
12K +/- 1%
15K +/- 1%
0.347V
0.423V
Vinafix.com
0.354V
0.430V
0.360V
0.438V
0x0C
0x1D
- 0x1C
- 0x26
1 Tulip EVT DIS Port1 USB3 connector 1
D 2 Tulip CZL DVT1 D
3 20K +/- 1% 0.541V 0.550V 0.559V 0x27 - 0x30
3 Tulip CZ DVT1 Port2 NA
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3B
4 Tulip CZL DVT2
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3C - 0x46
5 Tulip CZ DVT2 Port3
6 43K +/- 1% 0.978V 0.992V 1.006V 0x47 - 0x54
6 Tulip CZL pilot
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64
7 Tulip CZ pilot Port4
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76
8
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87
9 USB2.0
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96
10 VG EVT
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA3
11 VG DVT1 Port0 Card Reader
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA4 - 0xAD
12 VG DVT2
13 240K +/- 1% 2.316V 2.329V 2.343V 0xAE - 0xB7
13 VG pre-MP Port1 USB connector 2 (D/B)
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xC0
14 VG MP
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC1 - 0xC9
15 Port2 USB connector 3 (D/B)
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD3
16
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD4 - 0xDC
17 Port3 IIC Converter CY7C65211
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDD - 0xE6
C 18 C
19 NC 3.000V 3.300V 3.300V 0xE7 - 0xFF
19 Port4 NGFF Card (WLAN)
SMBUS Control Table
Port5 Touch Screen Panel
SOURCE BATT Charger VGA DIMM USB -> Thermal eDP Touch Touch
I2C Sensor Sensor PAD ULT Port6 USB3 connector 1
EC_SMB_CK1
EC_SMB_DA1
KB9022Q
V V Port7 Camera
EC_SMB_CK2
EC_SMB_DA2
KB9022Q
V V PCI EXPRESS
EC_I2C_TPCLK KB9022Q
EC_I2C_TPDAT Lane 1 10/100 LAN
APU_SCLK0 APU
APU_SDATA0 V Link Lane 2 NGFF Card (WLAN)
APU_SCLK1
APU_SDATA1 APU V V V Lane 3
B
APU_SIC
APU_SID
APU
V V Lane 4
B
Lane 5 PEG (AMD)EXO UL

CLOCK SIGNAL
Lane 6 PEG (AMD)EXO UL
CLKOUT_PCIE0 10/100 LAN
Symbol Note : Lane 7 PEG (AMD)EXO UL
CLKOUT_PCIE1 NGFF Card (WLAN)
: means Digital Ground Lane 8 PEG (AMD)EXO UL
CLKOUT_PCIE2
SATA
: means Analog Ground CLKOUT_PCIE3
SATA0 HDD
SATA1 ODD
A GFX CLK dGPU A

Notes List
0.3
5 4 3 2 1
5 4 3 2 1
SMBus Block Diagram R677 2.2K
R676 2.2K
+3VS 2014/08/28
BA15 APU_SCLK0 202 DIMM1 SMBUS Address [ ]
AY17 APU_SDATA0
Vinafix.com 200
D 202 DIMM2 D
SMBUS Address [ ]
200
RP20.1 2.2K
+3VS_TOUCH
RP20.2 2.2K
Carrizo R686 4.7K

@ RP24.1 2.2K
R685 4.7K
+3VALW 0 @ R122
+3VS
@ R135 0 ohm (@) TP_I2C_CLK
N-MOS
AG5 APU_SCLK1 I2C_CLK TPUSB@ U69
N-MOS SMBUS Address [ ]
AG4 APU_SDATA1 I2C_DAT TP_I2C_DAT USB to I2C
R136 0 ohm (@) Q2505
+3VS
0 @ R123
RP24.2 2.2K
R691 CZ_I2C@
R145 0 TPUSB@ I2C1_SCL_TP_R 6
CZL@ 10K 2.2K R955
+1.8VS JTP
R709 CZ_I2C@ R144 0 TPUSB@ I2C1_SDA_TP_R 7
CZL@ 10K 2.2K R956
RE337
CZ_I2C@
BB10 APU_I2C0_SCL_TP I2C_CLK_TP 0 ohm (CZ_I2C@) I2C1_SCL_TP_R
N-MOS
C APU_I2C0_SDA_TP C
N-MOS
BB9 I2C_DAT_TP
Q2509 CZ_I2C@ 0 ohm (CZ_I2C@) I2C1_SDA_TP_R
+1.8VS RE336
RP25.1
RP25.3
1K
1K
R679 0, CZL@
APU_SIC EC_SMB_CK2
N-MOS
B18
N-MOS
B17 APU_SID
Q79 CZL@ EC_SMB_DA2
R680 0, CZL@ +3VS

+3VS
RPE1.6 R17
RPE1.5 1K
1K
2.2K
2.2K
R16 DIS@ RV5 45.3K
+3VGS
DIS@ RV6 45.3K
QV1
EC_SMB_CK2_R 0 RE42 EC_SMB_CK2 U7
79 N-MOS VGA_SMB_CK3 UV1 GPU SMBUS Address [ ]
B
80 N-MOS U8
B
0 EC_SMB_DA2 VGA_SMB_DA3
RE35
EC_SMB_DA2_R
EC_SMB_CK2
RV164
10 U2407 thermal sensor 0,@ VGA_SMB_CK3_R 8
EC_SMB_DA2
9 UV11 thermal sensor
EC_SMB_CK2 0,@ 7
85 EC_I2C_TPCLK R124 0 ohm (@) TP_I2C_CLK RV165 VGA_SMB_DA3_R
2 UZ1 RTD2168
KBC EC_SMB_DA2
3 DP to VGA
86 EC_I2C_TPCDAT R125 0 ohm (@) TP_I2C_DAT
KB9022QD
RPE1.7 2.2K
+3VALW
RPE1.8 2.2K
PR770
EC_SMB_CK1_R 0 RE31 EC_SMB_CK1
0 ohm 4
77 SCL PU703 POWER
SDA Charger SMBUS Address [ ]
78 0 ohm 3
0 RE33
EC_SMB_DA1_R EC_SMB_DA1 PR769
A PR20 A
100 ohm 6
CLK_SMB PBATT1 BATT SMBUS Address [ ]
100 ohm CONN
DAT_SMB 5
PR18

SMBus block diagram
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
Vinafix.com
D D
UC1B
PCIE
U10 P_GPP_RXP[0] P_GPP_TXP[0] R1 PCIE_ATX_DRX_P0 C224 1 2 .1U_0402_16V7K

<19> PCIE_ARX_DTX_P0 U9 R2 PCIE_ATX_DRX_N0 C225 1 2 PCIE_ATX_C_DRX_P0 <19>
P_GPP_RXN[0] P_GPP_TXN[0] .1U_0402_16V7K LAN
<19> PCIE_ARX_DTX_N0 PCIE_ATX_C_DRX_N0 <19>
T6 P_GPP_RXP[1] P_GPP_TXP[1] R4 PCIE_ATX_DRX_P1 C226 1 2 .1U_0402_16V7K
<20> PCIE_ARX_DTX_P1 T5 R3 PCIE_ATX_C_DRX_P1 <20>
P_GPP_RXN[1] P_GPP_TXN[1] PCIE_ATX_DRX_N1 C227 1 2 .1U_0402_16V7K WLAN
<20> PCIE_ARX_DTX_N1 PCIE_ATX_C_DRX_N1 <20>
T9 P_GPP_RXP[2] P_GPP_TXP[2] N1
T8 P_GPP_RXN[2] P_GPP_TXN[2] N2 6/27 Change to 0.22U, checklist Rev1.0
P7 P_GPP_RXP[3] P_GPP_TXP[3] N4
P6 P_GPP_RXN[3] P_GPP_TXN[3] N3
+0.95VS_APU_GFX R542 1 CZ@ 2 196_0402_1% P_ZVDDP U7 P_ZVDDP P_ZVSS/P_RX_ZVDDP U6 P_ZVSS R73 1 CZL@ 2 1K_0402_1%
+0.95VS_APU_GFX
R404 1 CZL@ 2 1.69K_0402_1% R541 1 CZ@ 2 196_0402_1%
PEG_GTX_C_HRX_P0 P10 P_GFX_RXP[0] P_GFX_TXP[0] M2 PEG_HTX_GRX_P0 C185 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_P0

PEG_GTX_C_HRX_N0 P9 P_GFX_RXN[0] P_GFX_TXN[0] M1 PEG_HTX_GRX_N0 C176 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_N0
PEG_GTX_C_HRX_P1 N6 P_GFX_RXP[1] P_GFX_TXP[1] L1 PEG_HTX_GRX_P1 C215 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_P1

PEG_GTX_C_HRX_N1 N5 P_GFX_RXN[1] P_GFX_TXN[1] L2 PEG_HTX_GRX_N1 C178 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_N1
PEG_GTX_C_HRX_P2 N9 P_GFX_RXP[2] P_GFX_TXP[2] L4 PEG_HTX_GRX_P2 C223 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_P2

C PEG_GTX_C_HRX_N2 N8 L3 PEG_HTX_GRX_N2 C177 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_N2 C
P_GFX_RXN[2] P_GFX_TXN[2]
PEG_GTX_C_HRX_P3 L7 P_GFX_RXP[3] P_GFX_TXP[3] J1 PEG_HTX_GRX_P3 C196 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_P3

PEG_GTX_C_HRX_N3 L6 P_GFX_RXN[3] P_GFX_TXN[3] J2 PEG_HTX_GRX_N3 C175 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_N3
L10 P_GFX_RXP[4] P_GFX_TXP[4] J4

L9 P_GFX_RXN[4] P_GFX_TXN[4] J3
K6 P_GFX_RXP[5] P_GFX_TXP[5] H2
K5 P_GFX_RXN[5] P_GFX_TXN[5] H1
PEG_GTX_C_HRX_P[3..0] K9 P_GFX_RXP[6] P_GFX_TXP[6] G1 PEG_HTX_C_GRX_P[3..0]

<33> PEG_GTX_C_HRX_P[3..0] K8 G2 PEG_HTX_C_GRX_P[3..0] <33>
P_GFX_RXN[6] P_GFX_TXN[6]
PEG_GTX_C_HRX_N[3..0] PEG_HTX_C_GRX_N[3..0]
<33> PEG_GTX_C_HRX_N[3..0] J7 G4 PEG_HTX_C_GRX_N[3..0] <33>
P_GFX_RXP[7] P_GFX_TXP[7]
J6 P_GFX_RXN[7] P_GFX_TXN[7] G3
FP4 REV 0.93
FP4_BGA968
UC1 CZL_2P2G@ UC1 CZ_2P1G@
S IC A8 SERIES AM7410JBY44JBA 2.2G BGA S IC FX-8800P FM880PAAY43KA 2.1G BGA 968P APU Carrizo-L:
SA00008PS1L SA00008T30L PCIe GPP: Four x1 Gen2
B
UC1 CZL_2G@ UC1 CZ_1P8G@
PCIe Discrete Graphics Port: PCI Gen2 x4 B
S IC CARRIZO-L AM7310JBY44JBA 2G BGA S IC A10-8700P AM870PAAY43KA 1.8G BGA 968P APU

SA00008KX0L SA00008T40L
UC1 CZL_1P8G_A4@
CARRIZO-L AM7210JBY44JB 1.8G BGA 968P

SA00008J51L
UC1 CZL_1P8G_E2@
S IC CARRIZO-L EM7110JBY44JBA 1.8G BGA

SA00008KW0L
A A
UC1 CZL_1P5G@
S IC CARRIZO-L EM7010JCY23JBA 1.5G BGA

SA00008KY0L
FP3 PCIE/UMI
Custom 0.3
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

UC1A UC1I
<13,14> DDRAB_SMA[15..0] DDRAB_SDQ[63..0] <13,14>
MEMORY A MEMORY B
AE28 MA_ADD[0] MA_DATA[0] H17 DDRAB_SMA0 AG31 MB_ADD[0] MB_DATA[0] A25DDRAB_SDQ0
Y27 MA_ADD[1] MA_DATA[1] J17 DDRAB_SMA1 AC30 MB_ADD[1] MB_DATA[1] C25 DDRAB_SDQ1
Y29 MA_ADD[2] MA_DATA[2] F20 DDRAB_SMA2 AC31 MB_ADD[2] MB_DATA[2] C27 DDRAB_SDQ2
Y26 MA_ADD[3] MA_DATA[3] H20 DDRAB_SMA3 AB32 MB_ADD[3] MB_DATA[3] D27 DDRAB_SDQ3
W28 MA_ADD[4] MA_DATA[4] E17 DDRAB_SMA4 AA32 MB_ADD[4] MB_DATA[4] B24 DDRAB_SDQ4
W29 MA_ADD[5] MA_DATA[5] F17 DDRAB_SMA5 AA33 MB_ADD[5] MB_DATA[5] B25 DDRAB_SDQ5
W26
U29
W25
Vinafix.com
MA_ADD[6]
MA_ADD[7]
MA_ADD[8]
MA_DATA[6]
MA_DATA[7]
K18
E20
DDRAB_SMA6 AA31
DDRAB_SMA7 Y33
DDRAB_SMA8 AA30
MB_ADD[6]
MB_ADD[7]
MB_ADD[8]
MB_DATA[6]
MB_DATA[7]
B27 DDRAB_SDQ6
A27 DDRAB_SDQ7
U26 MA_ADD[9] MA_DATA[8] A21 DDRAB_SMA9 W32 MB_ADD[9] MB_DATA[8] A29 DDRAB_SDQ8
D AG29 MA_ADD[10] MA_DATA[9] C21 DDRAB_SMA10 AG32 MB_ADD[10] MB_DATA[9] C29 DDRAB_SDQ9 D
U27 MA_ADD[11] MA_DATA[10] C23 DDRAB_SMA11 Y32 MB_ADD[11] MB_DATA[10] B32 DDRAB_SDQ10
T28 MA_ADD[12] MA_DATA[11] D23 DDRAB_SMA12 W33 MB_ADD[12] MB_DATA[11] D32 DDRAB_SDQ11
AK26 MA_ADD[13] MA_DATA[12] B20 DDRAB_SMA13 AL31 MB_ADD[13] MB_DATA[12] B28 DDRAB_SDQ12
T26 MA_ADD[14]/MA_BG[1] MA_DATA[13] B21 DDRAB_SMA14 W30 MB_ADD[14]/MB_BG[1] MB_DATA[13] B29 DDRAB_SDQ13
T25 MA_ADD[15]/MA_ACT_L MA_DATA[14] B23 DDRAB_SMA15 V32 MB_ADD[15]/MB_ACT_L MB_DATA[14] A31 DDRAB_SDQ14
MA_DATA[15] A23 MB_DATA[15] C31 DDRAB_SDQ15
MA_DATA[16] G22 MB_DATA[16] E30 DDRAB_SDQ16

AG26 MA_BANK[0] MA_DATA[17] H22 AH32 MB_BANK[0] MB_DATA[17] E31 DDRAB_SDQ17
AG27 E25 <13,14> DDRAB_SBS0# AG33 G33 DDRAB_SDQ18
MA_BANK[1] MA_DATA[18] MB_BANK[1] MB_DATA[18]
T29 G25 <13,14> DDRAB_SBS1# W31 G32 DDRAB_SDQ19
MA_BANK[2]/MA_BG[0] MA_DATA[19] MB_BANK[2]/MB_BG[0] MB_DATA[19]
J20 <13,14> DDRAB_SBS2# C33 DDRAB_SDQ20
MA_DATA[20] MB_DATA[20]
E19 E22 <13,14> DDRAB_SDM[7..0] D25 D33
MA_DM[0] MA_DATA[21] DDRAB_SDM0 MB_DM[0] MB_DATA[21] DDRAB_SDQ21
D21 MA_DM[1] MA_DATA[22] H23 DDRAB_SDM1 D29 MB_DM[1] MB_DATA[22] G30 DDRAB_SDQ22
K21 MA_DM[2] MA_DATA[23] J23 DDRAB_SDM2 E33 MB_DM[2] MB_DATA[23] G31 DDRAB_SDQ23
F29 MA_DM[3] DDRAB_SDM3 J33 MB_DM[3]
AP28 MA_DM[4] MA_DATA[24] F26 DDRAB_SDM4 AR30 MB_DM[4] MB_DATA[24] J30 DDRAB_SDQ24
AV26 MA_DM[5] MA_DATA[25] E27 DDRAB_SDM5 AW30 MB_DM[5] MB_DATA[25] J31 DDRAB_SDQ25
AR22 MA_DM[6] MA_DATA[26] J26 DDRAB_SDM6 BC30 MB_DM[6] MB_DATA[26] L33 DDRAB_SDQ26
BC22 MA_DM[7] MA_DATA[27] J27 DDRAB_SDM7 BC26 MB_DM[7] MB_DATA[27] L32 DDRAB_SDQ27
K29 MA_DM[8] MA_DATA[28] H25 N33 MB_DM[8] MB_DATA[28] H32 DDRAB_SDQ28
MA_DATA[29] E26 MB_DATA[29] H33 DDRAB_SDQ29
H19 MA_DQS_H[0] MA_DATA[30] G28 B26 MB_DQS_H[0] MB_DATA[30] L30 DDRAB_SDQ30
G19 G29 <13,14> DDRAB_SDQS0 A26 L31 DDRAB_SDQ31
MA_DQS_L[0] MA_DATA[31] MB_DQS_L[0] MB_DATA[31]
B22 <13,14> DDRAB_SDQS0# B30
MA_DQS_H[1] MB_DQS_H[1]
A22 AN26 <13,14> DDRAB_SDQS1 A30 AN31 DDRAB_SDQ32
F23 AP29 <13,14> DDRAB_SDQS1# F32 AP32 DDRAB_SDQ33
MA_DQS_H[2] MA_DATA[33] MB_DQS_H[2] MB_DATA[33]
E23 AR26 <13,14> DDRAB_SDQS2 E32 AT32 DDRAB_SDQ34
G27 AP24 <13,14> DDRAB_SDQS2# K32 AU32 DDRAB_SDQ35
F27 AN29 <13,14> DDRAB_SDQS3 J32 AN33 DDRAB_SDQ36
AP25 AN27 <13,14> DDRAB_SDQS3# AR32 AN32 DDRAB_SDQ37
C AP26 AR29 <13,14> DDRAB_SDQS4 AR33 AR31 DDRAB_SDQ38 C
AW27 AR27 <13,14> DDRAB_SDQS4# AW32 AT33 DDRAB_SDQ39
AV27 <13,14> DDRAB_SDQS5 AW33
MA_DQS_L[5] MB_DQS_L[5]
AV22 AU26 <13,14> DDRAB_SDQS5# BA29 AU30 DDRAB_SDQ40
AU22 AV29 <13,14> DDRAB_SDQS6 AY29 AV32 DDRAB_SDQ41
BA21 AU25 <13,14> DDRAB_SDQS6# BA25 BA33 DDRAB_SDQ42
AY21 AW25 <13,14> DDRAB_SDQS7 AY25 AY32 DDRAB_SDQ43
L27 AU29 <13,14> DDRAB_SDQS7# P32 AU33 DDRAB_SDQ44
L26 MA_DQS_L[8] MA_DATA[45] AU28 N32 MB_DQS_L[8] MB_DATA[45] AU31 DDRAB_SDQ45
MA_DATA[46] AW26 MB_DATA[46] AW31DDRAB_SDQ46
AE25 MA_CLK_H[0] MA_DATA[47] AT25 AE33 MB_CLK_H[0] MB_DATA[47] AY33 DDRAB_SDQ47
AE26 <13> DDRA_CLK0 AE32
MA_CLK_L[0] MB_CLK_L[0]
AD26 AV23 <13> DDRA_CLK0# AE30 BC31 DDRAB_SDQ48
MA_CLK_H[1] MA_DATA[48] MB_CLK_H[1] MB_DATA[48]
AD27 AW23 <13> DDRA_CLK1 AE31 BB30 DDRAB_SDQ49
MA_CLK_L[1] MA_DATA[49] MB_CLK_L[1] MB_DATA[49]
AB28 AV20 <13> DDRA_CLK1# AD32 BB28 DDRAB_SDQ50
AB29 AW20 <14> DDRB_CLK0 AD33 AY27 DDRAB_SDQ51
AB25 AR23 <14> DDRB_CLK0# AC33 BB32 DDRAB_SDQ52
AB26 AT23 <14> DDRB_CLK1 AC32 BA31 DDRAB_SDQ53
AR20 <14> DDRB_CLK1# BC29 DDRAB_SDQ54
N29 MA_RESET_L MA_DATA[55] AT20 T33 MB_RESET_L MB_DATA[55] BB29 DDRAB_SDQ55
AE29 <13,14> MEM_MAB_RST# AG30
MA_EVENT_L MB_EVENT_L
BB23 <13,14> MEM_MAB_EVENT# BB27 DDRAB_SDQ56
P27 MA_CKE0 MA_DATA[57] BB22 U32 MB_CKE0 MB_DATA[57] BB26 DDRAB_SDQ57
P29 BB20 <13,14> DDRAB_CKE0 U33 BB24 DDRAB_SDQ58
MA_CKE1 MA_DATA[58] MB_CKE1 MB_DATA[58]
AY19 <13,14> DDRAB_CKE1 AY23 DDRAB_SDQ59
MA_DATA[60] BA23 MB_DATA[60] BA27 DDRAB_SDQ60
MA_DATA[61] BC23 MB_DATA[61] BC27 DDRAB_SDQ61
AK27 MA0_ODT[0] MA_DATA[62] BC21 AL30 MB0_ODT[0] MB_DATA[62] BC25 DDRAB_SDQ62
AL26 BB21 <13> DDRA_ODT0 AM32 BB25 DDRAB_SDQ63
MA0_ODT[1] MA_DATA[63] MB0_ODT[1] MB_DATA[63]
AH25 <13> DDRA_ODT1 AJ32
MA1_ODT[0] MB1_ODT[0]
AL25 K26 <14> DDRB_ODT0 AM33 N30
MA1_ODT[1] MA_CHECK[0] MB1_ODT[1] MB_CHECK[0]
K28 <14> DDRB_ODT1 N31
MA_CHECK[1] MB_CHECK[1]
B AH26 MA0_CS_L[0] MA_CHECK[2] N26 AJ33 MB0_CS_L[0] MB_CHECK[2] R33 B
AL29 N28 <13> DDRA_SCS0# AL32 R32
MA0_CS_L[1] MA_CHECK[3] MB0_CS_L[1] MB_CHECK[3]
AH29 J29 <13> DDRA_SCS1# AJ30 M32
AL28 K25 <14> DDRB_SCS0# AL33 M33
L29 <14> DDRB_SCS1# R30
MA_CHECK[6] MB_CHECK[6]
MA_CHECK[7] N25 MB_CHECK[7] R31
AG24 MA_RAS_L/MA_RAS_L_ADD[16] AH33 MB_RAS_L/MB_RAS_L_ADD[16]
AK29 <13,14> DDRAB_SRAS# AK32
MA_CAS_L/MA_CAS_L_ADD[15] MB_CAS_L/MB_CAS_L_ADD[15]
AH28 <13,14> DDRAB_SCAS# AJ31
MA_WE_L/MA_WE_L_ADD[14] MB_WE_L/MB_WE_L_ADD[14]
<13,14> DDRAB_SWE#
B19 AD29 +VREF_DQ APU_MAB_VREFDQ A19 AF32 MEM_MAB_ZVDDIO 1 2

T32
MA_VREFDQ MA_ZVDDIO_MEM_S 15mil T45 MB_VREFDQ MB_ZVDDIO_MEM_S
+1.35V
M_VREF R75
+MEM_VREF
39.2_0402_1%
FP4 REV 0.93 FP4 REV 0.93
FP4_BGA968 FP4_BGA968 Place them close to APU within 1"
RZ1049 1 CZ@ 2 0_0402_5% APU_MAB_VREFDQ
Carrizo: Carrizo-L(CHANNEL B ONLY):
EVENT# pull high +1.35V 0.675V reference voltage ‧

DDR3 - Dual Channel
‧ Up to 2133 ‧‧
DDR3 - Single Channel
Up to 1866
+1.35V
‧
‧
Up to 2 DIMMs/Channel
‧‧Up to 2 DIMMs/Channel
2
A R5 uDIMM and SO-DIMM/DRAM down uDIMM and SO-DIMM/DRAM down A

1K_0402_1% +MEM_VREF
R6 1 2 1K_0402_5% MEM_MAB_EVENT# 1.35V and 1.5V 1.35V and 1.5V
15mil
1
2
R8
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
1K_0402_1% C29 C30 Issued Date 2014/06/10 2015/06/30 Title
1000P_0402_50V7K Deciphered Date
2 1
0.1U_0402_16V7K
FP3 DDRIII MEMORY I/F
1
Custom 0.3
5 4 3 2 1
A B C D E
Main Func = CPU DP2 is not supported on Carrizo-L BOM Config change for EVT1 Only +3VS
DP2: VGA Translator
2
APU_HDMI_CLK_C
APU_HDMI_CLK_C <31>
APU_HDMI_DATA_C CZ@
DP1: HDMI APU_HDMI_DATA_C <31>
0_0402_5% RC7
CZ25 CZ32 RZ1045 RZ1047 DP0: eDP RC9 1 CZL@ 2 2.2K_0402_5%
CRT@ CRT@ CRT@ CRT@ APU_HDMI_CLK_C 1 HDMI@ 2
APU_HDMI_CLK <17>
1
APU_HDMI_DATA_CR704 1 20_0402_5% 3 1
D
PANEL_BKLEN_EC
0_0402_5% 0_0402_5% 0.1U_0402_16V7K 0.1U_0402_16V7K APU_HDMI_DATA <17> PANEL_BKLEN <27>
和CZ16,CZ17 Co-lay
CZ30 CZ31 RZ1046 RZ1048
For SIC, SID, ALERT_L, PROCHOT_L R705 HDMI@ 0_0402_5%
CZ@ QC1 MESS138W-G_SOT323-3
CRT@ CRT@ CRT@ CRT@ Carrizo: Each are pulled up to VDD_18 R704, R705
G
Vinafix.com
2
+3VS
0_0402_5% 0_0402_5% 0.1U_0402_16V7K 0.1U_0402_16V7K Carrizo-L: Each are pulled up to VDD_33 UC1C +1.8VS +1.8VS
DISPLAY/SVI2/JTAG/TEST
2
1
CZ12~CZ15 Co-lay CV184~CV187 Place near APU
CZ@ 1
B6 DP2_TXP[0] DP_ZVSSA9 DP_ZVSS R400 1 2 2K_0402_1% RC8
5
RZ1045 1 @ 2 0_0402_5% APU_DP1_TXP0_VGA CZ25 2 1 0.1U_0402_16V7K
APU_DP1_TXP0 A6 DP2_TXN[0] DP_AUX_ZVSS B9 DP_AUX_ZVSS R401 1 2 150_0402_1% EDP_HPD_R 1 CZL@ 2DP0_HPD U66 2.2K_0402_5%
<31> DP1_TXP0_CRT 1 @ 2 0_0402_5% APU_DP1_TXN0_VGA CZ30 2 1 0.1U_0402_16V7K
RZ1046 APU_DP1_TXN0 DP_BLON G5 PANEL_BKLEN_EC RC10 0_0402_5% 1
P
<31> DP1_TXN0_CRT
1
D7 NC
HDMI@ DP2_TXP[1] DP_DIGON G6 ENVDD_R 4 EDP_HPD_R
1 @ 2 0_0402_5% APU_DP1_TXP1_VGA CZ32 2 HDMI@
1 0.1U_0402_16V7K C7 Y
RZ1047 APU_DP1_TXP1 DP2_TXN[1] DP_VARY_BL F11 INVTPWM_R <16> DP0_HPD DP0_HPD 2
<31> DP1_TXP1_CRT A
G
RZ1048 1 @ 2 0_0402_5% APU_DP1_TXN1_VGA CZ31 2 1 0.1U_0402_16V7K
APU_DP1_TXN1 CZ@ 1 R366 2
<31> DP1_TXN1_CRT A7
HDMI@ DP2_TXP[2] NL17SZ07DFT2G_SC70-5 100K_0402_5%
3
HDMI@ B7 DP2_TXN[2] DP2_AUXP H9 SA00004BV00 @
DP2_AUXN G9
D9 E9 +1.8VS +1.8VS
Place near APU C9
DP2_TXP[3] DP2_HPD
DP2_TXN[3]
DP1_TXP0_C CV184 2 @1 0.1U_0402_16V7K APU_DP1_TXP0_VGA DP1_AUXP F7 APU_HDMI_CLK_C
<17> DP1_TXP0_C
5
DP1_TXN0_C CV185 2 @1 0.1U_0402_16V7K APU_DP1_TXN0_VGA APU_DP1_TXP0 A2 DP1_TXP[0] DP1_AUXN E7 APU_HDMI_DATA_C U64 U65
<17> DP1_TXN0_C APU_DP1_TXN0 A3 F5 1 1
DP1_TXN[0] DP1_HPD
P
DP1_TXP1_C CV186 2 @1 0.1U_0402_16V7K APU_DP1_TXP1_VGA
DP1_HPD <17,31> VDD_33 NC 4 NC 4
<17> DP1_TXP1_C DP1_TXN1_C CV187 2 Y ENVDD <16> Y INVTPWM <16>
@1 0.1U_0402_16V7K APU_DP1_TXN1_VGA APU_DP1_TXP1 B4 DP1_TXP[1] DP0_AUXP F8 ENVDD_R 2 INVTPWM_R 2
<17> DP1_TXN1_C A A
G
APU_DP1_TXN1 A4 DP1_TXN[1] DP0_AUXN E8 EDP_AUXP <16> CZ@ CZ@
DP0_HPD G8 EDP_HPD_R EDP_AUXN <16> NL17SZ07DFT2G_SC70-5 NL17SZ07DFT2G_SC70-5
VDD_33
3
CV184 CV186 DP1_TXP2_C CV188 2 1 HDMI@ 0.1U_0402_16V7K APU_DP1_TXP2 D5 DP1_TXP[2] SA00004BV00 SA00004BV00
<17> DP1_TXP2_C
HDMI@ HDMI@ DP1_TXN2_C CV189 2 1 HDMI@ 0.1U_0402_16V7K APU_DP1_TXN2 C5 DP1_TXN[2] RSVD_1 K24 CORETYPE
<17> DP1_TXN2_C E15 TEMPIN0 +3VS
TEMPIN0
0_0402_5% 0_0402_5% T28
DP1_TXP3_C CV190 2 1 HDMI@ 0.1U_0402_16V7K APU_DP1_TXP3 A5 DP1_TXP[3] TEMPIN1 E14 TEMPIN1 RP45
<17> DP1_TXP3_C T29
CV185 CV187 DP1_TXN3_C CV191 2 1 HDMI@ 0.1U_0402_16V7K APU_DP1_TXN3 B5 DP1_TXN[3] TEMPIN2 E12 TEMPIN2 ENVDD 1 2 8
PANEL_BKLEN_EC 1 1 CZL@ 2 ENVDD
ENVDD_R
<17> DP1_TXN3_C T30
HDMI@ HDMI@ TEMPINRETURN F14 TEMPINRETURN R1160 CZ@ ENVDD_R 7 2 R683
T31
EDP_TXP0 E2 DP0_TXP[0] TEST410 AK24 APU_TEST410 4.7K_0402_5% 6 3 0_0402_5%
0_0402_5% 0_0402_5% <16> EDP_TXP0 T32
EDP_TXN0 E1 DP0_TXN[0] TEST411 AL24 APU_TEST411 INVTPWM 1 2 5 4 INVTPWM_R 1 CZL@ 2 INVTPWM
<16> EDP_TXN0 T33
eDP TEST4 P24 APU_TEST4 R1161 CZ@ R703
T34
HDMI/ CRT COLAY EDP_TXP1 E3 DP0_TXP[1] TEST5 N24 APU_TEST5 4.7K_0402_5% 100K_0804_8P4R_5% 0_0402_5%
<16> EDP_TXP1 T35
EDP_TXN1 E4 DP0_TXN[1] TEST6 AN24 APU_TEST6
<16> EDP_TXN1 T36 +3VALW
TEST9 AB8 APU_TEST9
T38
D1 Y9 APU_TEST10
2 D2
DP0_TXP[2] TEST10
B10 APU_TEST14
T39
CORETYPE 1 @ 2
For DP_VARY_BL, DP_BLON, DP_DIGON 2
DP0_TXN[2] TEST14
2014/08/12 Modify TEST15 D11 APU_TEST15 T40 R654 Carrizo: VDD_18 level at the APU
C1 A10 APU_TEST16 100K_0402_5%
+1.8VS Place resistor(0ohm) for SVT on VRM side B1
DP0_TXP[3]
DP0_TXN[3]
TEST16
TEST17 C11 APU_TEST17 Carrizo-L: VDD_33 level at the APU

TEST11 B11 APU_TEST11
R673 1 @ 2 0_0402_5% APU_SVT_R C15 SVT0 TEST18 A14 APU_TEST18
1 2 <48> APU_SVT
@ APU_SVT R669 1 2 33_0402_5% APU_SVC_R D17 SVC0 TEST19 B14 APU_TEST19
<48> APU_SVC
R2 R670 1 2 33_0402_5% APU_SVD_R D19 SVD0 @ RP30
<48> APU_SVD APU_TEST14 8 1
1K_0402_5%
1 @ 2 APU_SVC R682 1 CZ@ 2 0_0402_5% GFX_SVT_R B15 A13 APU_TEST28_H APU_TEST16 7 2
R9
<49> GFX_SVT
R675 1 CZ@ 2 33_0402_5% GFX_SVC_R B16
SVT1
SVC1
TEST28_H
TEST28_L B13 APU_TEST28_L

T43
APU_TEST17 6 3
For DP_STEREOSYNC/TEST36
<49> GFX_SVC T42
1K_0402_5%
<49> GFX_SVD
R681 1 CZ@ 2 33_0402_5% GFX_SVD_R A18 SVD1 TEST31 P26 APU_TEST31
T41
APU_TEST11 5 4 Carrizo: Pulled up (DNI) to VDD_18
1 @ 2 APU_SVD E11 APU_TEST36
R10 APU_SIC B18 SIC
DP_STEREOSYNC/TEST36
TEST37 A17 APU_TEST37 1K_0804_8P4R_5%

Carrizo-L: Pulled up (DNI) to VDD_33
1K_0402_5% APU_SID C17 SID
+1.8VS <9> APU_RST# 1 2 300_0402_5% APU_RST# D15 1

+1.8VS R80 RESET_L APU_TEST36 CZ@ 2 +1.8VS
R82 1 2 300_0402_5% APU_PWRGD C19 PWROK
+1.8VS R155
+1.8VS
1K_0402_5%
1 2 <9,48,49> APU_PWRGD A15 APU_COREGFX_SEN_H <49> APU_TEST37 1 2 1
@ GFX_SVT PROCHOT_L @ CZL@ 2 +3VS
<9,27,41,42,48,49> H_PROCHOT# APU_ALERT# B17
R13 ALERT_L
T44 R117 R120
1K_0402_5% VDDCR_GFX_SENSE H11 APU_COREGFX_SEN_H 1K_0402_5% 1K_0402_5%
1 @ 2 GFX_SVC APU_TDI H15 TDI VDDCR_NB_SENSEJ12 1 @ 2 1 2
H14 APU_VDDNB_SEN <48>
R14 APU_TDO TDO VDDCR_CPU_SENSEG12 R118 R154
APU_TCK D13 AY18 APU_VDD_SEN <48>
1K_0402_5% TCK VDDP_SENSE
VDDP_SENSE 1K_0402_5% 1K_0402_5%
1 @ 2 GFX_SVD +1.8VS APU_TMS G15 TMS
T46 @
R15 APU_TRST# J14 TRST_L VSS_SENSE H12
C13 APU_VDD_RUN_FB_L <48>
1K_0402_5% APU_DBRDY DBRDY
APU_DBREQ# A11 DBREQ_L R20
5
1 2
+1.8VS APU_COREGFX_SEN_L <49>
CZ@
G
RP25 EC_SMB_CK2 3 4 APU_SIC 0_0402_5%

D
3 8 1 APU_SID Q79A CZ@ FP4 REV 0.93 3

2
7 2 APU_ALERT# DMN63D8LDW_SOT363-6 FP4_BGA968

6 3 APU_SIC
G
5 4 EC_SMB_DA2 6 1 APU_SID
D
Q79B CZ@ APU_TRST#_R

1K_0804_8P4R_5% DMN63D8LDW_SOT363-6
CZ@ 1 HDT+ HDT+ Debug conn - HDT@
1000P_0402_50V7K
C936
EC_SMB_CK21 CZL@ 2 APU_SIC
+3VS <27,28,31,34> EC_SMB_CK2
R679 HDT@
0_0402_5%
1 CZL@ 2 APU_ALERT# EC_SMB_DA21 CZL@ 2 APU_SID 2 +1.8VS
<27,28,31,34> EC_SMB_DA2
R134 R680 JHDT1 CONN@
1K_0402_5% 0_0402_5% 1 2 APU_TCK
1 2 +1.8VS
R16 1 @ 2 1K_0402_5% EC_SMB_CK2 3 4 APU_TMS RP28
R17 1 @ 2 1K_0402_5% EC_SMB_DA2 3 4 APU_TCK 1 8
5 6 APU_TDI APU_TMS 2 7
PU at EC side 5 6 APU_TDI 3 6
7 8 APU_TDO APU_DBREQ# 4 5
HDT@ 7 8 HDT@
APU_TRST# 1 2 APU_TRST#_R 9 10 APU_PWRGD_BUF1 D31 2 APU_PWRGD 1K_0804_8P4R_5%
1 CZL@ 2 H_PROCHOT# R671 33_0402_5% 9 10 DB2J31400L_SOD323-2 HDT@
R158 R52 1 2 11 12 APU_RST#_BUF 1 D32 2 APU_RST# +1.8VS
+1.8VS 1K_0402_5% HDT@ 10K_0402_5% 11 12 DB2J31400L_SOD323-2 RP27
+3VALW_EC+1.8VS R49 1 2 13 14 APU_DBRDY HDT@ 1 8
1 CZ@ 2 H_PROCHOT# HDT@ 10K_0402_5% 13 14 APU_TRST# 2 7
1
R159 R51 1 2 15 16 APU_DBREQ#_R 1 HDT@ 2 APU_DBREQ# APU_TEST19 3 6

1K_0402_5% HDT@ 10K_0402_5% 15 16 R672 33_0402_5% APU_TEST18 4 5
R7 17 18 APU_TEST19
+3VALW_EC+1.8VS 4.7K_0402_5% 17 18 1K_0804_8P4R_5%
5
U63 @ 19 20 APU_TEST18 HDT@

2
19 20
1
1
P
4 NC 4 APU_RST# APU_TRST# 1 2 4
R4 APU_RST#_EC 2 Y
<27> APU_RST#_EC A
G
4.7K_0402_5% SAMTE_ASP-136446-07-B @ C141

5
U62 @ NL17SZ07DFT2G_SC70-5 0.01U_0402_16V7K

2
1 SA00004BV00
P
NC 4 APU_PWRGD @
APU_PWRGD_EC 2 Y RH57 2 1 0_0402_5%
<27> APU_PWRGD_EC A
G
@
NL17SZ07DFT2G_SC70-5 Security Classification Compal Secret Data Compal Electronics, Inc.
3
SA00004BV00 Issued Date 2014/06/10 2015/06/30 Title

@ Deciphered Date
RH54 2 1 0_0402_5%
FP4 DISP/MISC/HDT
@ Size Document Number Rev
Custom 0.3
A B C D E
A B C D E
Main Func = CPU
+3VS
RH1 100K_0402_5%
2 1
2
1 2 R693 DIS@
UC1D
C615 150P_0402_50V8J 10K_0402_5%
<19,20,27> PLT_RST# Vinafix.com

R602 1 2 33_0402_5%
OUTPUT
LPC_RST_A# BB12 LPC_RST_L
ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC
SD0_WP/EGPIO101 BB2 KB_DET# KB_DET# <24> UMA: LOW
1
R907 1 2 33_0402_5% APU_PCIE_RST#_R AN7 PCIE_RST_L/EGPIO26 SD0_PWR_CTRL/AGPIO102 BB5
OUTPUT SD0_CD/AGPIO25 BC2 AGPIO25 R661 1 @ 2 0_0402_5% AGPIO65 DIS: HIGH
1 2 AE4 BB4 H_PROCHOT# <8,27,41,42,48,49>
1 APU_PCIE_RST#_C EC_RSMRST#_R RSMRST_L SD0_CLK/EGPIO95 1
2
C912 150P_0402_50V8J SD0_CMD/EGPIO96 AY5 ODD_EN# ODD_EN# <22>
RH51 2 @ 1 0_0402_5% AE1 10 kΩ (± 5%)/+3VALW
PWR_BTN_L/AGPIO0 R692 UMA@
VGATE <26,27,48,49> +3VALW <27> PBTN_OUT#
APU_FCH_PWRGD_R BC9 SD no used can NC
PWR_GOOD +3VALW/+1.8VALW 10K_0402_5%
APU_FCH_PWRGD RH52 2 @ 1 0_0402_5% SYS_RESET_L AF2 +3VALW
SYS_RESET_L/AGPIO1
APU_FCH_POK <27>
APU_PCIE_WAKE# AG2 WAKE_L/AGPIO2 SD0_DATA0/EGPIO97 BC3 R12 1 @ 2 0_0402_5% TP_I2C_INT#_APU
INPUT <19,27> APU_PCIE_WAKE# TP_I2C_INT#_APU <24>
1
SD0_DATA1/EGPIO98 BA3
NESD@ AK7 SLP_S3_L SD0_DATA2/EGPIO99 BC5
CH23 100P_0402_50V8J OUTPUT <27> PM_SLP_S3# AH5 SLP_S5_L SD0_DATA3/EGPIO100 BA5 +3VALW
2 1 APU_FCH_PWRGD OUTPUT <27> PM_SLP_S5#
SD0_LED/EGPIO93 BB6
AE8 PXS_PWREN <26,51,52,53> 2 CZL@ 1 R931
S0A3 S0A3_GPIO/AGPIO10 AGPIO4 10K_0402_5%
CH23 close to UC1 I/O S5_MUX_CTRL AH8 S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 BA15 APU_SCLK0 AGPIO8 10K_0402_5% 2 CZ@ 1 R932
<26> S5_MUX_CTRL AY17 APU_SDATA0 APU_SCLK0 <13,14>
SDA0/I2C2_SDA/EGPIO114
APU_SDATA0 <13,14> VDD_33/2.2K
R40 1 2 15K_0402_5% APU_TEST0 AH6 TEST0
R41 1 2 15K_0402_5% APU_TEST1 AK8 TEST1/TMS SCL1/I2C3_SCL/AGPIO19 AG5 APU_SCLK1
+3VALW_EC +1.8V_ALW +3VALW 1 2 15K_0402_5% APU_TEST2 AE3 AG4 APU_SDATA1 APU_SCLK1 <24>
R42 TEST2 SDA1/I2C3_SDA/AGPIO20
APU_SDATA1 <24> VDD_33_S5/2.2K PU at T/P side
1
AY15 As close as possible to UC1D

4.7K_0402_5%
4.7K_0402_5%
+3.3VS <27> KB_RST# ESPI_RESET_L/KBRST_L/AGPIO129

@ @ BC19 GA20IN/AGPIO126 2 1 2 1
R3 R21 +3.3VS <27> GATEA20 AD7 LPC_PME_L/AGPIO22 AGPIO3 AL5 MEM_VOLT_SEL High @ @ +3VS
VDD_33_S5 <27> EC_SCI# BB13 AL6 AGPIO4
@
<27> EC_SMI# LPC_SMI_L/AGPIO86 AGPIO4 High C31 0.1U_0402_16V7K C32 0.1U_0402_16V7K
5
U61 CZ-->S0, CZL->S5 AGPIO5 AJ1 ODD_DA#_FCH AGPIO64 10K_0402_5% 2 CZL@ 1 R934
2
1 ODD_DETECT# AG3 AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO6/LDT_RST AJ3 APU_RST#_R R662 1 @ 2 0_0402_5% APU_RST# AGPIO66 10K_0402_5% 2 CZL@ 1 R935
P
NC 4 APU_FCH_PWRGD_R
VDD_33_S5 <22> ODD_DETECT# TS_INT# AD5 AH1 APU_PWRGD_R R663 1 @ 2 0_0402_5% APU_PWRGD
APU_RST# <8>
AGPIO69 10K_0402_5% 2 CZ@ 1 R936
IR_TX0/USB_OC5_L/AGPIO13 AGPIO7/LDT_PWROK
APU_FCH_PWRGD 2 Y VDD_33_S5 <16> TS_INT# TS_RST# AL8 AJ4 AGPIO8 R22 1 @ 2 0_0402_5% TP_I2C_INT#_APU
APU_PWRGD <8,48,49>
PXS_PWREN 10K_0402_5% 2 1 R938
IR_TX1/USB_OC6_L/AGPIO14 AGPIO8
A VDD_33_S5 <16> TS_RST# TP_I2C_INT#_APU <24>
G
AN8 IR_RX1/AGPIO15 AGPIO9 AK5

AE2 AD8 GFX_VR_ON EC_LID_OUT# <27>
NL17SZ07DFT2G_SC70-5 IR_LED_L/LLB_L/AGPIO12 VDDGFX_PD/AGPIO39 I/O
VDD_33_S5/OD GFX_VR_ON <49>
3
SA00004BV00 LAN_CLKREQ# BC15 INPUT AG8 GFX_PWRGD_APU 1 @ 2 GFX_VR_ON:

VDD_33_S0 <19> LAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40 I/O
GFX_PWRGD <26,27,48,49>
WLAN_CLKREQ# BB17 CLK_REQ1_L/AGPIO115 INPUT AGPIO64 AW15AGPIO64 R664 0_0402_5% CZ only DISABLE GFX-->HIGH
RH53 2 @ 1 0_0402_5%
VDD_33_S0 <20> WLAN_CLKREQ# PWRGD_VGA BC17 AU15 AGPIO65
VDD_33_S0 <53> PWRGD_VGA CLK_REQ2_L/AGPIO116 INPUT AGPIO65
ENABLE GFX-->LOW
BB18 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 INPUT
VDD_33_S0 2 @ 1 0_0402_5% PEG_CLKREQ#_R BB16 AT15 AGPIO66 +3VS
VDD_33_S0 <34> PEG_CLKREQ# CLK_REQG_L/OSCIN/EGPIO132 INPUT AGPIO66/SHUTDOWN_L
RH56 USB_OC0# AH9 USB_OC0_L/TRST_L/AGPIO16 AGPIO68/SGPIO_CLK AU12 BT_ON#
<23> USB_OC0# AG1 AT14 AGPIO69 BT_ON# <20>
VDD_33_S5 USB_OC1# USB_OC1_L/TDI/AGPIO17 AGPIO69/SGPIO_LOAD
<25> USB_OC1# AH2 AR14
VDD_33_S5 USB_OC2_L/TCK/AGPIO18 AGPIO71/SGPIO_DATAOUT
PXS_RST# <33> AND Gate, as before
2
VDD_33_S5 AL9 USB_OC3_L/TDO/AGPIO24 AGPIO72/SGPIO_DATAIN BC13
PANEL_SIZE_ID <16>
RH55
2
10 kΩ (± 5%) / VSS HDA_BITCLK AU6 AZ_BITCLK/I2S_BCLK_MIC SPKR/AGPIO91 BA17 100K_0402_5% 2
APU_SPKR <18>
2
G
EMI@ 22–33Ω (± 5%) HDA_SDIN0 AR8 AZ_SDIN0/I2S_DATA_MIC[0] QH1
22–33Ω (± 5%) <18> HDA_SDIN0 AP6 AN5 AGPIO11
RP13 HDA_SDIN1 AZ_SDIN1/I2S_LR_PLAYBACK BLINK/USB_OC7_L/AGPIO11 CH15 @
+3VALW
1
1 8 HDA_RST# HDA_SDIN222–33Ω (± 5%) AR5 AZ_SDIN2/I2S_DATA_MIC[1] 1 2 3 1 ODD_DA#_FCH
<18> HDA_RST#_AUDIO 2 7 22–33Ω (± 5%) 5%) AU9 BB14 <22> ODD_DA#
HDA_SYNC HDA_RST# 22–33Ω (± HVB_FUNCTION
D
AZ_RST_L/I2S_LR_MIC GENINT1_L/AGPIO89
<18> HDA_SYNC_AUDIO 3 6 22–33Ω (± 5%) AT9 BA19
HDA_SDOUT HDA_SYNC AZ_SYNC/I2S_BCLK_PLAYBACK GENINT2_L/AGPIO90 0.1U_0402_16V7K
<18> HDA_SDOUT_AUDIO 4 5 22–33Ω (± 5%) AR7
HDA_BITCLK HDA_SDOUT AZ_SDOUT/I2S_DATA_PLAYBACK SSM3K7002FU_SC70-3
<18> HDA_BITCLK_AUDIO BC18
FANIN0/AGPIO84
33_0804_8P4R_5% VDD_18 APU_I2C0_SCL_TP BB10 I2C0_SCL/EGPIO145 FANOUT0/AGPIO85 BB19
VDD_18 APU_I2C0_SDA_TP BB9 I2C0_SDA/EGPIO146
I2C0 and I2C1 for CZ only VDD_18 APU_I2C1_SCL BB7 I2C1_SCL/EGPIO147 UART0_CTS_L/EGPIO135 AY9
1.8V_S0 level, need LS VDD_18 APU_I2C1_SDA BC7 I2C1_SDA/EGPIO148 UART0_RXD/EGPIO136 AW8
UART0_RTS_L/EGPIO137 AV5 UART no used can NC
I2C Not Implemented: 10 kΩ (± 5%) / VDD_33_S5 RTC_CLK AG7 AV8
RTCCLK UART0_TXD/EGPIO138
Used as EGPIO or configured with one of the following options: UART0_INTR/AGPIO139 AW9
1.PH 2.2K
2.PD 10K 32K_X1 AT1 X32K_X1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140 AV11
UART1_RXD/BT_I2S_SDI/EGPIO141 AU7
UART1_RTS_L/EGPIO142 AT11 APU_PCIE_RST# RH30 1 @ 2 APU_PCIE_RST#_C
UART1_TXD/BT_I2S_SDO/EGPIO143 AR11 0_0402_5%
32K_X2 AT2 X32K_X2 UART1_INTR/BT_I2S_LRCLK/AGPIO144 AP9
FP4 REV 0.93
FP4_BGA968 For PCIE device reset on FS1

+3VALW
(GFX,GLAN,WLAN,LVDS Travis) CH14 @
APU_PCIE_RST #: Reset PCIE device on APU 1 2
0.1U_0402_16V7K
5
MC74VHC1G08DFT2G SC70 5P
+1.8VS @ RH25 2
P
APU_PCIE_RST#_C 1 2 B 4
Y APU_PCIE_RST# <19,20,33>
R955 1 CZ_I2C@2 2.2K_0402_5% APU_I2C0_SCL_TP 33_0402_5% 1
A
G
R956 1 CZ_I2C@2 2.2K_0402_5% APU_I2C0_SDA_TP UH1 QCL10 LAN-APU,WLAN&ExCARD-FCH 20110803
8.2K_0402_5%
2
RH45 1 @ 2 10K_0402_5% HVB_FUNCTION
150P_0402_50V8J
1
1
CH16
RH26
@ @
+3VALW RH27
3 @ @ 0_0402_5% 3
R930 1 @ 2 10K_0402_5% APU_PCIE_WAKE# +1.8VS 2
1
R905 1 2 100K_0402_5% USB_OC0#
2
@ RH28
+3VS 1 2 PLT_RST#
5
0_0402_5%
R676 1 2 2.2K_0402_5% APU_SCLK0
G
R677 1 2 2.2K_0402_5% APU_SDATA0 3 4 APU_I2C0_SCL_TP

<24> I2C_CLK_TP
D
R937 1 2 10K_0402_5% GATEA20 Q2509A CZ_I2C@ GEVENT2_L ???? RTC_CLK BLINK/GPIO11 SYS_RST#
2
R941 1 2 10K_0402_5% KB_RST# DMN63D8LDW_SOT363-6 LPC_CLK0_EC LPC_CLK1 LPC_FRAME#

RH41 1 @ 2 10K_0402_5% BT_ON# <INT PU> <INT PU> <INT PU> <INT PU>
G
RH44 1 @ 2 10K_0402_5% HVB_FUNCTION 6 1 APU_I2C0_SDA_TP LDT_RST#/PG

<24> I2C_DAT_TP CZL CZ
D
Q2509B CZ_I2C@ BOOT FAIL CLKGEN SPI ROM COIN BATT NORMAL
+3VALW
DMN63D8LDW_SOT363-6
+1.8V_ALW +3VALW H TIMER
ENABLED
ENABLE
(DEFAULT)
(DEFAULT) 1.8V SPI ROM
(Default)
ENHANCED
RESET
ON BOARD
(DEFAULT)
OUTPUT TO
APU
(DEFAULT)
RESET MODE
(DEFAULT)
R685 1 @ 2 4.7K_0402_5% APU_SCLK1 (AOAC)
R686 1 @ 2 4.7K_0402_5% APU_SDATA1 RSMRST# BOOT FAIL
R942 1 2 10K_0402_5% PBTN_OUT# 1.8V /EC program to 1.8V OUTPUT CLKGEN TRADITION COIN BATT OUTPUT SHORT RST
L TIMER
1
R943 1 @ 2 100K_0402_5% EC_LID_OUT# CZL@ CZ@ LPC ROM 3.3V SPI ROM
DISABLED DISABLED RESET NOT ON TO PADS MODE
22K_0402_5%
R347
22K_0402_5%
R348
R944 1 PTP@ 2 100K_0402_5% S0A3 Check RSMRST delay 10ms R346

22K_0402_5% (DEFAULT) (DEFAULT) BOARD
R709 1 CZL@ 2 10K_0402_5% APU_I2C0_SCL_TP
R691 1 CZL@ 2 10K_0402_5% APU_I2C0_SDA_TP +3VS +3VALW
2
R689 1 CZ@ 2 10K_0402_5% APU_I2C1_SCL EC_RSMRST# 1 2 EC_RSMRST#_R

<27> EC_RSMRST#
1
R688 1 CZ@ 2 10K_0402_5% APU_I2C1_SDA D3
R694 1 NPTP@ 2 10K_0402_5% S0A3 RB751V-40 SOD-323 APU_FCH_PWRGD @ CZ@
R695 1 CZ@ 2 10K_0402_5% HDA_SDIN1 R902 R904 R925 R928 R949 R951 R954
RH46 1 @ 2 10K_0402_5% HVB_FUNCTION RB751 Max Vf=0.37V 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
R696 1 CZ@ 2 10K_0402_5% HDA_SDIN2 2 2
2
C999 C1000
<10,27> LPC_FRAME#
<10,27> LPC_CLK0_EC
SYS_PWRGD: .1U_0402_16V7K .1U_0402_16V7K
<10> LPC_CLK1
1 1 MEM_VOLT_SEL
32.768KMHz CRYSTAL CZ->3.3V /EC program to 3.3V OUTPUT
CZL->1.8V /EC program to 1.8V OUTPUT
RTC_CLK
SYS_RESET_L
AGPIO11
4 32K_X1 4
1
1
1
@ @ @ @ @
SJ100001K00 Y3 R903 R926 CE30 R927 R929 R950 R952 R953
32.768KHZ_12.5PF_CM31532768DZFT 2K_0402_5% 2K_0402_5% 22P_0402_50V8J 2K_0402_5% 2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2 CZL@
NEMI@
2
2
2 1 32K_X2
R914
20M_0402_5%
1 1
C686 C682 Security Classification Compal Secret Data Compal Electronics, Inc.
18P_0402_50V8J 22P_0402_50V8J 2014/06/10 2015/06/30 Title
2 2 Issued Date Deciphered Date
FP4 GPIO/AZ/MISC/STRAPS
Custom 0.3
A B C D E
A B C D E
Main Func = CPU

UC1E
CLK/SATA/USB/SPI/LPC
AU3 SATA_TX0P USBCLK/25M_48M_OSCAP8
<22> SATA_ATX_DRX_P0 AU4 SATA_TX0N
<22> SATA_ATX_DRX_N0 AP5 USB_ZVSS
USB_ZVSS R641 1 2 11.8K_0402_1%
HDD AV1 SATA_RX0N
<22> SATA_ARX_DTX_N0 AV2 AR2
SATA_RX0P USB_HSD0P USB20_CR_P0
Vinafix.com
<22> SATA_ARX_DTX_P0 AR1 USB20_CR_N0 USB20_CR_P0 <21>
USB_HSD0N
USB20_CR_N0 <21> Card Reader
AY2 SATA_TX1P
<22> SATA_ATX_DRX_P1 AY1 AR3 USB20_JUSB2_P1
SATA_TX1N USB_HSD1P
<22> SATA_ATX_DRX_N1 AR4 USB20_JUSB2_P1 <25>
ODD USB_HSD1N USB20_JUSB2_N1 USB Conn JUSB2 (DB)
1 AW4 USB20_JUSB2_N1 <25> 1
SATA_RX1N
<22> SATA_ARX_DTX_N1 AW3 AN2 USB20_JUSB3_P2
SATA_RX1P USB_HSD2P
<22> SATA_ARX_DTX_P1 AN1 USB20_JUSB3_N2 USB20_JUSB3_P2 <25>
USB_HSD2N
USB20_JUSB3_N2 <25> USB Conn JUSB3 (DB)
R90 2 1 1K_0402_1% SATA_ZVSS AW1 SATA_ZVSS
R96 2 1 1K_0402_1% SATA_ZVDD AW2 SATA_ZVDDP USB_HSD3P AN3 USB20_P3
+0.95VS USB20_P3 <24>
DEVSLP0_HDD AT17 DEVSLP[0]/EGPIO67 USB_HSD3N AN4 USB20_N3 For I2C
<22> DEVSLP0_HDD WL_OFF# AT12 USB20_N3 <24>
DEVSLP[1]/EGPIO70
<20> WL_OFF# SATA_ACT# BB15 AM1 USB20_MINI1_P4
SATA_ACT_L/AGPIO130 USB_HSD4P
<27,29> SATA_ACT# AM2 USB20_MINI1_N4 USB20_MINI1_P4 <20>
USB_HSD4N
USB20_MINI1_N4 <20> Mini Card (WLAN)
AU2 SATA_X1
USB_HSD5P AL2 USB20_TOUCH_P5
1 2 DEVSLP0_HDD AL1 USB20_TOUCH_N5 USB20_TOUCH_P5 <16>
+3VS @ USB_HSD5N
USB20_TOUCH_N5 <16> Touch screen panel
10K_0402_5%1 @ 2 RH40 WL_OFF#
10K_0402_5%1 2 RH42 SATA_ACT# AU1 SATA_X2 USB_HSD6P AL3 USB20_JUSB1_P6
AL4 USB20_JUSB1_N6 USB20_JUSB1_P6 <23>
10K_0402_5% RH43 USB_HSD6N
USB20_JUSB1_N6 <23> USB Conn JUSB1
U4 GFX_CLKP USB_HSD7P AK2 USB20_CAM_P7 USB 3.0
<33> CLK_PEG_VGA U3 AJ2 USB20_CAM_N7 USB20_CAM_P7 <16>
VGA <33> CLK_PEG_VGA# GFX_CLKN USB_HSD7N
USB20_CAM_N7 <16> Camera
U1 GPP_CLK0P
<19> CLK_PCIE_LAN U2
LAN <19> CLK_PCIE_LAN# GPP_CLK0N
W4 GPP_CLK1P
<20> CLK_PCIE_WLAN W3
WLAN <20> CLK_PCIE_WLAN# GPP_CLK1N
W1 GPP_CLK2P
W2 GPP_CLK2N
Y2 GPP_CLK3P
Y1 GPP_CLK3N
BC10 X25M_48M_OSC
2 AD2 USBSS_ZVSS R644 1 2 1K_0402_1% 2
USB_SS_ZVSS
USB_SS_ZVDDP AD1 USBSS_ZVDD R645 1 2 1K_0402_1%
+0.95VALW
48M_X1 T2 X48M_X1
USB_SS_0TXP AA3
USB_SS_0TXN AA4
48M_X2 T1 X48M_X2 USB_SS_0RXP W9

USB_SS_0RXN W8
R449 1 2 33_0402_5% AW14 LPCCLK0/EGPIO74 USB_SS_1TXP AA2

<9,27> LPC_CLK0_EC
R450 1 @ 2 0_0402_5% AY13 LPCCLK1/EGPIO75 USB_SS_1TXN AA1
<9> LPC_CLK1
BB11 LAD0 USB_SS_1RXP W5
<27> LPC_AD0 BA11 W6
LAD1 USB_SS_1RXN
<27> LPC_AD1 AY11 LAD2
<27> LPC_AD2 BA13 AC1 USB3TP1_JUSB1
LAD3 USB_SS_2TXP
<27> LPC_AD3 AV14 AC2 USB3TP1_JUSB1 <23>
LFRAME_L USB_SS_2TXN USB3TN1_JUSB1
<9,27> LPC_FRAME# BA1 USB3TN1_JUSB1 <23>
ESPI_ALERT_L/LDRQ0_L USB Conn JUSB1
BC14 SERIRQ/AGPIO87 USB_SS_2RXP Y6 USB3RP1_JUSB1
<27> SERIRQ BC11 USB3RP1_JUSB1 <23>
LPC_CLKRUN_L/AGPIO88 USB_SS_2RXN Y7 USB3RN1_JUSB1
AE9 USB3RN1_JUSB1 <23>
LPC_PD_L/AGPIO21
R106 USB_SS_3TXP AC4
0_0402_5% USB_SS_3TXN AC3
R1691 1 AL@ 2 0_0402_5% APU_SPI_CLK 1 EMI@ 2 APU_SPI_CLK_R BC6 SPI_CLK/ESPI_CLK/EGPIO117
<27> EC_SPI_CLK
R1693 1 AL@ 2 0_0402_5% APU_SPI_CS1# BB8 SPI_CS1_L/EGPIO118 USB_SS_3RXP AB5
<27> EC_SPI_CS1# APU_SPI_CS1#_R AW7 AB6
SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN
R1692 1 AL@ 2 0_0402_5% APU_SPI_MISO BA9 SPI_DI/ESPI_DATA/EGPIO120
<27> EC_SPI_MISO
R1694 1 AL@ 2 0_0402_5% APU_SPI_MOSI AY7 SPI_DO/EGPIO121
<27> EC_SPI_MOSI APU_SPI_WP# AW11 SPI_WP_L/EGPIO122
APU_SPI_HOLD# BA7 SPI_HOLD_L/EGPIO133
APU_SPI_TPMCS# AW12 SPI_TPM_CS_L/AGPIO76
CRT_EMI@
3 APU_SPI_CLK C27 1 2
10P_0402_50V8J
FP4 REV 0.93
FP4_BGA968
48MHz CRYSTAL 3
7/25 Add, EMI request

48M_X2
APU_SPI_CS1# 1 @ 2 APU_SPI_CS1#_R
R107 0_0402_5% 1 R939 2 48M_X1
1M_0402_5%
+SPI_VCC 2 1
2 1
2 CZL@ 1 APU_SPI_HOLD#
R634 10K_0402_5%
2 CZL@ 1 APU_SPI_WP# +1.8VS Y2

R635 10K_0402_5% U56 CZL@ 48MHZ_8PF_X3S048000D81H-W
+1.8V_ALW Part Number = SJ10000AF00
2 CZL@ 1 APU_SPI_CS1# +3VALW
R636 10K_0402_5%
R1673 1 CZL@ 2 0_0603_5% 3 4
2 @ 1 APU_SPI_CS1# R1672 1 @ 2 0_0603_5% 3 4
1 1
R637 R1675 1 CZ@ 2 0_0603_5% SPI ROM
10K_0402_5% Part Number = SA00008IP00 C796 C797
2 @ 1 APU_SPI_TPMCS# EN25QH64A-104HIP_SO8 5.6P_0402_50V8D 5.6P_0402_50V8D
R638
10K_0402_5%
8MB SPI ROM 2 1
2 2
C635 @
U56 CZ@ .1U_0402_16V7K
APU_SPI_CS1# 1 8 +SPI_VCC
APU_SPI_MISO 2 CS# VCC 7 APU_SPI_HOLD#
APU_SPI_WP# 3 DO(IO1) HOLD#(IO3) 6 APU_SPI_CLK
4 WP#(IO2) CLK 5 APU_SPI_MOSI
4 +SPI_VCC GND DI(IO0) 4
W25Q64FWSSIQ_SO8
2 CZ@ 1 APU_SPI_HOLD#
R642 10K_0402_5% APU_SPI_CLK 1 2 1 2
2 CZ@ 1 APU_SPI_WP# R617 NEMI@ C636 NEMI@
R640 10K_0402_5% 10_0402_5% 10P_0402_50V8J
2 CZ@ 1 APU_SPI_CS1#
R639 10K_0402_5%
FT3 SATA/CLK/USB/SPI
Custom 0.3
A B C D E
A B C D E
Main Func = CPU
+1.35V
Vinafix.com
C1008
C1057
C1058
C1059
C1060
C1061
C1062
C1063
C1064
C1065
C1066
C1087
C1088
C1089
C1090
C1091
C1092
C1093
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ @ @
1 UC1F 1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
180P_0402_50V8J
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 POWER
+1.35V P25 VDDIO_MEM_S3_1 VDDCR_CPU_1 U8 +APU_CORE +APU_CORE

P28 W7
3A VDDIO_MEM_S3_2 VDDCR_CPU_2
40A
C1052
C1128
C1127
C1125
C1123
C1122
C1121
C1120
C1117
C1068
C1009
C1010
C1011
C1015
C1016
C1053
C1054
C1055
T24 VDDIO_MEM_S3_3 VDDCR_CPU_3 W12
T27 VDDIO_MEM_S3_4 VDDCR_CPU_4 W15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
U25 VDDIO_MEM_S3_5 VDDCR_CPU_5 W18
U28 VDDIO_MEM_S3_6 VDDCR_CPU_6 W21
180P_0402_50V8J
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
V30 VDDIO_MEM_S3_7 VDDCR_CPU_7 Y8
V33 Y10 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Under APU W24
VDDIO_MEM_S3_8
VDDIO_MEM_S3_9
VDDCR_CPU_8
VDDCR_CPU_9 Y13
W27 VDDIO_MEM_S3_10 VDDCR_CPU_10 Y16
+1.35V Y25 VDDIO_MEM_S3_11 VDDCR_CPU_11 Y19
Y28 VDDIO_MEM_S3_12 VDDCR_CPU_12 Y22
C1111
C1112
C1113
C1114
C1115
C1116
Y30 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB7
1 1 1 1 1 1 AB24 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB9
AB27 VDDIO_MEM_S3_15 VDDCR_CPU_15 AB12
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
180P_0402_50V8J
180P_0402_50V8J
2 2 2 2 2 2 AD25 VDDIO_MEM_S3_18 VDDCR_CPU_18 AB21
AD28 VDDIO_MEM_S3_19 VDDCR_CPU_19 AD6
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
CZ@
AD30 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD10
AE24 VDDIO_MEM_S3_21 VDDCR_CPU_21 AD13
AE27 VDDIO_MEM_S3_22 VDDCR_CPU_22 AD16
+APU_CORE_GFX
AF30 VDDIO_MEM_S3_23 VDDCR_CPU_23 AD19
C1056
C1149
C1138
C1136
C1135
C1134
C1133
C1132
C1131
C1130
C1077
C1069
C1070
C1071
C1072
C1073
C1074
C1075
C1076
AF33 VDDIO_MEM_S3_24 VDDCR_CPU_24 AD22
AG25 AE7
DIMMS/GND AG28
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDCR_CPU_25
VDDCR_CPU_26 AE12
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AH24 VDDIO_MEM_S3_27 VDDCR_CPU_42 AK9
180P_0402_50V8J
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
AH27 VDDIO_MEM_S3_28 VDDCR_CPU_31 AG10
2 @ 1 VDDIO_AUDIO AH30 VDDIO_MEM_S3_29 VDDCR_CPU_43 AK10 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.5VS
R11 0_0402_5% AK25 VDDIO_MEM_S3_30 VDDCR_CPU_32 AG13
AK28 AK13
FOR DEBUG ONLY AK30
VDDIO_MEM_S3_31
VDDIO_MEM_S3_32
VDDCR_CPU_44
VDDCR_CPU_33 AG16
AK33 VDDIO_MEM_S3_33 VDDCR_CPU_45 AK16
1 @ 2 AL27 VDDIO_MEM_S3_34 VDDCR_CPU_34 AG19
+3VS +3VS_APU +1.8VS +1.5VS
AM30 VDDIO_MEM_S3_35 VDDCR_CPU_46 AK19
C1137
C1100
C1101
C1102
2 R119 C1005
VDDCR_CPU_35 AG22 2
C1006
C1007
0_0402_5% 1 1 1 1 VDDIO_AUDIO AR19 VDDIO_AUDIO VDDCR_CPU_47 AK22
AH7
@
1 1 1 0.2A AE6 VDDP_GFX_2
VDDCR_CPU_36
VDDCR_CPU_28 AE18
+0.95VS_APU_GFX +APU_CORE_NB
10U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
AE5 AE21
2 2 2 2 1.5A VDDP_GFX_1 VDDCR_CPU_29
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C1067
C1146
C1145
C1144
C1143
C1142
C1141
C1140
C1139
C1095
C1096
C1097
C1098
VDDCR_CPU_40 AH21
2 2 2 AP19 AG6
+3VS_APU VDD_33_1 VDDCR_CPU_30 1 1 1 1 1 1 1 1 1 1 1 1 1
AP21 AH12
0.2A VDD_33_2 VDDCR_CPU_37
VDDCR_CPU_49 AN6
180P_0402_50V8J
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
AP16 VDD_18_1 VDDCR_CPU_38 AH15
+1.8VS 2 2 2 2 2 2 2 2 2 2 2 2 2
AP18 AH18
1.5A VDD_18_2 VDDCR_CPU_39
VDDCR_CPU_48 AL7
+1.8V_ALW AP10 VDD_18_S5_1 VDDCR_CPU_41 AK6
AR9 AE15
0.5A VDD_18_S5_2 VDDCR_CPU_27
+3VALW AP15 VDD_33_S5_1

CZ@ CZ@ CZ@ AR15 L8
+3VALW +1.8V_ALW +VDDCR_FCH_ALW 0.2A VDD_33_S5_2 VDDCR_GFX_14
L13
+APU_CORE_GFX
VDDCR_GFX_15
22A
C1124
C1126
C1085
C1086
C1108
C1109
C1110
AN12 VDDP_S5_1 VDDCR_GFX_16 L16

+0.95VALW
AP12 L19
1 1 1 1 1 1 1 0.8A VDDP_S5_2 VDDCR_GFX_17
VDDCR_GFX_18 L22
Under APU
AP13 VDDCR_FCH_S5_1 VDDCR_GFX_19 N7
10U_0603_6.3V6M
0.22U_0402_10V6K
10U_0603_6.3V6M
0.22U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
+VDDCR_FCH_ALW AR12 VDDCR_FCH_S5_2 VDDCR_GFX_20 N12

2 2 2 2 2 2 2 VDDCR_GFX_21 N15
AW19 VDDP_6 VDDCR_GFX_22 N18
+0.95VS_APU_GFX
AU17 N21
7A AU19
VDDP_1
VDDP_2
VDDCR_GFX_23
VDDCR_GFX_24 P8
+APU_CORE_NB
C1084
C1082
C1081
C1079
C1078
AV17 VDDP_3 VDDCR_GFX_25 P13
AV19 VDDP_4 VDDCR_GFX_26 P16 1 1 1 1 1
AW17 VDDP_5 VDDCR_GFX_27 P19
VDDCR_GFX_28 P22
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
AL12 VDDCR_NB_1 VDDCR_GFX_29 T7
+APU_CORE_NB 2 2 2 2 2
AL13 F12
12A AL15
VDDCR_NB_2 VDDCR_GFX_1
F15
+0.95VALW/+0.95VS OF APU +VDDP_VS AL18
AL21
VDDCR_NB_3
VDDCR_NB_4
VDDCR_GFX_2
VDDCR_GFX_3 G11
G14
VDDCR_NB_5 VDDCR_GFX_4
AN13 J8
VDD_095 VDD_095_GFX AN16
VDDCR_NB_6
VDDCR_NB_7
VDDCR_GFX_5
VDDCR_GFX_6 J9
3 +0.95VS +0.95VS_APU_GFX 3
AN19 J11
L22
+VDDP_ALW AN22
VDDCR_NB_8
VDDCR_NB_9
VDDCR_GFX_7
VDDCR_GFX_8 K7
2 1 K12
FBMA-L11-201209-121LMA50T_0805
+0.95VALW VDDCR_GFX_9
VDDCR_GFX_10 K13
ACROSS VDDNB AND VSS SPLIT
C935
C934
C951
C203
C1118
C1119
+RTC_APU_R +RTC_APU_R AR17 VDDBT_RTC_G VDDCR_GFX_11 K15

1 1 1 1 1 1 VDDCR_GFX_12 K16
C1129
T12
1
VDDCR_GFX_30
VDDCR_GFX_31 T15 OPEN
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
0.22U_0402_10V6K
VDDCR_GFX_32 T18
2 2 2 2 2 2 JP14
VDDCR_GFX_33 T21
0.22U_0402_10V6K
VDDCR_GFX_34 U13 2 1
2 VDDCR_GFX_35 U16 +RTCVCC 2 1
VDDCR_GFX_36 U19 JUMP_43X39
VDDCR_GFX_37 U22
VDDCR_GFX_13 K19
JP12
FP4 REV 0.93 2 1
FP4_BGA968 +CHGRTC 2 1 +3VLP
JUMP_43X39
+0.95VS_APU_GFX
DIS@ DIS@ +0.95VS_APU_GFX
SHORT
C949
C950
C1080
C1083
C1099
C245
C1147
C1148
1 1 1 1 1 1
1 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_10V6K
180P_0402_50V8J
2 2 2 2 2 2 +RTC_APU +RTCVCC
10U_0603_6.3V6M
0.22U_0402_10V6K
2 2
Vo=1.5V D101
2 1 2
+RTCBATT
+RTC_APU 3 R31 1K_0402_5%
Vout 1 1
2 Vin
W=20mils GND
+RTC_APU_R R93 1 2 1K_0402_5% 3
Under APU 1 1 +CHGRTC
RTC OF APU 1 1 Need OPEN C119

U101
C120 BAS40C-2-GP
0.1U_0603_25V7K AP2138N-1.5TRG1_SOT23-3 680P_0603_50V8J
Close AE6, AE5
1
2 2
C166
0.22U_0402_10V6K
C923
1U_0402_6.3V6K
@
CLRP1
for Clear CMOS
4 4
2 2 SHORT PADS
2
2 1
- + +RTCBATT

JRTC
LOTES_AAA-BAT-054-K01 FP4 PWR
CONN@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
SP07000H700 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
5 4 3 2 1
Main Func = CPU

UC1G UC1H
UC1J
GND GND
A8 VSS_1 VSS_63 L28 AE10 VSS_125 VSS_187 AV30
A12 VSS_2 VSS_64 M4 AE13 VSS_126 VSS_188 AV33 U30 RSVD_2
T173
A16 VSS_3 VSS_65 M30 AE16 VSS_127 VSS_189 AW22 U31 RSVD_3
T12
A20 VSS_4 VSS_66 N10 AE19 VSS_128 VSS_190 AY4 AN30 RSVD_4
T13
A24 VSS_5 VSS_67 N13 AE22 VSS_129 VSS_191 AY6
A28 VSS_6 VSS_68 N16 AF1 VSS_130 VSS_192 AY8
A32
B2
B8
VSS_7
VSS_8
VSS_9
VSS_69
VSS_70
VSS_71
Vinafix.com
N19
N22
N27
AF4
AG9
AG12
VSS_131
VSS_132
VSS_133
VSS_193
VSS_194
VSS_195
AY10
AY12
AY14
B12 VSS_10 VSS_72 P1 AG15 VSS_134 VSS_196 AY16
D B33 VSS_11 VSS_73 P2 AG18 VSS_135 VSS_197 AY20 D
C3 VSS_12 VSS_74 P4 AG21 VSS_136 VSS_198 AY22 FP4 REV 0.93
D4 VSS_13 VSS_75 P5 AH4 VSS_137 VSS_199 AY24
D6 VSS_14 VSS_76 P12 AH10 VSS_138 VSS_200 AY26 FP4_BGA968
D12 VSS_17 VSS_79 P21 AH19 VSS_141 VSS_203 BB1
D14 VSS_18 VSS_80 P30 AH22 VSS_142 VSS_204 BB33
D16 VSS_19 VSS_81 P33 AK1 VSS_143 VSS_205 BC4
D18 VSS_20 VSS_82 T4 AK4 VSS_144 VSS_206 BC8
D26 VSS_24 VSS_86 T19 AL16 VSS_148 VSS_210 BC24
F1 VSS_27 VSS_89 U5 AM4 VSS_151
F2 VSS_28 VSS_90 U12 AN9 VSS_152
F4 VSS_29 VSS_91 U15 AN10 VSS_153
F9 VSS_30 VSS_92 U18 AN15 VSS_154
F19 VSS_31 VSS_93 U21 AN18 VSS_155
F22 VSS_32 VSS_94 U24 AN21 VSS_156
F25 VSS_33 VSS_95 V1 AN25 VSS_157
F30 VSS_34 VSS_96 V2 AN28 VSS_158
F33 VSS_35 VSS_97 V4 AP1 VSS_159
G7 VSS_36 VSS_98 W10 AP2 VSS_160
G17 VSS_37 VSS_99 W13 AP4 VSS_161
G20 VSS_38 VSS_100 W16 AP7 VSS_162
G23 VSS_39 VSS_101 W19 AP22 VSS_163
G26 VSS_40 VSS_102 W22 AP27 VSS_164
H4 VSS_41 VSS_103 Y4 AP30 VSS_165
H30 VSS_42 VSS_104 Y5 AP33 VSS_166
C J5 Y12 AR6 C
VSS_43 VSS_105 VSS_167
J15 VSS_44 VSS_106 Y15 AR25 VSS_168
J19 VSS_45 VSS_107 Y18 AR28 VSS_169
J22 VSS_46 VSS_108 Y21 AT4 VSS_170
J25 VSS_47 VSS_109 Y24 AT19 VSS_171
J28 VSS_48 VSS_110 AB1 AT22 VSS_172
K1 VSS_49 VSS_111 AB2 AT30 VSS_173
K2 VSS_50 VSS_112 AB4 AU5 VSS_174
K4 VSS_51 VSS_113 AB10 AU8 VSS_175
K10 VSS_52 VSS_114 AB13 AU11 VSS_176
K22 VSS_53 VSS_115 AB16 AU14 VSS_177
K27 VSS_54 VSS_116 AB19 AU20 VSS_178
K30 VSS_55 VSS_117 AB22 AU23 VSS_179
K33 VSS_56 VSS_118 AD4 AU27 VSS_180
L5 VSS_57 VSS_119 AD9 AV4 VSS_181
L18 VSS_60 VSS_122 AD18 AV12 VSS_184 VSS_213 L24
L21 VSS_61 VSS_123 AD21 AV15 VSS_185 VSS_215 AL10
L25 VSS_62 VSS_124 AD24 AV25 VSS_186 VSS_214 AK21
FP4 REV 0.93 FP4 REV 0.93
FP4_BGA968 FP4_BGA968
B B
A A

FP3 GND
Custom 0.3
5 4 3 2 1
A B C D E
Main Func = DIMM1

+VREF_DQ +1.35V +1.35V DDRAB_SDQ[0..63]
DDRAB_SDQ[0..63] <7,14>
JDIMM1 DDRAB_SDM[0..7]
15mil 1 2
DDRAB_SDM[0..7] <7,14>
3 VREF_DQ VSS 4 DDRAB_SDQ4 DDRAB_SMA[0..15]
DDRAB_SMA[0..15] <7,14>
.1U_0402_16V7K
1000P_0402_50V7K
DDRAB_SDQ0 5 VSS DQ4 6 DDRAB_SDQ5
2 1 DQ0 DQ5
DDRAB_SDQ1 7 8
C179
C142
9 DQ1 VSS 10 DDRAB_SDQS0#
VSS DQS0# DDRAB_SDQS0# <7,14>
DDRAB_SDM0 11 12 DDRAB_SDQS0
1 2 13 DM0 DQS0 14 DDRAB_SDQS0 <7,14>
DDRAB_SDQ2 15 VSS VSS 16 DDRAB_SDQ6 MEM_MAB_RST# 1 2
Vinafix.com
DDRAB_SDQ3 17 DQ2 DQ6 18 DDRAB_SDQ7 C1274 NESD@
19 DQ3 DQ7 20 100P_0402_50V8J
DDRAB_SDQ8 21 VSS VSS 22 DDRAB_SDQ12
DDRAB_SDQ9 23 DQ8 DQ12 24 DDRAB_SDQ13
25 DQ9 DQ13 26
1
DDRAB_SDQS1# 27 VSS VSS 28 DDRAB_SDM1 1
<7,14> DDRAB_SDQS1# 29 DQS1# DM1 30
DDRAB_SDQS1 MEM_MAB_RST#
<7,14> DDRAB_SDQS1 DQS1 RESET# MEM_MAB_RST# <7,14>
31 32
37 DQ11 DQ15 38
43 DQ17 DQ21 44
DDRAB_SDQS2# 45 VSS VSS 46 DDRAB_SDM2
Place near DIMM1
<7,14> DDRAB_SDQS2# DQS2# DM2
DDRAB_SDQS2 47 48
<7,14> DDRAB_SDQS2 49 DQS2 VSS 50 DDRAB_SDQ22 +1.35V
DDRAB_SDQ19 53 DQ18 DQ23 54 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
55 DQ19 VSS 56 DDRAB_SDQ28
VSS DQ28 2 2 2 1 1 1 1 1 1 1
DDRAB_SDQ24 57 58 DDRAB_SDQ29
DDRAB_SDQ25 59 DQ24 DQ29 60 C109 C110 C111 C112 C113 C138 C149 C144 C125 C150
63 VSS DQS3# 64 DDRAB_SDQS3# <7,14> 1 1 1 2 2 2 2 2 2 2
DDRAB_SDM3 DDRAB_SDQS3
DM3 DQS3 DDRAB_SDQS3 <7,14>
65 66 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
71 DQ27 DQ31 72
VSS VSS
+0.675VS
DDRA_CKE0 73 74 DDRA_CKE1
<7,14> DDRAB_CKE0 CKE0 CKE1 DDRAB_CKE1 <7,14>
75 76 1U_0402_6.3V6K
77 VDD VDD 78 DDRAB_SMA15
NC A15 2 1 1
DDRAB_SBS2# 79 80 DDRAB_SMA14
<7,14> DDRAB_SBS2# BA2 A14
81 82 C130 C124 C131
DDRAB_SMA12 83 VDD VDD 84 DDRAB_SMA11
DDRAB_SMA9 85 A12/BC# A11 86 DDRAB_SMA7 1 2 2
87 A9 A7 88 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
DDRAB_SMA5 91 A8 A6 92 DDRAB_SMA4
93 A5 A4 94
2 2
99 A1 A0 100
DDRA_CLK0 101 VDD VDD 102 DDRA_CLK1
<7> DDRA_CLK0 DDRA_CLK0# 103 CK0 CK1 104 DDRA_CLK1#
DDRA_CLK1 <7> Follow CRB design
<7> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <7>
105 106
DDRAB_SMA10 107 VDD VDD 108 DDRAB_SBS1#
A10/AP BA1 DDRAB_SBS1# <7,14> +VREF_CA +1.35V
DDRAB_SBS0# 109 110 DDRAB_SRAS#
<7,14> DDRAB_SBS0# BA0 RAS# DDRAB_SRAS# <7,14>
111 112
DDRAB_SWE# 113 VDD VDD 114 DDRA_SCS0#
<7,14> DDRAB_SWE# WE# S0# DDRA_SCS0# <7>
2
DDRAB_SCAS# 115 116 DDRA_ODT0 +1.35V +0.675VS
<7,14> DDRAB_SCAS# 117 CAS# ODT0 118 DDRA_ODT0 <7>
R55
DDRAB_SMA13 119 VDD VDD 120 DDRA_ODT1 1K_0402_1%
A13 ODT1 DDRA_ODT1 <7>
DDRA_SCS1# 121 122 15mil
<7> DDRA_SCS1# S1# NC
10P_0402_50V8J
CD66
10P_0402_50V8J
CD68
10P_0402_50V8J
CD70
10P_0402_50V8J
CD72
10P_0402_50V8J
CD74
10P_0402_50V8J
CD76
10P_0402_50V8J
CD78
123 124 15mil
1
125 VDD VDD 126 +VREF_CA
TEST VREF_CA +VREF_CA 1 1 1 1 1 1 1
127 128
.1U_0402_16V7K
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_16V4Z
DQ32 DQ36
RF@
RF@
RF@
RF@
RF@
RF@
RF@
DDRAB_SDQ33 131 132 DDRAB_SDQ37 1 2
133 DQ33 DQ37 134 @ 2 2 2 2 2 2 2
C134
C167
VSS VSS 1 1 1
2
DDRAB_SDQS4# 135 136 DDRAB_SDM4 C145 C147 C148
<7,14> DDRAB_SDQS4# 137 DQS4# DM4 138
DDRAB_SDQS4 4.7U_0402_6.3V6K R56
<7,14> DDRAB_SDQS4 DQS4 VSS 2 1
139 140 DDRAB_SDQ38 1K_0402_1%
DDRAB_SDQ34 141 VSS DQ38 142 DDRAB_SDQ39 2 2 2
DQ34 DQ39
2.2U_0402_6.3V6M
CD67
2.2U_0402_6.3V6M
CD69
2.2U_0402_6.3V6M
CD71
2.2U_0402_6.3V6M
CD73
2.2U_0402_6.3V6M
CD75
2.2U_0402_6.3V6M
CD77
2.2U_0402_6.3V6M
CD79
DDRAB_SDQ35 143 144
1
VSS DQ44 1 1 1 1 1 1 1
DDRAB_SDQ41 149 DQ40 DQ45 150
DQ41 VSS
RF@
RF@
RF@
RF@
RF@
RF@
RF@
151 152 DDRAB_SDQS5#
153 VSS DQS5# 154 DDRAB_SDQS5# <7,14> 2 2 2 2 2 2 2
155 156
161 DQ43 DQ47 162
167 DQ49 DQ53 168
3 <7,14> DDRAB_SDQS6# DQS6# DM6 +VREF_DQ +1.35V 3
DDRAB_SDQS6 171 172
<7,14> DDRAB_SDQS6 173 DQS6 VSS 174 DDRAB_SDQ54
DQ50 DQ55
2
DDRAB_SDQ51 177 178
179 DQ51 VSS 180 DDRAB_SDQ60 R57
DDRAB_SDQ56 181 VSS DQ60 182 DDRAB_SDQ61 1K_0402_1%
DDRAB_SDQS7# <7,14> 15mil
1
DDRAB_SDM7 187 VSS DQS7# 188 DDRAB_SDQS7
189 190
0.1U_0402_16V4Z
DQ58 DQ62
4.7U_0603_6.3V6K
1000P_0402_50V7K
195 DQ59 DQ63 196
VSS VSS 1 1 1
2
197 198 MEM_MAB_EVENT# @ C137 C146
<Address: 00> SA0 EVENT# MEM_MAB_EVENT# <7,14>
C135
199 200 R59

+3VS VDDSPD SDA APU_SDATA0 <9,14>
1 2 2 201 202 1K_0402_1%
203 SA1 SCL 204 APU_SCLK0 <9,14> 2 2 2
+0.675VS VTT VTT +0.675VS
C136 C944 NESD@
1
.1U_0402_16V7K .1U_0402_16V7K C945 NESD@ 205 206
2 1 1 207 GND1 GND2 208
.1U_0402_16V7K BOSS1 BOSS2
FOX_AS0A621-J4SB-7H
CONN@
SP07000P110
DIMM_A H:4mm STD +1.35V +1.35V

330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
1 1
C151
C152
+ @ + @
4 4
2 2

DDR3 SODIMM-I Socket
C 0.3
A B C D E
A B C D E
Main Func = DIMM2

+VREF_DQ +1.35V +1.35V
15mil JDIMM2
1 2
3 VREF_DQ VSS 4 DDRAB_SDQ4 DDRAB_SDQ[0..63]
DDRAB_SDQ0 5 VSS DQ4 6 DDRAB_SDQ5 DDRAB_SDQ[0..63] <7,13>
.1U_0402_16V7K
1000P_0402_50V7K
DDRAB_SDQ1 7 DQ0 DQ5 8 DDRAB_SDM[0..7]
2 1 DQ1 VSS DDRAB_SDM[0..7] <7,13>
9 10 DDRAB_SDQS0#
C180
C143
VSS DQS0# DDRAB_SDQS0# <7,13> DDRAB_SMA[0..15]
DDRAB_SDM0 11 12 DDRAB_SDQS0 DDRAB_SMA[0..15] <7,13>
13 DM0 DQS0 14 DDRAB_SDQS0 <7,13>
1 2 DDRAB_SDQ2 15 VSS VSS 16 DDRAB_SDQ6
Vinafix.com
19 DQ3 DQ7 20 MEM_MAB_RST# 1 2
DDRAB_SDQ8 21 VSS VSS 22 DDRAB_SDQ12 C1275 NESD@
DDRAB_SDQ9 23 DQ8 DQ12 24 DDRAB_SDQ13 100P_0402_50V8J
25 DQ9 DQ13 26
1
DDRAB_SDQS1# 27 VSS VSS 28 DDRAB_SDM1 1
<7,13> DDRAB_SDQS1# 29 DQS1# DM1 30
DDRAB_SDQS1 MEM_MAB_RST#
<7,13> DDRAB_SDQS1 DQS1 RESET# MEM_MAB_RST# <7,13>
31 32
37 DQ11 DQ15 38
43 DQ17 DQ21 44
Place near DIMM1
<7,13> DDRAB_SDQS2# DQS2# DM2
DDRAB_SDQS2 47 48
<7,13> DDRAB_SDQS2 49 DQS2 VSS 50 DDRAB_SDQ22 +1.35V
DDRAB_SDQ19 53 DQ18 DQ23 54 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
VSS DQ28 2 2 2 1 1 1 1 1 1 1
DDRAB_SDQ25 59 DQ24 DQ29 60 C114 C117 C115 C118 C116 C155 C162 C158 C127 C165
63 VSS DQS3# 64 DDRAB_SDQS3# <7,13> 1 1 1 2 2 2 2 2 2 2
65 66 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M
71 DQ27 DQ31 72
VSS VSS
+0.675VS
DDRB_CKE0 73 74 DDRB_CKE1
<7,13> DDRAB_CKE0 CKE0 CKE1 DDRAB_CKE1 <7,13>
75 76 1U_0402_6.3V6K
77 VDD VDD 78 DDRAB_SMA15
NC A15 2 1 1
DDRAB_SBS2# 79 80 DDRAB_SMA14
<7,13> DDRAB_SBS2# BA2 A14
81 82 C132 C126 C133
DDRAB_SMA9 85 A12/BC# A11 86 DDRAB_SMA7 1 2 2
87 A9 A7 88 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
93 A5 A4 94
2 2
99 A1 A0 100
DDRB_CLK0 101 VDD VDD 102 DDRB_CLK1 +VREF_DQ
<7> DDRB_CLK0 103 CK0 CK1 104 DDRB_CLK1 <7> +VREF_CA
DDRB_CLK0# DDRB_CLK1#
<7> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <7>
105 106 15mil 15mil
DDRAB_SMA10 107 VDD VDD 108 DDRAB_SBS1#
A10/AP BA1 DDRAB_SBS1# <7,13>
DDRAB_SBS0# 109 110 DDRAB_SRAS# +VREF_DQ +VREF_CA
<7,13> DDRAB_SBS0# BA0 RAS# DDRAB_SRAS# <7,13>
111 112
VDD VDD
1000P_0402_50V7K
1000P_0402_50V7K
DDRAB_SWE# 113 114 DDRB_SCS0#
<7,13> DDRAB_SWE# WE# S0# DDRB_SCS0# <7>
0.1U_0402_16V7K
0.1U_0402_16V7K
DDRAB_SCAS# 115 116 DDRB_ODT0
<7,13> DDRAB_SCAS# 117 CAS# ODT0 118 DDRB_ODT0 <7>
VDD VDD 1 1 1 1
C161
C183
C186
DDRAB_SMA13 119 120 DDRB_ODT1 C159
A13 ODT1 DDRB_ODT1 <7>
DDRB_SCS1# 121 122 15mil
<7> DDRB_SCS1# 123 S1# NC 124
125 VDD VDD 126 2 2 2 2
TEST VREF_CA +VREF_CA
127 128
.1U_0402_16V7K
1000P_0402_50V7K
DQ32 DQ36 1 2
C139
C174
133 DQ33 DQ37 134
<7,13> DDRAB_SDQS4# 137 DQS4# DM4 138 2 1
DDRAB_SDQS4
<7,13> DDRAB_SDQS4 DQS4 VSS
139 140 DDRAB_SDQ38
153 VSS DQS5# 154 DDRAB_SDQS5# <7,13>
155 156
161 DQ43 DQ47 162
167 DQ49 DQ53 168
3 <7,13> DDRAB_SDQS6# DQS6# DM6 3
DDRAB_SDQS6 171 172
<7,13> DDRAB_SDQS6 173 DQS6 VSS 174 DDRAB_SDQ54
187 VSS DQS7# 188 DDRAB_SDQS7# <7,13>
189 190
195 DQ59 DQ63 196
1 2 DDRB_SA0 197 VSS VSS 198 MEM_MAB_EVENT#
SA0 EVENT# MEM_MAB_EVENT# <7,13>
R690 10K_0402_5% 199 200
+3VS VDDSPD SDA APU_SDATA0 <9,13>
1 201 202
203 SA1 SCL 204 APU_SCLK0 <9,13>
C140 <Address: 01> +0.675VS VTT VTT +0.675VS
.1U_0402_16V7K 205 206
2 207 GND1 GND2 208 +1.35V +1.35V
BOSS1 BOSS2
FOX_AS0A621-J4RB-7H
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
CONN@
SP07000J520
1 1
@ @
C156
C164
+ +
DIMM_B H:4mm REV 2 2
4 4

DDR3 SODIMM-II Socket
C 0.3
A B C D E
5 4 3 2 1
+APU_CORE_GFX
PU500
+19VB PL501 PWM P49
ISL62771HRTZ
Max:22A For Carrizo Only
Max:3.4A Max:5.5A
PJPDC1 +19V_ADPIN +19V_VIN +APU_CORE Max:22A
AC Adapter PL1 PQ740
NMOSFET
PQ718
NMOSFET
Charger
PWM PU703 PQ717
+19VB PL1001
PU1001
PWM P48
+19V_ADPIN
P41 Vinafix.com
PR703 PL700 NMOSFET ISL62771HRTZ +APU_CORE_NB
Max:12A
ISL95520 P42 Max:5.5A
D D
65W PR765
1206 PU300 PJP301
Max:11.3A
PL301 PWM +0.95VALWP PJP302 +0.95VALW
P47
RT8237EZQW
+17.4V_BATT+ Max:2A U15
LOAD SWITCH
0.95VSDGPU_OUT
J11
+0.95VSDGPU Max:2A
AMD Carrizo-L LA-C142 PR01 +INV_PWR_SRC For LCD APE8990 P26
RX4 0805
PL3
Backlight Max:8.5A U4
NMOSFET
+0.95VS
Max:8.5A
2014/09/13 AO4304L P26
+17.4V_BATT++
PL201
PU200
PWM P44
+0.675VSP PJP203 +0.675VS Max:2A 0603
+3VS_CAM
RT8207PGQW
+1.35VP PJP200 +1.35V Max:5A RX27 Max:0.5A
PJP201
PBATT1 UX4 +LCDVDD +LCDVDD_CONN
LOAD SWITCH LX1
Battery (4S)
PU1100 P53
+VGA_CORE SY6288 P16 Max:1.5A
PL1101 PWM
P41 ISL62771HRTZ Max:34A +3VALW
+APU_CORE RM10 1206
+APU_CORE_NB Max:2A
PU1400 +1.35V_MEM_GFX
Max:2A RM7 1206
+3VS_WLAN_NGFF
C
PL1401 PWM P51
SYX198DQNC
+1.35VGPUP PJP1401 Max:3.38A C
+APU_CORE_GFX U74 AP2821

LOAD SWITCH
P26
+3VGS Max:0.05A
(+0.775VALW)
Max:7.8A Max:5.07A
DIS@
+VDDCR_FCH_ALW) PU100 PJP100 +3VALW U2301 3VS +3VS

PL102 PWM PJP102 LOAD SWITCH J511
APW8822 P43 APE8990 P26
+1.35V
+19VB RE331 @
+0.95VS Max:5.5A +V_TP U78 P24 +3VS_TOUCH
+0.95VALW RE330 LOAD SWITCH
AP2821
Max:0.035A
+1.8VS
VDDCR_FCH_S5
+1.8V_ALW PU800 P50
PJP801 APL5336 LDO PJP802 +0.775VALW Max:0.2A
+3VS
+3VALW
Q135,Q2513, Q2515 For Carrizo Only
,Q2514 AO3416L +VDDCR_FCH_ALW
+1.5VS Q2516 , Q2507 DMN66
U2 ,LM393 P26
PU400 P45
Max:0.2A
+RTCBATT PJP401 LDO +1.5VSP PJP402 +1.5VS
APL5930 Max:0.3A
PU1200 P52 +1.8VGSP
PJP1201 LDO
APL5930
PJP1202 +1.8VGS
Max:0.5A
B B
PU600 +1.8V_ALW
PJP601 PWM
SY8003DFC
P46 PJP602 Max:2.0A
U15 +1.8VS_LS +1.8VS
UL3
LOAD SWITCH
+LAN_VDD33 LOAD SWITCH
APE8890 P26
J10 Max:1.5A
SY6288 P19
JP3 @
Max:0.07A
+APU_CORE
+APU_CORE_NB +3VS +V_TS
RX30 @ RX28 +VDD_TOUCH
0603
+APU_CORE_GFX
PJP101 +5VALW Max:7.8A RX29
+V_TS UX3
LOAD SWITCH
PJP103 APL3512 P16
(+0.775VALW)
+VDDCR_FCH_ALW
U2301 5VS J509 +5VS +5VS
LOAD SWITCH J510
+1.35V
APE8990 P26 Max:7.0A
FE1 Fuse
+0.95VS UI7
Max:2.0A @ P24 +5VS_KBL
USB Power SW
SY6288 P25
+5V_USB_PWR2
RE59
Max:0.5A
+0.95VS
+0.95VALW UI5
Max:2.0A JP7 +5VS_ODD
USB Power SW +5V_USB_PWR1 @
SY6288 P23
A
+1.8VS QS2P22
SI3456
Max:2.0A A
+1.8V_ALW NMOSFET
UE6
+3VS
FAN Power SW
APE8875 P24
+FAN_POWER Max:1.0A
+3VALW Security Classification Compal Secret Data Compal Electronics, Inc.
+1.5VS Issued Date 2014/06/10 Deciphered Date 2015/06/30 Title
+RTCBATT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Green CLK
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = LCD

+3VS
+5VS
1
R384
10K_0402_5% Q20
2
G
@ L2N7002LT1G_SOT23-3
@ Main: LTCX005Y400 (CIS ok)
2
3 1 EDP_HPD +3VS
<8> DP0_HPD
R6181 @ 2 EDP_AUXN_C
D
100K_0402_1% (TEMP:SP021403055)
LCD PWR CTRL Vinafix.com eDP Connector
1
1 @ 2 1 @ 2 EDP_AUXP_C
R407 R616 100K_0402_1%
+LCDVDD +3VS 0_0402_5% R365
100K_0402_5% JEDP CONN@
D D
W=60mils 42
2
UX4 W=60mils CX7 1 @ 2
<27> TS_RST#_EC
1 5 1 2 RX19 0_0402_5% +VDD_TOUCH 40
+3VS OUT IN 4.7U_0805_10V4Z 39
2 1 2 TS_RST#_R TS_RST#_R 38
RX10 GND DX1 <9> TS_RST#
RX17 @ 0_0402_5% 2 1 TS_EN_RR 37
1 2 3 4 2 1 <27> TS_EN_R 36
ENVDD_RE DISPOFF# DISPOFF# <27> RX25 33_0402_5%
OC EN <27> BKOFF#
10K_0402_5% USB20_TOUCH_P5 35
1
1 2 TS_EN_R USB20_TOUCH_N5 34
<9> TS_INT#
AP22802AW5-7 SOT25 5P RB751V-40_SOD323-2 RX18 @ 0_0402_5% 33
10K_0402_5% 32
RX9 +3VS_CAM
USB20_CAM_P7_R 31
+VDD_TOUCH Array MIC USB20_CAM_N7_R 30
2
2 @ 1 ENVDD_RE 29
<8> ENVDD
RX7 0_0402_5% A_MIC_DATA 28
<18> A_MIC_DATA
2 1 1 @ 2 TS_EN_R A_MIC_CLK 27
<27> EC_ENVDD <18> A_MIC_CLK
RX8 @ 0_0402_5% RX35 100K_0402_5% 26
INVTPWM 25
<8> INVTPWM 1 2 24
@ TS_RST#_R
RX24 100K_0402_5% 23
1
PANEL_SIZE_ID_CONN 22
RX26 DISPOFF# 21
100K_0402_5% INVTPWM 20
+LCDVDD +LCDVDD_CONN 19
+3VS 0.1U_0402_16V7K 2 1 C4314 EDP_TXP1_C 18
W=60mils <8> EDP_TXP1
2
0.1U_0402_16V7K 2 1 C4313 EDP_TXN1_C 17
1 2 <8> EDP_TXN1 16
2
FBMA-L11-201209-221LMA30T_0805 @ 0.1U_0402_16V7K 2 1 C4312 EDP_TXP0_C 15
<8> EDP_TXP0 2 1 C4311 14
LX1 RX16 0.1U_0402_16V7K EDP_TXN0_C
<8> EDP_TXN0
0.1U_0402_10V7K
CX11
4.7U_0805_10V4Z
CX8
10K_0402_5% 13
1 1 0.1U_0402_16V7K 2 1 C4322 EDP_AUXN_C 12
<8> EDP_AUXN 2 1 C4321 11
100_0402_5% 0.1U_0402_16V7K EDP_AUXP_C
<8> EDP_AUXP
1
1 2 RX3 PANEL_SIZE_ID_CONN 1 2 RX2 LCD_TST_C 10
<9> PANEL_SIZE_ID <27> LCD_TEST 9
100_0402_5% EDP_HPD
2 2 DBC_EN_R 8
1
7
RX11 6
C 0_0402_5% +LCDVDD_CONN 5 C
4
@ 3
2
2
+INV_PWR_SRC
W=60mils 1
41
ACES-CON40-18-GP
EMI@ SP021403055
+19VB +INV_PWR_SRC +INV_PWR_SRC LX6 ACES_51540-04001-P01_40P-T
W=60mils 1 2 USB20_CAM_P7_R
<10> USB20_CAM_P7 1 2
1 2
RX4 4 3 USB20_CAM_N7_R
<10> USB20_CAM_N7 4 3
0_0805_5%
10U_0603_6.3V6M
0.1U_0603_25V7K
1 1 WCM-2012HS-900T_4P
CX5 CX6
@ 1 2
2 2 RX22 0_0402_5%
NEMI@
1 2
RX21 0_0402_5%
NEMI@
USB20_TOUCH_N5
<10> USB20_TOUCH_N5
USB20_TOUCH_P5
<10> USB20_TOUCH_P5
3
+3VS +LCDVDD_CONN
NESD@
B B
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0805_10V6K
PESD5V0U2BT_SOT23-3
1 1 1
DX2
CX1
CX2
CX3
1
2 2 2
DBC_EN 1 @ 2 DBC_EN_R Place close to JEDP

+3VS +5VS * Touch Screen Panel <27> DBC_EN RX23 0_0402_1%
1
+V_TS +VDD_TOUCH @
Webcam PWR CTRL
1
RX28 RX36
@ RX30 RX29 2 @ 1 0_0402_5%
0_0603_5% @ 0_0603_1%
2
0_0603_1%
+V_TS
2
+3VS +3VS_CAM +VDD_TOUCH
UX3
RX27 1
1 @ 2 5 VOUT
VIN
0.1U_0402_10V7K
CX50
4.7U_0805_10V4Z
CX49
0_0603_1% 2 1 1
@1 4 GND @
SS @
1
0.1U_0402_10V7K
CX52
CX51 @ 3
4.7U_0805_10V4Z EN 2 2
2 APL3512ABI-TRG_SOT23-5
2 @
A 1 2 TS_EN_R A
<27> TS_EN
RX20 @ 0_0402_5%
Css Tss
0.1uF 100mS
10nF 10mS SS table
1nF 1mS Security Classification Compal Secret Data Compal Electronics, Inc.
Open or 1mS
tied to THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP / webcam / TouchScreen
VIN AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = HDMI
Vinafix.com HDMI@
R5409
D Place close to JHDMI 1 2 D

CX12 CX13 CX14 CX15 CX16 CX17 CX18 CX19
HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ 0R3J-0-U-GP
RX31 1 NEMI@ 2 0_0402_5% +VDISPLAY_VCC
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
WCM-2012HS-900T_4P TMDS_L_TXCN D5501
W=40mils
1
TMDS_TXCN 1 2 TMDS_L_TXCN EMI@ +5VS
2 1 2 1
1 2
10U_0603_6.3V6M
0.1U_0402_16V7K
150_0402_5% 1 1
CX21
NEMI@ CX12 2 1 0.1U_0402_10V7K TMDS_TXCN RB551V-30_SOD323-2 FX1
<8> DP1_TXN3_C RX43
NEMI@ CX13 2 1 0.1U_0402_10V7K TMDS_TXCP TMDS_TXCP 4 3 TMDS_L_TXCP CRT@ 1.5A_6V_1206L150PR~D CX22
<8> DP1_TXP3_C 4 3 TMDS_L_TXCP
2
NEMI@ CX14 2 1 0.1U_0402_10V7K TMDS_TX0N LX2 HDMI_EMI@ +3VS 2 2
<8> DP1_TXN2_C
NEMI@ CX15 2 1 0.1U_0402_10V7K TMDS_TX0P 1 2
<8> DP1_TXP2_C
RX32 NEMI@ 0_0402_5%
NEMI@ CX16 2 1 0.1U_0402_10V7K TMDS_TX1N
<8> DP1_TXN1_C
NEMI@ CX17 2 1 0.1U_0402_10V7K TMDS_TX1P
<8> DP1_TXP1_C
1
RX37 1 NEMI@ 2 0_0402_5%
NEMI@ CX18 2 1 0.1U_0402_10V7K TMDS_TX2N RX12
<8> DP1_TXN0_C WCM-2012HS-900T_4P
NEMI@ CX19 2 1 0.1U_0402_10V7K TMDS_TX2P TMDS_L_TX0N 10K_0402_5%
<8> DP1_TXP0_C
1
TMDS_TX0N 1 2 TMDS_L_TX0N EMI@ HDMI@
1 2
2
150_0402_5% JHDMI CONN@
TMDS_TX0P 4 3 TMDS_L_TX0P RX44 HDMI_HPLUG 19
4 3 HP_DET
1
2
3
4
4
3
2
1
TMDS_L_TX0P 18
2
RP59 RP58 LX3 HDMI_EMI@ 17 +5V
499_0804_8P4R_1% 499_0804_8P4R_1% 1 2 CPU_DPB_CTRLDAT_R 16 DDC/CEC_GND
RX38 NEMI@ 0_0402_5% CPU_DPB_CTRLCLK_R 15 SDA
HDMI@ HDMI@ 14 SCL
8
7
6
5
5
6
7
8
13 Reserved
1 NEMI@ 2 TMDS_L_TXCN 12 CEC
RX39 0_0402_5% TMDS_L_TX1N 11 CK- 23
CK_shield GND3
1
WCM-2012HS-900T_4P TMDS_L_TXCP 10 22
EMI@ CK+ GND2
TMDS_TX1N 1 2 TMDS_L_TX1N TMDS_L_TX0N 9 21
1 2 150_0402_5% 8 D0- GND1 20
RX45 TMDS_L_TX0P 7 D0_shield GND0
+3VS TMDS_TX1P 4 3 TMDS_L_TX1P TMDS_L_TX1P TMDS_L_TX1N 6 D0+
2
4 3 D1-
1
5
D LX4 HDMI_EMI@ TMDS_L_TX1P 4 D1_shield
C D1+ C
2 QX3 1 2 TMDS_L_TX2N 3
G 2N7002K_SOT23-3 RX40 NEMI@ 0_0402_5% 2 D2-
D2_shield
1
S HDMI@ TMDS_L_TX2P 1
RX13 D2+
3
100K_0402_5% C-K_96067-3K28-192-124
HDMI@ 1 NEMI@ 2 DC021407310
RX41 0_0402_5%
2
LX5 HDMI_EMI@
TMDS_TX2P 4 3 TMDS_L_TX2P TMDS_L_TX2P
4 3
1
TMDS_TX2N 1 2 TMDS_L_TX2N
EMI@
150_0402_5%
Main: LTCX0064K00 (CIS ok)
1 2
WCM-2012HS-900T_4P
RX46
TMDS_L_TX2N
(TEMP:DC021407310)
2
1 2
RX42 NEMI@ 0_0402_5%
46@ ROYALTY HDMI W/LOGO

TMDS_TXCN NEMI@
NEMI@CV357
CV357 1 2 1P_0402_50V8J TMDS_L_TXCN NEMI@ CX23 1 2 3.3P_0402_50V8C
Part Number Description
TMDS_TXCP NEMI@
NEMI@CV358
CV358 1 2 1P_0402_50V8J TMDS_L_TXCP NEMI@ CX24 1 2 3.3P_0402_50V8C RO0000002HM HDMI W/Logo:RO0000002HM
TMDS_TX0N NEMI@
NEMI@CV359
CV359 1 2 1P_0402_50V8J TMDS_L_TX0N NEMI@ CX25 1 2 3.3P_0402_50V8C
TMDS_TX0P NEMI@
NEMI@CV360
CV360 1 2 1P_0402_50V8J TMDS_L_TX0P NEMI@ CX26 1 2 3.3P_0402_50V8C
TMDS_TX1N NEMI@
NEMI@CV361
CV361 1 2 1P_0402_50V8J TMDS_L_TX1N NEMI@ CX27 1 2 3.3P_0402_50V8C
TMDS_TX1P NEMI@
NEMI@CV362
B TMDS_TX2N NEMI@
NEMI@CV363
CV363 1 2 1P_0402_50V8J TMDS_L_TX2N NEMI@ CX29 1 2 3.3P_0402_50V8C B
TMDS_TX2P NEMI@
NEMI@CV364
+3VS
+VDISPLAY_VCC RP63
8 1 APU_HDMI_CLK
7 2 APU_HDMI_DATA
6 3 CPU_DPB_CTRLDAT_R
5 4 CPU_DPB_CTRLCLK_R +3VS
2.2K_0804_8P4R_5%
CRB use 4.7k, CL use 2.2k
HDMI@
1
C
HDMI@ QX5 2 1 2 HDMI_HPLUG
MMBT3904_NL_SOT23-3 B
+3VS E RX15 1
1
<8,31> DP1_HPD 150K_0402_5% HDMI@
HDMI@ CX20 @
1
220P_0402_50V8J RX34
HDMI@ 2 20K_0402_5%
RX14
2
HDMI@ 100K_0402_5%
QX4B
2
2
DMN66D0LDW-7_SOT363-6
G
1 6 CPU_DPB_CTRLCLK_R
<8> APU_HDMI_CLK
S
D
5
G
4 3 CPU_DPB_CTRLDAT_R
<8> APU_HDMI_DATA
S
QX4A
3
HDMI@
A D20 A
PESD24VS2UT_SOT23-3
NEMI@
1

HDMI
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = Audio CA53, CA55 change Value

CA71, CA51 place close to Pin 26 from 10U_0603_6.3V6M~D to
4.7U_0603_6.3V6K
CA57,CA58 close +5VA +5V_PVDD +5V_PVDD
to UA1 pin1
4.7U_0603_6.3V6K
CA71
4.7U_0603_6.3V6K
CA53
4.7U_0603_6.3V6K
CA55
1 1 1
+3VS
1 1 1
0.1U_0402_16V7K
CA51
0.1U_0402_16V7K
CA54
0.1U_0402_16V7K
CA56
1 1
2 2 2
0.1U_0402_16V7K
CA58
4.7U_0402_6.3V6K
CA57
1
Vinafix.com
2 2 2
4.7U_0603_6.3V6K
CA66
2 2
2
D D
CPVDD 1
+3VS +CODEC_AVDD2
UA1 CA61
CA59 CA60 close 1 1 1
4.7U_0603_6.3V6K
CA70
CA59 CA60 1 26 4.7U_0603_6.3V6K
4.7U_0402_6.3V6K 0.1U_0402_16V7K DVDD AVDD1 40
to UA1 pin9 9 AVDD2 2
2 2 2 +1.5VS DVDD-IO
36 CPVDD
CPVDD 41 +1.5VS +CODEC_AVDD2
6 PVDD1 46
<9> HDA_BITCLK_AUDIO BCLK PVDD2 1 @ 2
5 RA8 0_0402_5%
<9> HDA_SDOUT_AUDIO SDATA-OUT 13 RA13 1 2 100K_0402_5%
HP/LINE1 JD(JD1) +3VS
10 14
<9> HDA_SYNC_AUDIO SYNC MIC2/LINE2 JD(JD2) 15 1 2 JACK_SENSE#
1 2 8 SPDIFO/FRONT JD(JD3)/GPIO3 RA34 200K_0402_1%
<9> HDA_SDIN0 SDATA-IN
RA130 22_0402_5%
11
<9> HDA_RST#_AUDIO RESETB 32 HPOUT-L
HPOUT-L(PORT-I-L) 33 HPOUT-R
LINE1-R 21 HPOUT-R(PORT-I-R)
LINE1-L 22 LINE1-R(PORT-C-R)
Line1-VREFO-R 30 LINE1-L(PORT-C-L)
Line1-VREFO-L 31 LINE1-VREFO-R 42 INT-SPK-L+ +5V_PVDD +5VS +MIC2-VREFO
23 LINE1-VREFO-L SPK-OUT-L+ 43 INT-SPK-L-
24 LINE2-R(PORT-E-R) SPK-OUT-L- 45 INT-SPK-R+ RA1110
LINE2-L(PORT-E-L) SPK-OUT-R+ 44 INT-SPK-R- 2 @ 1
+A_VCC SPK-OUT-R-
16 +5VA 0_0603_1% +5VS 2 1 SLEEVE
MONO-OUT RA53 2.2K_0402_5% RA29 1 @ 2 0_0603_1%
2 RA1111
1 2 +MIC2-VREFO 29 GPIO0/DMIC-DATA 3 MIC_CLK_C A_MIC_DATA <16> 2 1 2 1 RING2 1 2 0_0603_1%
+3VALW @ +MIC2-VREFO @ RA30 @
RA10 0_0402_5% RING2 17 MIC2-VREFO GPIO1/DMIC-CLK 48 RA1109 2.2K_0402_5%
SLEEVE 18 MIC2-L(PORT-F-L)/RING SPDIF-OUT/GPIO2 0_0603_1% RA31 1 @ 2 0_0603_1%
C MIC2-R(PORT-F-R)/SLEEVE C
2 1 MIC1-L 19
10U_0603_6.3V6M CA74 MIC_CAP 37 RA32 1 @ 2 0_0603_1%
CBP 35 1U_0402_6.3V6K 2 1 CA24
20 CBN
+A_VCC NC
EC_MUTE# 47
<27> EC_MUTE# PDB 28 2 1
RA12 1 2 100K_0402_5% VREF 12
2.2U_0603_6.3V6K CA23 GNDA GND
CA62 1 2 10U_0603_6.3V6M 27 PCBEEP 34 1U_0402_6.3V6K 2 1 CA25
CA63 1 2 10U_0603_6.3V6M 39 LDO1-CAP CPVEE
NEMI@ CA64 1 2 10U_0603_6.3V6M 7 LDO2-CAP
RA1112 LDO3-CAP Place on the moat between GND & GNDA.
0_0402_5% 0_0402_5%
HDA_BITCLK_AUDIO 1 2 1 2 4 25
@ RA1113 DVSS AVSS1 38
49 AVSS2
1 GND
NEMI@
CA21 ALC3234-CG_MQFN48_6X6
22P_0402_50V8J SA000076U00
2 LA1 EMI@
MIC_CLK_C 1 2 A_MIC_CLK DA8
A_MIC_CLK <16> 2
BLM15BB221SN1D_2P
PC_BEEP 2 1 RA79 2 1 CA65 EC Beep <27> BEEP#
1K_0402_1% 0.1U_0402_16V7K 1 PC_BEEP
SM01000BV00 1
NEMI@
100P_0402_50V8J 2 1 CA69 @ CA22 3
need CIS symbol MCU Beep <9> APU_SPKR
1
22P_0402_50V8J
2 BAT54C-7-F_SOT23-3 @
1 2 RA19
RA81 10K_0402_5% 10K_0402_5%
2
+RTCVCC
PC Beep
1
SLEEVE
B RA5 Close to UA1 B
@ 470K_0402_5% Pin11,13,14,16
close to Codec
2
JSPK CONN@
3
INT-SPK-R+ EMI@ LA3 1 2 NBQ160808T-800Y-N 0603 SPK_R+_CONN 1 5

5 G
D
QA6A INT-SPK-R- EMI@ LA4 1 2 NBQ160808T-800Y-N 0603 SPK_R-_CONN 2 1 G5
QA6B S DMN66D0LDW-7_SOT363-6 INT-SPK-L+ EMI@ LA5 1 2 NBQ160808T-800Y-N 0603 SPK_L+_CONN 3 2
DMN66D0LDW-7_SOT363-6 @ RING2_R INT-SPK-L- EMI@ LA6 1 2 NBQ160808T-800Y-N 0603 SPK_L-_CONN 4 3
4
RING2_R <25> 4
6
1 2 2 6
D
HDA_RST#_AUDIO @
Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R-
G
G6
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
RA6 10K_0402_5% S @ JACK_SENSE#
JACK_SENSE# <25>
1 1 1 1 ACES_50224-0040N-001
1
3
Speaker 4 ohm : 40mil
EMI@ CA29
EMI@ CA30
EMI@ CA31
EMI@ CA32
SP011204198
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
AUD_HP_OUT_L_CN
AUD_HP_OUT_R_CN AUD_HP_OUT_L_CN <25>
SLEEVE_R
AUD_HP_OUT_R_CN <25>
Speaker 8 ohm : 20mil 2 2 2 2 ESD@
DA13
ESD@
DA14
SLEEVE_R <25>
1
HPOUT-L 1 2 HPOUT-R-L
iPhone and Nokia type Combo Jack
RA55 10_0402_5% EMI@
HPOUT-R 1 2 HPOUT-R-R SLEEVE LA7 2 1 0_0402_5% 40mil SLEEVE_R
RA56 10_0402_5% EMI@
RING2 LA10 2 1 0_0402_5% 40mil RING2_R
4.7U_0603_6.3V6K EMI@
1
A LINE1-L CA671 2 1 ESD@ 2 HPOUT-R-L LA8 2 1 0_0603_5% AUD_HP_OUT_L_CN A

RA80 1K_0402_1% @ @ EMI@
LINE1-R 1 2 1 ESD@ 2 RA83 RA84 HPOUT-R-R LA9 2 1 0_0603_5% AUD_HP_OUT_R_CN
CA68 RA82 1K_0402_1% 10K_0402_5% 10K_0402_5%
4.7U_0603_6.3V6K
Place CAP and ESD Diode on D/B
2
Line1-VREFO-L RA165 1 2 4.7K_0402_5%
Line1-VREFO-R RA166 1 2 4.7K_0402_5%

Audio Codec ALC3234
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
0.3
5 4 3 2 1
1 2 3 4 5
Main Func = LAN
+3VALW OPEN +LAN_VDD33 +LAN_IO rising time : >1ms and <100ms 60mils_3via
JP3 2 1000@ 1
+LAN_REGOUT RL1 +LAN_VDD10
2 1
0_0603_5%
40mils_2via CL10 add by 9/6
Vinafix.com 2MM LAN_SW@

W=40mils W=40mils +LAN_REGOUT 1
2
LL1
W=40mils 2.2UH_LQM2MPN2R2NG0L_30%
A 1 1 1 1 1 1 1 1 A
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1U_0402_6.3V4Z
0.1U_0402_25V6
LAN_SW@
4.7U_0603_6.3V6K
+3VALW +LAN_VDD33 +LAN_VDD33
CL5
CL6
CL7
CL8
CL9
CL10
CL4
CL3
CL39
1.5A 0.1U_0402_25V6
2 1000@ 2 2 2 2 2 2 2
1U_0402_6.3V6K UL3
4.7U_0603_6.3V6K
CL19
2 1 5 1
0.1U_0402_10V7K
IN OUT +3VALW
1 1
2
GND RL40
CL15
WOL_EN 4 3 2 1
<27> WOL_EN EN OC 2 2 RTL811G(LDO mode) RTL811G(SWR mode)
10K_0402_5% Place close Place close
to UL1.3/UL1.8 to UL1.22
AP22802AW5-7 SOT25 5P
and UL1.30
2
RL27
100K_0402_5% Place close to UL1: Pin 11
+LAN_VDD33 RL6 +LAN_VDDREG
0_0603_1%
1
1 @ 2
0.1U_0402_16V7K
CL12 1000@
4.7U_0603_6.3V6K
CL13 1000@
10U_0603_6.3V6M
CL14 @
0.1U_0402_16V7K
CL16 1000@
4.7U_0603_6.3V6K
CL17 1000@
1 1 1 1 1
2 2 2 2 2
TL1 TL2
UL1 100@ +LAN_VDD10

CL30, CL31 close to UL1 Pin 17, 18
<6> PCIE_ARX_DTX_P0
CL30 1
CL31 1
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
PCIE_ARX_DTX_P0_C
PCIE_ARX_DTX_N0_C
17
18 HSOP AVDD10
3
8
These caps close to UL1: Pin 11,32
+LAN_VDD33 Rising time (10%~90%) 要>1mS and <100mS
B <6> PCIE_ARX_DTX_N0 HSON AVDD10 B
30 S X'FORM_ NS0015 LF LAN S X'FORM_ NS0015 LF LAN
AVDD10 22
DVDD10 +LAN_VDD33
SP050005Y00 SP050005Y00
11 1000@
AVDD33 32
PCIE_PTX_C_DRX_P0 13 AVDD33
<6> PCIE_ATX_C_DRX_P0 HSIP
PCIE_PTX_C_DRX_N0 14 23 +LAN_VDDREG
<6> PCIE_ATX_C_DRX_N0 HSIN VDDREG 24 +LAN_REGOUT
REGOUT
1 MDI0+
MDIP0 2 MDI0-
MDIN0 4 MDI1+
PLT_RST#_R 19 MDIP1 5 MDI1-
PERSTB MDIN1 TL1
ISOLATEB 20 15
ISOLATEB REFCLK_P
REFCLK_N
16
CLK_PCIE_LAN <10>
CLK_PCIE_LAN# <10> MDI1-
MDI1+
1
2 RD+ RX+
16
15
MDO1-
MDO1+
Place close to TCT pin
APU_PCIE_WAKE# 21 12 +V_DAC 3 RD- RX- 14 MCT1
<9,27> APU_PCIE_WAKE# LANWAKEB CLKREQB LAN_CLKREQ# <9> CT CT
28 XTLO 4 13 MCT0 RL19 1 2 75_0603_5%
1 2 26 CKXTAL1 29 XTLI 5 NC NC 12 MCT1 RL20 1 2 75_0603_5%
+LAN_VDD33 LED1/GPO CKXTAL2 NC NC
RL39 @ 10K_0402_5% +V_DAC 6 11 MCT0 MCT2 RL41 1 2 75_0603_5%
25 T94 MDI0- 7 CT CT 10 MDO0- MCT3 RL42 1 2 75_0603_5%
MDI2+ 6 LED2 27 T95 MDI0+ 8 TD+ TX+ 9 MDO0+
T-GND_L
MDI2- 7 NC LED0 TD- TX-
MDI3+ 9 NC 31 RL31 2 1 2.49K_0402_1%~D
MDI3- 10 NC RSET 350UH_LF-H1201P-2
NC 33
GND @ 1
+V_DAC EMI@
@ RTL8106E-CG QFN 32P E-LAN CTRL TL2 CL33
PLT_RST# 1 2 PLT_RST#_R 2 100P_1206_2KV8J
<9,20,27> PLT_RST# 2
RH29 SA000065Y00 MDI2+ 1 16 MDO2+
0_0402_5% CL41 MDI2- 2 RD+ RX+ 15 MDO2- T-GND
+V_DAC 3 RD- RX- 14 MCT2
0.01U_0402_16V7K CT CT
C APU_PCIE_RST# 1 @ 2 1 4 13 C
<9,20,33> APU_PCIE_RST# NC NC
RH31 0_0402_5% UL1 1000@ 5 12
+V_DAC 6 NC NC 11 MCT3
MDI3+ 7 CT CT 10 MDO3+
MDI3- 8 TD+ TX+ 9 MDO3-
TD- TX-
RTL8111G-CG QFN 32P E-LAN CTRL 350UH_LF-H1201P-2

@
SA00005V700 Main: DC23400AI00 (CIS ok)
JLAN CONN@
MDO3- 8
+LAN_VDD33 +3VS PR4-
MDO3+ 7
PR4+
MDO1- 6
PR2-
1
1 2 APU_PCIE_WAKE#
RL34 10K_0402_5% RL33 MDO2- 5
1K_0402_5% PR3-
MDO2+ 4
CL36 PR3+
2
+3VS +LAN_VDD33 2 1 XTLI MDO1+ 3

ISOLATEB PR2+
10P_0402_50V8J YL2 MDO0- 2 9
1 2 PR1- GND
XTAL0 GND0
1
MDO0+ 1 10
RL35 3 4 PR1+ GND
15K_0402_1% XTAL1 GND1
LAN_CLKREQ# 1 2 CL37 25MHZ_10PF_7V25000014 T-GND
RL37 @ 10K_0402_5% 2 1 XTLO
2
WOL_EN 1 2 10P_0402_50V8J
D D
RL38 @ 10K_0402_5% SDAN_601028-008041
DC23400AI00
XTAL
Reserve 10K pull LAN_IO
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2014/06/10 Deciphered Date 2015/06/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL LAN RTL8106EUS
Custom 0.3
Date:
Tulip AAL12
Friday, February 13, 2015 Sheet 19
LA-C142P
of 56
1 2 3 4 5
5 4 3 2 1
Main Func = WLAN

closed to pin 2, 4 closed to pin 64, 66
+3VS_WLAN_NGFF
+3VS_WLAN_NGFF +3VS_WLAN_NGFF
10P_0402_50V8J
CM8
10P_0402_50V8J
CM10
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
1 1 1 1 1 1
Vinafix.com
CM4
CM6
CM5
CM7
RF@
RF@
2 2 2 2 2 2
D D
2.2U_0402_6.3V6M
CM9
2.2U_0402_6.3V6M
CM11
1 1
RF@
RF@
+3VS_WLAN_NGFF 2 2
NGFF WL Con (A Key)

JNGFF
1 2
USB20_MINI1_P4 3 GND 3.3VAUX 4
<10> USB20_MINI1_P4 5 USB_D+ 3.3VAUX 6
USB20_MINI1_N4
<10> USB20_MINI1_N4 7 USB_D- LED1# 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13
15
SDIO_CMD
SDO_DAT0
PCM_IN
PCM_OUT
14
16
+3VS TO +3VS_WLAN_NGFF
17 SDO_DAT1 LED2# 18
19 SDO_DAT2
SDO_DAT3
GND
UART_WAKE#
20 80mil
21 22
23 SDIO_WAKE# UART_RX 1 2
SDIO_RESET# +3VS +3VS_WLAN_NGFF
For EC to detect RM7 0_1206_5%
1 @ 2
+3VALW +3VS_WLAN_NGFF
debug card insert. RM10 0_1206_5%
24 RM9 1 2 100K_0402_5%
25 UART_TX 26
27 GND UART_CTS 28
<6> PCIE_ATX_C_DRX_P1 PETP0 UART_RTS
<6> PCIE_ATX_C_DRX_N1
29 30 E51_TX1 0_0402_5% 2 @ 1 R23 EC_TX
31 PETN0 RESERVED 32 EC_TX <27>
C E51_RX1 0_0402_5% 2 @ 1 R24 EC_RX C
33 GND RESERVED 34 EC_RX <27> +3VS_WLAN_NGFF +3VS
<6> PCIE_ARX_DTX_P1 35 PERP0 RESERVED 36
<6> PCIE_ARX_DTX_N1 37 PERN0 COEX3 38
GND COEX2
1
CLK_PCIE_WLAN 39 40
<10> CLK_PCIE_WLAN REFCLKP0 COEX1
CLK_PCIE_WLAN# 41 42 RM8
<10> CLK_PCIE_WLAN# REFCLKN0 SUSCLK
43 44 PLT_RST#_RW 10K_0402_5%~D QM1
GND PERST0#
2
WLAN_CLKREQ# 45 46 BT_ON# DII-DMN65D8LW-7~D
G
<9> WLAN_CLKREQ# 47 CLKEQ0# W_DISABLE2# 48 BT_ON# <9>
WLAN_WAKE# WL_OFF#_R
<27> WLAN_WAKE#
2
49 PEWAKE0# W_DISABLE1# 50 WL_OFF#_R 1 3
GND I2C_DATA WL_OFF# <10>
51 52
S
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
57 GND RESERVED 58 E51_TX2 0_0402_5% 2 @ 1 R25 EC_TX
RSRVD/PERP1 RESERVED EC_TX <27> Prevent Backdriver from +3VS_WLAN_NGFF to +3VS
59 60 E51_RX2 0_0402_5% 2 @ 1 R26 EC_RX
61 RSRVD/PERN1 RESERVED 62 EC_RX <27>
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
For V4DA2 debug board
67 RESERVED 3.3VAUX
GND
69 68
MTG77 MTG76
LCN_DAN05-67406-0100
CONN@ @
PLT_RST#_RW 0_0402_5% 1 2 RM6
2 1 PLT_RST# <9,19,27>
@ APU_PCIE_RST#
APU_PCIE_RST# <9,19,33>
0_0402_5% RH32
B B
A A

NGFF WLAN
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = Card Reader
Vinafix.com
D D
SD_CD#
1
CR9 EMI@
22P_0402_50V8J
+3VS +VCC_3IN1 2
Trace width:40mil For EMI request. Place close to UR1
5
UR1
CARD_3V3
3V3_IN
RR1 2 1 6.19K_0402_1% RREF 1 22
EMI@ RREF SP14 21 SD_D2
LR2 SP13 20 MS_D1_SD_D3
<10> USB20_CR_P0
USB20_CR_P0 4
4 3
3 USB20_CR_P0_R USB20_CR_N0_R 2
DM
SP12
SP11
19 close to chip side
USB20_CR_P0_R 3 18 SD_CMD
DP SP10 16
USB20_CR_N0 1 2 USB20_CR_N0_R SP9 15 MS_D2_SD_CLK_R 1 2 MS_D2_SD_CLK
<10> USB20_CR_N0 1 2 SP8
WCM-2012HS-900T_4P EMI@
RTS5170-GR_QFN24 RR2
14 22_0402_5%
7 SP7 13 SD_CD#
23 XD_CD# SP6 12
17 XD_D7 SP5 11 SD_D0
USB20_CR_N0 GPIO0 SP4 10 SD_D1 MS_D2_SD_CLK MS_CLK_SD_WP
Thermal pad
6 SP3 9
SDREG SP2
1
1
C V18 24 8 MS_CLK_SD_WP_R 1 2 MS_CLK_SD_WP C
R808 V18 SP1 R809 R810
@ 300_0402_5% EMI@ 1 1 @ 300_0402_5% @ 300_0402_5%
5P_0402_50V8C
CR5
EMI@
5P_0402_50V8C
CR6
EMI@
2 2 RR3
22_0402_5%
2
25
2
1U_0402_6.3V6K
CR3
1U_0402_6.3V6K
CR4
1 RTS5170-GR_QFN24_4X4 1 1
C157 2 2 C160 C163
@ 15P_0402_50V8J 1 1 @ 15P_0402_50V8J @ 15P_0402_50V8J
SA00005T300
2 2 2
AMD request 5/16

+3VS
1 1
CR1 CR2
0.1U_0402_10V7K 4.7U_0603_6.3V6K
2 2
+VCC_3IN1
JREAD
B B
4
SD_CMD 2 VDD
MS_D2_SD_CLK 5 CMD
3 CLK
6 VSS1
+VCC_3IN1 VSS2
SD_D0 7
SD_D1 8 DAT0
SD_D2 9 DAT1
MS_D1_SD_D3 1 DAT2
CD/DAT3
12
GND 13
1 1 GND
CR8 CR7 MS_CLK_SD_WP 11 14
SD_CD# 10 W/P GND 15
4.7U_0603_6.3V6K 0.1U_0402_10V7K CD GND
2 2 TAI_PSDATG-11GLBS1NN4H0
TAI_PSDATG-11GLBS1NN4H0_11P-T
Part Number = DC0214090500
CONN@
Close to JREAD
SD_CMD
1
CR11 EMI@
A 22P_0402_50V8J A
2
For EMI request.

Place close to JREAD
Card Reader RTS5179
0.3
5 4 3 2 1
A B C D E F G H
Main Func = HDD

JHDD2
12
11 GND
GND
+3VS
US2 TI@ US2 @

Vinafix.com US2 PARADE@ SATA_ARX_RC_DTX_P0_C
SATA_ARX_RC_DTX_N0_C
CLRP5
CLRP4
1@
1@
2 SHORT PADS
2 SHORT PADS
SATA_ARX_RC_DTX_P0_C_R
SATA_ARX_RC_DTX_N0_C_R
10
9
8
10
9
8
SATA_ATX_RC_DRX_N0_C CLRP3 1@ 2 SHORT PADS SATA_ATX_RC_DRX_N0_C_R 7
SATA_ATX_RC_DRX_P0_C CLRP2 1@ 2 SHORT PADS SATA_ATX_RC_DRX_P0_C_R 6 7
1 6 1
5
5
0.01U_0402_16V7K
0.1U_0402_25V6K
SN75LVCP601RTJR PI3EQX6741STZDEX PS8527CTQFN20GTR2-A2 DEVSLP0_HDD RS45 1 @ 2 0_0402_5% DEVSLP0_HDD_R 4
3 4
1 1 3
2
SA00003ZX00 SA00004H100 SA00007JU10 2
2
4.7K_0402_5%
RS33
4.7K_0402_5%
RS34
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
+5V_HDD
1
1
1
CS42
CS27
2 2
RS25
RS26
RS27
RS28
ACES_50208-01001-001
@ @ @ @ CONN@
1
+3VS
CZL@ TI@ SP01000JF10
2
US2 @
RS19 1 @ 2 0_0402_5% 7 6 DEW2
EN VDD 16 DEW1
CS37 1 2 0.01U_0402_16V7K SATA_ATX_C_DRX_P0 1 VDD
<10> SATA_ATX_DRX_P0 A_INp
<10> SATA_ATX_DRX_N0 CS36 1 2 0.01U_0402_16V7K SATA_ATX_C_DRX_N0 2 10
A_INn NC 20 HDD_REXT_SATA0
CS35 1 2 0.01U_0402_16V7K SATA_ARX_C_DTX_P0 5 REXT
<10> SATA_ARX_DTX_P0 B_OUTp
CS33 1 2 0.01U_0402_16V7K SATA_ARX_C_DTX_N0 4 9 HDD_A0_PRE0 JHDD1
<10> SATA_ARX_DTX_N0 B_OUTn A_PRE0 8 14
HDD_B0_PRE0
RS29 1 @ 2 0_0402_5% HDD_B0_PRE1 17 B_PRE0 13 GND
+3VS B_PRE1 GND
RS30 1 @ 2 0_0402_5% HDD_A0_PRE1 19 15 SATA_ATX_RC_DRX_P0 CS30 1 2 0.01U_0402_16V7K SATA_ATX_RC_DRX_P0_C
A_PRE1 A_OUTp 14 SATA_ATX_RC_DRX_N0 CS32 1 2 0.01U_0402_16V7K SATA_ATX_RC_DRX_N0_C 12
RS20 1 @ 2 0_0402_5% 18 A_OUTn SATA_ATX_RC_DRX_P0_C 11 12
3 TEST 11 SATA_ARX_RC_DTX_P0 CS34 1 2 0.01U_0402_16V7K SATA_ARX_RC_DTX_P0_C SATA_ATX_RC_DRX_N0_C 10 11
RS22 1 @ 2 0_0402_5% HDD_B0_EQ 13 GND B_INp 12 SATA_ARX_RC_DTX_N0 CS31 1 2 0.01U_0402_16V7K SATA_ARX_RC_DTX_N0_C 9 10
21 GND B_INn SATA_ARX_RC_DTX_N0_C 8 9
EPAD SATA_ARX_RC_DTX_P0_C 7 8
SN75LVCP601RTJR_QFN20_4X4 6 7
+5V_HDD Source <10> DEVSLP0_HDD

RS8 1 @ 2 0_0402_5% JHDD_P10 5
4
3
6
5
4
+3VS +5V_HDD 3
2
1 2
+5V_HDD +5VS 1
JP13 ACES_51625-01201-001
RS38 1 @ 2 0_0402_5% 1 2 DC021408183
1 2 CONN@
2 2
HDD_B0_EQ RS37 1 @ 2 0_0402_5% JUMP_43X79
DEW2 RS35 1 TI@ 2 4.7K_0402_5%
DEW1 RS36 1 TI@ 2 4.7K_0402_5%

SHORT
+5V_HDD
HDD_B0_PRE0 RS21 1 @ 2 0_0402_5%
HDD_B0_PRE1 RS18 1 @ 2 0_0402_5%
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
HDD_A0_PRE1 RS23 1 @ 2 0_0402_5%
1 1 1
SATA_ATX_DRX_P0 RS41 1 NRDSA@2 0_0402_5% SATA_TX_P0 CS38 1NRDSA@
2 0.01U_0402_16V7K SATA_ATX_RC_DRX_P0_C HDD_A0_PRE0 RS24 1 @ 2 2K_0402_5%
CS5 CS6 CS7
SATA_ATX_DRX_N0 RS42 1 NRDSA@2 0_0402_5% SATA_TX_N0 CS39 1NRDSA@
2 0.01U_0402_16V7K SATA_ATX_RC_DRX_N0_C HDD_REXT_SATA0 RS31 1 @ 2 5.1K_0402_1%
2 2 2
SATA_ARX_DTX_P0 RS43 1 NRDSA@2 0_0402_5% SATA_RX_P0 CS40 1NRDSA@

2 0.01U_0402_16V7K SATA_ARX_RC_DTX_P0_C
SATA_ARX_DTX_N0 RS44 1 NRDSA@2 0_0402_5% SATA_RX_N0 CS41 1NRDSA@

2 0.01U_0402_16V7K SATA_ARX_RC_DTX_N0_C
3
ODD Power Control SATA ODD Connector (FFC Type) 3
SATA_ATX_DRX_P1 1 2 ODD@ SATA_ATX_DRX_P1_C JODD

SOC TX <10> SATA_ATX_DRX_P1
SATA_ATX_DRX_N1
CS8
1
0.01U_0402_16V7K
2 ODD@ SATA_ATX_DRX_N1_C 1 GND1
21
OPEN
JP7
<10> SATA_ATX_DRX_N1
SATA_ARX_DTX_P1
CS9
1
0.01U_0402_16V7K
2 ODD@ SATA_ARX_DTX_P1_C
SATA_ATX_DRX_P1_C
SATA_ATX_DRX_N1_C
2
3
1
2
1
1 2
2 SOC RX <10> SATA_ARX_DTX_P1
SATA_ARX_DTX_N1
CS13
1
0.01U_0402_16V7K
2 ODD@ SATA_ARX_DTX_N1_C SATA_ARX_DTX_N1_C
4
5
3
4
<10> SATA_ARX_DTX_N1 6 5
CS14 0.01U_0402_16V7K SATA_ARX_DTX_P1_C
JUMP_43X79 7 6
+5VS ODD_DETECT# 8 7
<9> ODD_DETECT# 9 8
QS2 +5VS_ODD
10 9
10
D
6 11
S
5 4 12 11
1U_0402_6.3V6K
ODD@ 2 13 12
1 +5VS_ODD 13
1 14
CS15 SI3456BDV-T1-E3 1N TSOP6 15 14
G
16 15
3
+19VB 2 ODD@ ODD_DA# 17 16

<9> ODD_DA# 18 17
ODD@
ODD_DA# .1U_0402_16V7K 1 2 C229 19 18
19
2
20 22
RS6 ODD_DETECT# .1U_0402_16V7K 1 2 C228 20 GND2
470K_0402_5%
ODD@ ODD@ AECS_51519-02001-001
DC021409120 CONN@
1
ODD_EN
1
D 1
2 QS3 CS16
<9> ODD_EN# G 2N7002KW_SOT323-3 0.1U_0603_50V_X7R
4 ODD@ 4
S 2 +5VS_ODD
3
ODD@
1000P_0402_50V7K
0.1U_0402_25V6K
10U_0805_10V6K
1 1 1
CS10
CS11
CS12
ODD@ 2 ODD@ 2 ODD@ 2

HDD
0.3
A B C D E F G H
5 4 3 2 1
Main Func = USB3.0 Port1
+5VALW
+5V_USB_PWR1
Vinafix.com 1 1 1
W=80mils 1
JUSB1
VBUS
10U_0603_6.3V6M
0.1U_0402_16V7K
LI1 EMI@ CI18 CI12 CI14 USB20_JUSB1_N6_R 2
D-
47U_0805_6.3V4Z
47U_0805_6.3V4Z
USB3RN1_JUSB1 1 2 USB3RN1_JUSB1_R USB20_JUSB1_P6_R 3
<10> USB3RN1_JUSB1 4 D+
D 47U_0805_6.3V4Z 4.7U_0805_10V4Z 0.1U_0402_16V7K 1 1 1 1 D
2 2 2 USB3RN1_JUSB1_R 5 PGND
SSRX-
CI5
CI1
CI40
CI2
USB3RP1_JUSB1 4 3 USB3RP1_JUSB1_R USB3RP1_JUSB1_R 6 10
<10> USB3RP1_JUSB1 7 SSRX+ GND 11
S COM FI_ CHILISIN CMMI21T-670Y-N 2 2 2 2 USB3TN1_JUSB1_R 8 GND GND 12
SSTX- GND
3
USB3TP1_JUSB1_R 9 13
SSTX+ GND
DI2 SUYIN_020053GR009M221ZL
+5V_USB_PWR1 CONN@
+5VALW L30ESDL5V0C3-2_SOT23-3
UI5 80mil
1 ESD@
5 OUT 2014/08/11 Modify
IN 2
1
USB_EN# 4 GND
<25,27> USB_EN# EN 3 USB_OC0#
OCB USB_OC0# <9>
LI3 EMI@ 1
USB3TN1_JUSB1 2 1 USB3TN1_JUSB1_C 1 2 USB3TN1_JUSB1_R SY6288D20AAC_SOT23-5 1
<10> USB3TN1_JUSB1
CI3 0.1U_0402_10V7K CI13 SA00007AO00
0.1U_0402_16V7K
CI15
0.1U_0402_16V7K
USB3TP1_JUSB1 2 1 USB3TP1_JUSB1_C 4 3 USB3TP1_JUSB1_R 2
<10> USB3TP1_JUSB1 2
CI4 0.1U_0402_10V7K
S COM FI_ CHILISIN CMMI21T-670Y-N
ESD@
DI1
USB3RN1_JUSB1_R 1 10 USB3RN1_JUSB1_R
USB3RP1_JUSB1_R 2 9 USB3RP1_JUSB1_R
EMI@
LI2 USB20_JUSB1_N6 USB3TN1_JUSB1_R 4 7 USB3TN1_JUSB1_R
USB20_JUSB1_P6 1 2 USB20_JUSB1_P6_R
<10> USB20_JUSB1_P6 1 2
1
USB3TP1_JUSB1_R 5 6 USB3TP1_JUSB1_R
C R811 C
USB20_JUSB1_N6 4 3 USB20_JUSB1_N6_R @ 300_0402_5% 3
<10> USB20_JUSB1_N6 4 3
WCM-2012HS-900T_4P 8 USB connector1
2
1
@
C168
15P_0402_50V8J
IP4292CZ10-TBR_XSON10_2.5X1~D
USB20 port0
2 USB30 port1
AMD request 5/16
B B
A A

USB3.0
0.3
5 4 3 2 1
5 4 3 2 1
+VDDD +VBUS
Main Func = Touch Pad
+3VS R153 +TPUSB_VCC
+3VS_TOUCH
0.1U_0402_16V4Z
C665 TPUSB@
4.7U_0603_6.3V6K
C828 TPUSB@
0.1U_0402_16V4Z
C666 TPUSB@
4.7U_0603_6.3V6K
C831 TPUSB@
R146 U69 TPUSB@ 0_0402_5% 2 2 2 2
2
0_0402_5% 1 24 +VDDD 1 @ 2
Touch pad SCB_0/GPIO_6 VDDD
G
TP_CLK 4.7K_0402_5% 1 2 R18 +VDDD_M_M 1 @ 2 +VDDD_M 2 23
TP_DATA 4.7K_0402_5% 1 2 R19 3 SCB_5/GPIO_7 SCB_4/GPIO_5 22 TP_I2C_DAT
TP_I2C_INT#_D 3 1 TP_I2C_INT# TP_I2C_INT#_D 4 VSSD SCB_3/GPIO_4 21 TP_I2C_CLK 1 1 1 1
5 GPIO_8 SCB_2/GPIO_3 20 TPUSB_X2
D
+3VS_TOUCH TPUSB@ Q87 2N7002K_SOT23-3 @ C668 1 2 .1U_0402_16V7K 6 GPIO_9 SCB_1/GPIO_2 19 TPUSB_X1
R126 1 @ 2 0_0402_5% 2 1 +VDDD_M_M 7 GPIO_10 GPIO_1 18 1 @ 2
@ C836 4.7U_0603_6.3V6K 8 GPIO_11 GPIO_0 17 R148 +5VS
JTP Vinafix.com RP20

+3VS_TOUCH
+3VS_TOUCH
1 <10> USB20_P3
9
10
SUSPEND
WAKEUP
USBDP
VSSA
VSSD
VBUS
16
15
0_0402_5%
+VBUS 2 1
0.1U_0402_16V4Z
C667 @
1 I2C_DAT 1 8 11 14 R138 @
1 <10> USB20_N3 USBDM nXRES
2
I2C1_SDA_TP_R 2 I2C_CLK 2 7 12 13 0_0603_5%
I2C1_SCL_TP_R 3 2 TP_I2C_INT# 3 6 +VDDD_M 1 @ 2 VCCD VSSD 25 T26 2 1
G
D 3 2 thermal pad +TPUSB_VCC D
4 4 5 R139 R149 TPUSB@
TP_I2C_INT# 5 4 1 3 TP_I2C_INT# 0_0402_5% CY7C65211-24LTXI_QFN24_4X4 0_0603_5%
6 5 <9> TP_I2C_INT#_APU 1 2
PTP_DIS# 2.2K_0804_8P4R_5% CZ_I2C@ @
S
<27> PTP_DIS# 6 +TPUSB_VCC
TP_DATA 7 Q92 2N7002K_SOT23-3 R147 1
<27> TP_DATA 8 7 +3VS
TP_CLK R150 1 @ 2 0_0402_5% 0_0402_5%
<27> TP_CLK 9 8 +TPUSB_VCC_IN +3VALW
RP24 C43 TPUSB@
10 GND TP_I2C_CLK 1 8 1U_0402_6.3V6K +TPUSB_VCC_IN 2 1
GND 2 +TPUSB_VCC
TP_I2C_DAT 2 7 R152 TPUSB@ 0_0603_5%
EC_TP_INT# 1 @ 2 TP_I2C_INT# JXT_FP202DH-008M10M TP_I2C_INT#_D 3 6 2 @ 1
<27> EC_TP_INT# 4 5
RE338 0_0402_5% CONN@ TPUSB_X1 R151 0_0603_5%
Y9 @
2.2K_0804_8P4R_5% 4 1 +3VS
TPUSB@ 2 1
R160 0_0603_5% +TPUSB_VCC
@ C41 TPUSB@
1 R940 2 TPUSB_X2 3 2 1U_0402_6.3V6K UL4
TP_CLK 1M_0402_5% 2 1 +TPUSB_VCC_IN 5 1
IN OUT
33P_0402_50V8J
C62
33P_0402_50V8J
C73
TP_DATA 12MHZ_18PF_7V12000001
1
+TPUSB_VCC_IN
10K_0402_5%
R452
2
NEMI@ C553
NEMI@ C551
Part Number = SJ10000C210 @
100P_0402_50V8J
100P_0402_50V8J
1 1 GND R44
@ @ PCB Footprint = Y_CRG3201212_4P
@ TP_I2C_EN 4 3 2 1
<27> TP_I2C_EN
2
EN OC 10K_0402_5%
2
2 2 AP22802AW5-7 SOT25 5P @
R30 @
100K_0402_5%
@
1
RE330
1 @ 2
From APU +3VALW
0_0603_1%
+V_TP +3VS
TPUSB@
2
VDD_18_S0 CZ_I2C@ RE331 0_0603_5% TP I2C to bridge & EC
RE336 1 2 0_0402_5% I2C1_SDA_TP_R 1 2
G
<9> I2C_DAT_TP +3VS
RE337 1 2 0_0402_5% I2C1_SCL_TP_R TP_I2C_CLK 1 6 I2C_CLK
<9> I2C_CLK_TP <27> TP_I2C_CLK
D
@ Q2505B
C CZ_I2C@ DMN66D0LDW-7_SOT363-6 C
5
+V_TP +3VS_TOUCH VDD_33 Q2505A TPUSB@ VDD_33_S5
G
+3VS_TOUCH TP_I2C_DAT 4 3 I2C_DAT
<27> TP_I2C_DAT
D
U78 R122 1 @ 2 0_0402_5%
1 R123 1 @ 2 0_0402_5%
5 1
CE58 IN OUT 2
1U_0402_6.3V6K~D 4 GND 3
2 <27> TP_EN EN FLG TP SMBus to CPU
1 2 APU_SCLK1 R135 1 @ 2 0_0402_5% I2C_CLK
<9> APU_SCLK1
C1280 C523 VDD_33_S5 APU_SDATA1 R136 1 @ 2 0_0402_5% I2C_DAT
<9> APU_SDATA1
1U_0402_6.3V6K AP22802AW5-7 SOT25 5P 4.7U_0603_6.3V6K CZ Only
@
2 1 USB20_P3 R140 1 @ 2 0_0402_5% USB20_P3_R
USB20_N3 R141 1 @ 2 0_0402_5% USB20_N3_R
+3VS_TOUCH +3VS_TOUCH
USB20_P3_R R143 1 @ 2 0_0402_5% I2C1_SDA_TP_R
USB20_N3_R R142 1 @ 2 0_0402_5% I2C1_SCL_TP_R
1
RE341 RE340 I2C_DAT R144 1 TP_I2C@2 0_0402_5% I2C1_SDA_TP_R

10K_0402_5% I2C_CLK R145 1 TP_I2C@2 0_0402_5% I2C1_SCL_TP_R
PTP@ 10K_0402_5%
2
PTP_DIS# EC_TP_INT#
CZ: CZ_I2C@+TP_I2C@+PTP@
INT_KBD Connector CZ-L: TPUSB@+TP_I2C@+PTP@
+FAN_POWER
Main: SP01001H600 (CIS ok)
40mil
* Key Board Back Light
B
FAN Control circuit +5VS
RE60 JKB CONN@
B
2.2U_0603_6.3V6K
1 @ 2 30 32 +5VS FE1 @ +5VS_KBL

1000P_0402_50V7K
1 1 30 GND 31
KSI7 29
CE29 CE28 240_0402_1% KSI6 28 29 GND 0.75A_24V_1812L075-24DR~OK
+5VS KSI4 27 28
2 2 CE27 KSI2 26 27 2 1
26
10U_0603_6.3V6M
2.2U_0603_6.3V6K KSI5 25 20mil
25
1U_0603_10V6K
1 2 KSI[0..7] KSI1 24 1 2
<27> KSI[0..7] 23 24
KSI3 1 RE59 1
23
CE56
KSO[0..16] KSI0 22 0_0805_5%
<27> KSO[0..16] 22
CE57
UE6 KSO5 21 KBBL@ KBBL@
21 KBBL@
1 8 KSO4 20
2 VEN GND 7 KSO7 19 20 2 2
3 VIN GND 6 KSO6 18 19
EN_DFAN1 4 VO GND 5 KSO8 17 18
<27> EN_DFAN1 VSET GND 17
KSO3 16
NCT3942S SOP 8P KSO1 15 16
KSO2 14 15
KSO0 13 14 +3VS
+5VS KSO12 12 13
+3VS KSO16 11 12 @
KSO15 10 11
10
RE68 Main: SP01001UE00 (CIS ok)
2
240_0402_1%
KSO13 9 1 2
9 <9> KB_DET#
1
+FAN_POWER
RE73
KSO14 8
RE72 KSO9 7 8 10K_0402_5% +5VS_KBL
10K_0402_5% R29 KSO11 6 7
0_0402_5% KSO10 5 6 JKBBL CONN@
1
1
JFAN CONN@ 1 2 KB_CAPS_PWR 4 D 1
40mil <27> CAPS_LED
2
1 @ 3 4 2 KB_DET 2 1
2 1 2 3 G 3 2 5
<27> FAN_SPEED1 3 2 1 2 1 2 4 3 G1 6
@ CAPS_LED_R QE4 S KB_BL_PWM
<27> CAPS_LED
3
3 1 4 G2
1
2N7002KW 1N SOT323-3
2
4 R27 ACES_51510-0304N-P01 KBBL@ RE58 ACES_50524-00401-P01

1
5 GND1 0_0402_5% R28 SP01001H600 100K_0402_5%
20mil SP01001UE00
CE26 GND2 @ 0_0402_5% KBBL@
A
0.01U_0402_16V7K A
1
2
5
6
2 ACES_50224-0030N-001
1
DC021408184 D QE5
G AP2606AGY-HF 1N SOT26-6
3
<27> KB_LED_PWM S KBBL@
4
FAN / TP / PWR SW / KBBL
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = IO Connector

+5VALW
+5V_USB_PWR2
CI44
1 1
CI45 IO to MB CONN
Vinafix.com
4.7U_0805_10V4Z 0.1U_0402_16V7K 80mil CI48
1
+
D 2 2
150U_B15G_6.3VM_R70M
@ Main: SP010022O00 (CIS ok) D
+5V_USB_PWR2
+5VALW JIO1 CONN@
UI7 80mil 24 26
1 23 24 GND 25
5 OUT USB20_JUSB2_N1_R 22 23 GND
IN 2 USB20_JUSB2_P1_R 21 22
USB_EN# 4 GND 20 21
<23,27> USB_EN# EN 3 19 20
USB_OC1# USB20_JUSB3_P2_R
OCB USB_OC1# <9> 18 19
1 USB20_JUSB3_N2_R
CI46 SY6288D20AAC_SOT23-5 17 18
1 17
SA00007AO00 CI47 RI1 2 @ 1 0_0402_5% 16
0.1U_0402_16V7K 15 16
2 +5V_USB_PWR2 15
0.1U_0402_16V7K 14
2 13 14
12 13
11 12
RI2 2 @ 1 0_0402_5% 10 11
9 10
AUD_HP_OUT_L_CN 8 9
AUD_HP_OUT_R_CN 7 8
C 7 C
SLEEVE_R 6
5 6
RING2_R 4 5
3 4
JACK_SENSE# 2 3
WCM-2012HS-900T_4P 1 2
4 3 USB20_JUSB2_P1_R 1
<10> USB20_JUSB2_P1 4 3 ACES_51524-0240N-001
SP010022O00
1 2 USB20_JUSB2_N1_R
<10> USB20_JUSB2_N1 1 2
LI7
2
EMI@
DI3
L30ESDL5V0C3-2_SOT23-3
ESD@
1
B B
EMI@
LI8 RING2_R
<18> RING2_R
1 2 USB20_JUSB3_P2_R
<10> USB20_JUSB3_P2 1 2
<18> JACK_SENSE# JACK_SENSE#

4 3 USB20_JUSB3_N2_R
<10> USB20_JUSB3_N2 4 3
WCM-2012HS-900T_4P AUD_HP_OUT_L_CN
<18> AUD_HP_OUT_L_CN
2
AUD_HP_OUT_R_CN
<18> AUD_HP_OUT_R_CN
DI4 <18> SLEEVE_R SLEEVE_R
L30ESDL5V0C3-2_SOT23-3
ESD@
AUDIO Jack
1
A A

IO-DB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 0.3
5 4 3 2 1
A B C D E
Main Func = DC Interface

+5VS and +3VS switch +3VS to +3VGS
+1.8V_ALW to +1.8VS
SHORT 2000mA
Vinafix.com J509 @
Max:7.0A U15 J11
2 1 +0.95VALW
1 14 0.95VSDGPU_OUT 1 2 +0.95VSDGPU
+5VALW 2 1 +5VS 2 VIN1 VOUT1 13 1 2
1 VIN1 VOUT1 1
JUMP_43X118 DIS@ C343 JUMP_43X118
PXS_PWREN R438 1 2 47K_0402_5% 0.95VSDGPU_ON 3 12 2 1 330P_0402_50V7K
<9,51,52,53> PXS_PWREN ON1 CT1
U2301 J510 DIS@
1 14 5VS 2 1 DIS@ 1 2 +5VALW
4 11
2 VIN1 VOUT1 13 2 1 C983 0.22U_0402_10V6K VBIAS GND
VIN1 VOUT1 +1.8VS
C2307
10U_0805_10V4Z
C2308
10U_0603_6.3V6M
R2313 JUMP_43X79 SUSP# R437 1 2 1K_0402_5% +0.95VALW_ON 5 10 2 1
SUSP# 1 @ 2 5VS_GATE 3 12 1 2 @ ON2 CT2 330P_0402_50V7K J10
ON1 CT1 1 1
0_0402_5% C5216 470P_0402_50V7K 1 2 +1.8V_ALW
6 9 +1.8VS_LS
C349 1 2
4 11 C987 0.1U_0402_16V7K 1 2 7 VIN2 VOUT2 8 1 2
VBIAS GND VIN2 VOUT2 2
R2318 C5217 @ C24 @ JUMP_43X79 @
1 @ 2 3VS_GATE 5 10 1 2 1000P_0402_50V7K 2 2 1U_0402_6.3V6K 15 C26
10mil ON2 CT2 GPAD .1U_0402_16V7K
0_0402_5% 6
VIN2 VOUT2
9 3VS EM5209VF DFN 14P DUAL LOAD SW 1500mA 1
1
C2322 C2309 +3VALW 7 8 SA00007PM00

VIN2 VOUT2
0.01U_0603_25V7K
0.01U_0603_25V7K
15 +3VS
2
GPAD
EM5209VF DFN 14P DUAL LOAD SW J511 For Test,
SA00007PM00 2
2 1
1 Max:5.07A APE8937(SA000070L00)
AOZ1336(SA00006U600)
+3VS
@ JP2
+3VGS
C2324
10U_0603_6.3V6M
C2323
10U_0603_6.3V6M
JUMP_43X118 TPS22967(SA000070S00) 2 1
+3VALW +5VALW @ 2 1
1 1
JUMP_43X39
@ U74 DIS@
2 2
5 1
100mil(1.5A)
+5VALW +5VALW IN OUT
C2316
10U_0603_6.3V6M
C2318
10U_0603_6.3V6M
C2306
10U_0603_6.3V6M
C2305
10U_0603_6.3V6M
2
PXS_PWREN 4 GND 3
1 1 1 1
SHORT EN FLG
2
2 2
RZ10 RZ19 C620 C621
2 2 2 2 100K_0402_5% 100K_0402_5% 4.7U_0603_6.3V6K AP22802AW5-7 SOT25 5P 4.7U_0603_6.3V6K
DIS@ DIS@
1 1
1
2 SUSP SYSON# 2
3
Q52A Q52B
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
+1.8V_ALW +1.8VGS
SUSP# 2 5
<27,44,45> SUSP# SYSON <27,44>
1
1
4
+0.95VALW U4 +0.95VS U75 @
AO4354_SO8 RZ591 100K_0402_5%
8 1 RZ21 5 1
20mil(0.5A)
10K_0402_5%
7 2 IN OUT 2
1
2
+0.95VS GND
4.7U_0603_6.3V6K
C939
1U_0402_6.3V6K
C46
C940 6 3 1 1 PXS_PWREN 4 3
4.7U_0603_6.3V6K 5 EN FLG
2 2
2 C623 C622
4
2 @2 1 4.7U_0603_6.3V6K AP22802AW5-7 SOT25 5P 4.7U_0603_6.3V6K

R1671 @ @ @
470_0603_5% 1 1
+5VALW
1 2
1 2 0.95VS_GATE
R1674 +5VALW
1
4.7K_0402_5% C16 D Q83 @
1
.1U_0402_16V7K 0.95VS_PWR_EN# 2 2N7002K_SOT23-3

D G
2 2 S +APU_CORE_NB
<27> 0.95VS_PWR_EN#
2
G
3
S Q84 R53
2N7002K_SOT23-3 +5VALW CZ@ 1K_0402_5%
3
8
U2A CZ@
3 LM393DR_SO8
1
+
2
1 CORE_NB_GATE_BUFF
+3VALW R2635 +0.775VALW +0.775MOS 2 O
-
G
100K_0402_5% CZ@ +5VALW
4
2
6
1
2
D
3 R2634 CZ@
G
3
100K_0402_5% CZ@ Q2516B S
2
1
3
Q135 CZ@ Q2513 CZ@ +0.775MOS R54
1
+APU_CORE_NB AO3416L_SOT23-3 AO3416L_SOT23-3 +VDDCR_FCH_ALW S5_MUX_CTRL 5 G
D
CZ@ 1K_0402_5%
8
Q2516A S CZ@ U2B CZ@
1 3 3 1 5
S
DMN66D0LDW-7_SOT363-6 R2636 LM393DR_SO8

D
P
4
1
CZ@ 100K_0402_5% + 7 0.775VALW_GATE_BUFF
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1 1 1 O
1
6
CZ@ C2621
CZ@ C2620
C2618
-
G
CZ@ C432
CZ@ C431
4.7U_0603_6.3V6K
G
G
2
1
CZ@ CORE_NB_GATE
2
4
2 2 2
Q2515 CZ@ Q2514 CZ@

+0.775VALW AO3416L_SOT23-3 AO3416L_SOT23-3
CORE_NB_GATE_BUFF R1271 CZ@ 2 0_0402_5%CORE_NB_GATE
1 3 3 1 +5VALW 1 CZ@ 2
S
0.775VALW_GATE_BUFF 0.775VALW_GATE
D
1 1 R128 0_0402_5%
C2619 C2622 CZ@ +5VALW
2
4.7U_0603_6.3V6K 4.7U_0603_6.3V6K @
G
G
2
CZ@ 0.775VALW_GATE R918 CORE_NB_GATE_CC R1291 @ 2 0_0402_5%
2
2 2 @ 0.775VALW_GATE_CC 1 @ 2
+3VALW R917 100K_0402_5% R130 0_0402_5%
1
100K_0402_5% CORE_NB_GATE_CC
1
2
6
@ @
1
2
D
R916 G Q2507B
S
DMN66D0LDW-7_SOT363-6 D
100K_0402_5% 2
1
0.775VALW_GATE_CC G @
3
@ S Q93
5
D
S5_MUX_CTRL G 2N7002K_SOT23-3
<9> S5_MUX_CTRL
3
Q2507A S
4
VGATE
<9,27,48,49> VGATE
4 4

DC/DC Interface
0.3
A B C D E
5 4 3 2 1
Main Func = KBC +RTC_APU_R
RE22 CZ@ RE22 VG_EVT@

Board ID
1
D Q91 +3VALW
RTC_DIS 2 2N7002K_SOT23-3
G
2
Project ID S
33K_0402_1% 130K_0402_1% RE20
3
+3VALW R1563 100K_0402_1%
+EC_VCCA
Ra
100K_0402_5% SD034330280 SD034130380
+3VALW +3VALW_EC LE3
Vinafix.com
1
2
FBMA-L11-160808-800LMT_0603 RE22 CZL@ AD_BID0
RE23 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K +3VALW_EC 1 2 +EC_VCCA
2
Rc 100K_0402_1% RE13 0_0805_5% 1 1 1 1 2 2 1 @ 1
+3VLP CE17 CE3 CE4 CE14 CE13 CE10@ 0.1U_0402_16V7K RE22 CE39
D 1 @ @ CE21 Rb 0_0402_1% D
PID0 1 2 1000P_0402_50V7K
RE4 0_0805_5% 2 2 2 2 1 1 2 ECAGND 43K_0402_1% 2
1
ECAGND <41>
2
@ 1 0.1U_0402_16V7K 0.1U_0402_16V7K 1000P_0402_50V7K 0.1U_0402_16V7K

RE24 CE47 SD034430280
Rd 0_0402_1% 1 @ 2 +3VLP
RE14 0_0402_5% Analog Board ID definition,
2
1
Please see page 4.
111
125
0.1U_0402_16V7K Reserved for KB9012
22
33
96
67
9
UE1
2014/09/09 Modify 1 @ 2
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
+5VS +V_EC
RE26 0_0402_5%
TS_RST#_EC <16>
0_0402_5%
RD15 2 1 SATA_LED#_R 1 2
SATA_LED#_R <29> +3VS
GATEA20 1 21 @ RE25 @ 0_0402_5%
<9> GATEA20 2 GATEA20/GPIO00 GPIO0F 23
KB_RST# BEEP#
<9> KB_RST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# <18> 2 1
SERIRQ SATA_ACT#_RR @ SATA_ACT# SATA_ACT# <10,29>
<10> SERIRQ LPC_FRAME# 4 SERIRQ GPIO12 27 ACOFF RD19 0_0402_5% +V_EC
+3VALW <9,10> LPC_FRAME# 5 LPC_FRAME# ACOFF/GPIO13 ACOFF <42> 2 1
CE24 LPC_AD3 ECAGND
<10> LPC_AD3 7 LPC_AD3
NEMI@ 22P_0402_50V8J NEMI@ LPC_AD2 PWM Output CE43 100P_0402_50V8J
2 1 <10> LPC_AD2 LPC_AD2
RE16 2 1 33_0402_5% LPC_AD1 8 63 BATT_TEMP TP_CLK 2 @ 1
1 2 <10> LPC_AD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_TEMP <41,42>
KSO1 LPC_AD0 LPC & MISC 4.7K_0402_5% RE28
<10> LPC_AD0 LPC_AD0 GPIO39 65 VCIN1_BATT_DROP <41> 2 1
RE62 @ 47K_0402_5% ADP_I TP_DATA @
12 ADP_I/GPIO3A 66 ADP_I <41,42>
AD Input AD_BID0 4.7K_0402_5% RE27
1 2 <9,10> LPC_CLK0_EC 13 CLK_PCI_EC GPIO3B 75
KSO2 BATT_I
<9,19,20> PLT_RST# PCIRST#/GPIO05 GPIO42 BATT_I <42>
RE63 @ 47K_0402_5% +3VALW RE17 2 9012@ 1 47K_0402_5% EC_RST# 37 76 PANEL_BKLEN
20 EC_RST# IMON/GPIO43 PANEL_BKLEN <8>
EC_SCI# +5VALW
1 2 2 1 <9> EC_SCI# 38 EC_SCII#/GPIO0E
LID_SW# CE23 0.1U_0402_16V7K PTP_DIS#_R
RE75 10K_0402_5% GPIO1D 68 GPU_AC_LIGHT
DAC_BRIG/GPIO3C 70 EN_DFAN1 USB_EN# RE504 1 2 10K_0402_5%
1 2 EN_DFAN1/GPIO3D 71 EN_DFAN1 <24>
WLAN_WAKE# no support "Power on by lid" DA Output EC_ENVDD
55 IREF/GPIO3E 72 EC_ENVDD <16>
RE70 10K_0402_5% KSI0
2 1 PTP_DIS#_R 56 KSI0/GPIO30 CHGVADJ/GPIO3F LCD_TEST <16>
PTP_DIS# @ KSI1
1 2 <24> PTP_DIS# 57 KSI1/GPIO31
@ EC_SMI# RE15 0_0402_5% KSI2 CE40 100P_0402_50V8J
RE19 1K_0402_1% KSI3 58 KSI2/GPIO32 83 EC_MUTE# ACIN 2 1
59 KSI3/GPIO33 EC_MUTE#/GPIO4A 84 EC_MUTE# <18>
KSI4 USB_EN#
1 2 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 USB_EN# <23,25>
EC_PME# KSI5 EC_I2C_TPCLK R124 1 @ 2 0_0402_5%
KSI[0..7] 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 TP_I2C_CLK <24>
C RE21 10K_0402_5% KSI6 PS2 Interface EC_I2C_TPDAT R125 1 @ 2 0_0402_5% C
<24> KSI[0..7] 62 KSI6/GPIO36 EAPD/GPIO4D 87 TP_I2C_DAT <24>
KSI7 TP_CLK
1 KSO[0..16] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <24>
9022@2 EC_SCI# KSO0 39 88 TP_DATA
<24> KSO[0..16] 40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <24>
RE61 10K_0402_5% KSO1
KSO2 41 KSO1/GPIO21 0_0402_5% EC_LID_OUT# 1 2 EMI@
KSO3 42 KSO2/GPIO22 97 PID0 RD16 2 1 CE42 1000P_0402_50V7K
KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 WOL_EN @
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 WOL_EN <19> WOL_EN (Hi Active) 1 2 EMI@
PM_SLP_S5# PM_SLP_S3# KSO5 0.95VS_PWR_EN# EC_RSMRST#
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 0.95VS_PWR_EN# <26>
+3VS CE41 1000P_0402_50V7K
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH <41>
1 NEMI@ 1 NEMI@ KSO7/GPIO27 SPI Device Interface
CE33 CE25 KSO8 47 Reserve for ESD
KSO8/GPIO28
5
KSO9 48 119 U5 CE26, CE27 please close to UE1
+3VALW 49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SPI_MISO <10> 2
KSO10 PANEL_BKLEN
P
+3VS 2 2 50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SPI_MOSI <10> B 4
KSO11 SPI Flash ROM
51 KSO11/GPIO2B SPICLK/GPIO58 128 EC_SPI_CLK <10> 1 Y DISPOFF# <16>
RPE1 0.1U_0402_16V7K 0.1U_0402_16V7K KSO12 BKOFF#
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS1# <10> A
G
1 8 EC_SMB_CK1_R KSO13 52 For share ROM reserve
2 7 EC_SMB_DA1_R KSO14 53 KSO13/GPIO2D @ MC74VHC1G08DFT2G_SC70-5
3
3 6 EC_SMB_CK2_R KSO15 54 KSO14/GPIO2E 73 ERP_LOT6 EC_RSMRST# 1 2
ESD Request at SSI KSO15/GPIO2F ENBKL/GPIO40 ERP_LOT6 <41>
@
4 5 EC_SMB_DA2_R KSO16 81 74 VGATE 4.7K_0402_5% RE48
KSO16/GPIO48 PECI_KB930/GPIO41 VGATE <9,26,48,49>
TP_EN 82 89 DBC_EN
<24> TP_EN KSO17/GPIO49 FSTCHG/GPIO50 90 DBC_EN <16>
2.2K_0804_8P4R_5% WLAN_WAKE# 0.95_1.8VALW_PWREN1 @ 2
BATT_CHG_LED#/GPIO52 91 WLAN_WAKE# <20>
CAPS_LED 4.7K_0402_5% RE46
1 2RE31 77 CAPS_LED#/GPIO53 92 CAPS_LED <24>
EC_SMB_CK1 0_0402_5% @ EC_SMB_CK1_R GPIO PWR_PWM_LED#
+3VS <41,42> EC_SMB_CK1 1 2RE33 78 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 PWR_PWM_LED# <29>
CHARGER <41,42> EC_SMB_DA1 0_0402_5% @ EC_SMB_DA1_R BATT_LOW_LED#
EC_SMB_DA1 1 2RE42 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_LOW_LED# <29>
EC_SMB_CK2 0_0402_5% @ EC_SMB_CK2_R SM Bus SYSON
<8,28,31,34> EC_SMB_CK2 1 2RE35 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 SYSON <26,44>
APU, GPU, Thermal<8,28,31,34> EC_SMB_DA2 0_0402_5% @ EC_SMB_DA2_R VR_ON
1 2 EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 VR_ON <48,49>
@ EC_SCI# 0.95_1.8VALW_PWREN
RE32 10K_0402_5% PM_SLP_S4#/GPIO59 0.95_1.8VALW_PWREN <46,47> 3.3V
1
0_0402_5% @ 2RE53 PM_SLP_S3#_R 6 100 EC_RSMRST#
<9> PM_SLP_S3# 1 2RE54 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 1 2 EC_RSMRST# <9>
0_0402_5% @ PM_SLP_S5#_R EC_LID_OUT#_R @
<9> PM_SLP_S5# 1 2RE55 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 EC_LID_OUT# <9>
0_0402_5% @ EC_SMI#_R VCIN1_PH 0_0402_5% RE71
<9> EC_SMI# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 VCIN1_PH <41>
VCOUT1_PH
<41> PS_ID 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 2 1 VCOUT1_PH <41>
0.775PW_EN VCOUT0 @
<50> 0.775PW_EN 18 GPIO0B VCOUT0_PH/GPXIOA07 105 VCOUT0_PH# <28,43>
DEL GPIO0B(CE_EN) GPO BKOFF# RE39 0_0402_5%
<53> DGPU_PWROK 19 GPIO0C BKOFF#/GPXIOA08 106 BKOFF# <16>
Change Pin19 from ODD_DA# to TS_EN for Touch function TS_EN GPIO EC_TP_INT#
<16> TS_EN 25 GPIO0D PBTN_OUT#/GPXIOA09 107 EC_TP_INT# <24>
KB_LED_PWM AD_I_HW2 Delay SUSP# 10ms
<24> KB_LED_PWM 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 AD_I_HW2 <41>
B FAN_SPEED1 APU_PWRGD_EC GPU_AC_LIGHT 1 @ 2 B
1 <24>
2 FAN_SPEED1 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 APU_PWRGD_EC <8> ACIN_65W <34>
@ EC_PME# 1.8VS RE80 0_0402_5%
<9,19> APU_PCIE_WAKE# 0_0402_5% RE56 EC_TX 30 EC_PME#/GPIO15
<20> EC_TX 31 EC_TX/GPIO16 110
EC_RX ACIN
<20> EC_RX 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 ACIN <34,41,42>
APU_FCH_POK EC_ON
<9> APU_FCH_POK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <43>
<43> POK 34
36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
114
115
ON/OFF
ON/OFF <29>
RTC_DIS GPI LID_SW# D4
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 LID_SW# <29>
SUSP#
SUSP#/GPXIOD05 117 SUSP# <26,44,45> 1 2 +3VLP
AD_I_HW1 LID_SW# TS_EN_R
GPXIOD06 118 AD_I_HW1 <41> TS_EN_R <16>
APU_RST#_EC 1.8VS
122 PECI_KB9012/GPXIOD07 APU_RST#_EC <8>
AGND/AGND
PBTN_OUT#
<9> PBTN_OUT# XCLKI/GPIO5D
1
TP_I2C_EN 123 124 +V18R 2 1
GND/GND
GND/GND
GND/GND
GND/GND
<24>TP_I2C_EN XCLKO/GPIO5E V18R +1.8V_ALW RB751V-40-H-GP

RE69 @ 0_0402_5% RE30
GND0
@ 47K_0402_5%
2 @ 1
+3VALW_EC
RE64 0_0402_5%
2
9012@ KB9012QF A3 LQFP 128P_14X14
11
24
35
94
113
69
20mil 1 VCIN1_PH
LE4 CE44
ECAGND 2 1 9012@ reserve for KB9012 Rev.A2
FBMA-L11-160808-800LMT_0603 4.7U_0805_10V4Z
2
RE65 UE1 9022@

VCOUT1_PH 2 @ 1
0_0402_5% 1 @ 2 H_PROCHOT# <8,9,41,42,48,49>

+3VS
0.1U_0402_10V7K
R1690
1
KB9022QD LQFP 128P 0_0402_5%
1 D Q89 9012@
CE45
SA000075S30 VCOUT1_PH 2 2N7002K_SOT23-3

1
9012@ G
S
RE66 @ 2
A A
FAN_SPEED1 0_0402_1% 3
5
2
@ 1 UE3
P
CE37 H_PROCHOT# 4 2 VCOUT1_PH

Y A
NC
0.1U_0402_16V7K
2 SN74LVC1G06DCKR_SC70-5 RE67
1
1
9012@ 100K_0402_5%
CE46 9012@
Please close to EC 47P_0402_50V8J 9012@
1
2
SA00004AU00 Issued Date 2014/06/10 Deciphered Date 2015/06/30 Title
EC ENE-KB9012A4/KB9022QC
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = Thermal Sensor
D
Vinafix.com
Fintek thermal sensor D
placed near by TOP DDR3

+3VS +3VS
1
R2448
U2407 10K_0402_5%
@
2
1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <8,27,31,34>
REMOTE1+ 2 9 EC_SMB_DA2
DP1 SMDATA EC_SMB_DA2 <8,27,31,34>
1
C2498 REMOTE1- 3 8
0.1U_0402_10V6K DN1 ALERT#
REMOTE2+ 4 7 R2450 1 @ 2
2 DP2/DN3 THERM# VCOUT0_PH# <27,43>
0_0402_5%
REMOTE2- 5 6
DN2/DP3 GND
C C
F75303M_MSOP10
Address 1001_101xb
SA000046C00
2nd source
SA000029210-->EMC1403-2-AIZL-TR
REMOTE1,2 (+/-) :
REMOTE1+ BOTTOM DDR3
Close U2407 Trace width/space:10/10 mil
1
REMOTE1+ C
1 @ C2500 2 Q2407
Trace length:<8"
2200P_0402_25V7K B MMST3904-7-F_SOT323-3
2
C2502 E
3
2200P_0402_25V7K REMOTE1-
2 REMOTE1-
REMOTE2+
B 1
REMOTE2+ BOTTOM CPU B
C2504
1
2200P_0402_25V7K C
2 REMOTE2- @ C2505 2 Q2408
2200P_0402_25V7K 2 B MMST3904-7-F_SOT323-3
E
3
REMOTE2-
A A

Thermal Sensor
Document Number Rev
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = Power BTN

+5VALW (AMBER_LED)
Low actived from
R6105
KBC GPIO Q6101
R2
Battery LED1
3 LED1
BATT_LOW_LED# 1 2BATT_LOW_LED_R# 2 R6103 470R2J-2-GP
<27> BATT_LOW_LED# R1
1 BATT_LOW_LED 2 1 BAT_AMBER 1
D
Vinafix.com 0R2J-2-GP
DDTA144VCA-7-F-GP
R6107 2 1 390R2J-3-GP BAT_WHITE 3
D
2
+5VALW
Low actived from KBC GPIO Q6102
LTW-327ZDSKS-5A 3X1 YELLOW/WHITE
R6104 R2
3
PWR_PWM_LED# 1 2PWR_PWM_LED_R# 2
<27> PWR_PWM_LED#
0R2J-2-GP
R1
1 PWR_PWM_LED
Battery LED2
DDTA144VCA-7-F-GP +3VS
R6110 (WHITE_LED)
1 2 SATA_LED#_R
@
+3VS
10KR2J-3-GP
2
2N7002KW_SOT323-3
G
<27> SATA_LED#_R
Q6103
Q6104
@ HDLED1
APU-->EC and LED @ R2
3
+5VS
From EC
2
3 1 SATA_LED#_B 2 R6108 2N7002KW_SOT323-3
G
C <10,27> SATA_ACT# C
S
R1
1 SATA_LED 1 2 SATA_LED_R 2 1
@
@ LED-W-27-GP-U @
DDTA144VCA-7-F-GP 330R2J-3-GP SATA_ACT# 3 1 PWR_PWM_LED_R#
R6106
D
2nd = 83.00110.R70
1 2 3rd = 083.11204.0070
@ Q6105
0R2J-2-GP
For EMI Reserved
SATA HDD LED SATA_LED EC6104 1 2 SCD1U16V2KX-3GP
LOW actived from PCH GPIO @
B B
ON/OFF switch PWR/B TO M/B

TOP Side
SW1
SMT1-05-A_4P +3VLP
1 3
2 4 JPWR
1
4 6
RE49 LID_SW# 3 4 GND 5
<27> LID_SW#
6
5
ON/OFF 2 3 GND
100K_0402_5% 2
1
+3VALW 1
2
0.1U_0402_16V7K
0.1U_0402_16V7K
CONN@
Pop only before MP 1 1 JXT_FP202DH-004M10M
ON/OFF <27>
C34
C33
1
CE20 2 2
0.1U_0402_16V7K
A 2 A

Reserved Page
Document Number Rev
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = Screw Hole
ZZZ
Part Number
DA6001AL000
Description
PCB 1AO LA-C142P REV0 M/B 3
Vinafix.com @
PCB@ CLIP1
D 1 D
1
EMIST-SQ-26G_1P
@
CLIP2
1
1
EMIST-SQ-26G_1P
@
CLIP4
1
1
EMIST-SQ-26G_1P
C
Screw Hole H1
H_3P0
@ RJ45
C
1
CPU bracket
H2 H3
Upper H_3P0
@
H_3P0X3P8N
@
HDMI
H31 H32 H33
1
H_3P4 H_3P7 H_3P7
@ @ @
1
H4
H_3P0
H21 H22 H23

@ DDR RIGHT (TOP View)
1
H_3P3 H_3P3 H_3P3
@ @ @ GPU stand-off
1
APU RIGHT down

H5
(TOP View)
B H_3P0 B
@
H14
1
H_3P0
@ FAN stand-off
1
FD1 FD2 FD3 FD4 FD5 FD6

IO Conn Upper (TOP View)
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL H6
H_3P2
@
1
VRAM Left Side (TOP View)

H7 H8
H_3P2 H_4P0N
@ @
1
A A

Screw Hole
0.3
5 4 3 2 1
5 4 3 2 1
Main Func = VGA Translator
For Power consumption

Measurement +3VS_2168 +3VS_2168_DA +3VS_2168_AV +VCCK_V12 Place to
pin 25
+VDISPLAY_VCC
+3VS +3VS_2168
Vinafix.com CRT_DATA
10U_0603_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
JP15
1 2 CRT@ 1 1 CRT@ 1 1 CRT@ 1 CRT@ 1 CRT@ 1 CRT@ 1 CRT_CLK JCRT CONN@
1 2 @ @
JUMP_43X39 6
CZ1
CZ2
CZ3
CZ4
CZ5
CZ6
CZ7
CZ8
D T27 D
11
2 2 2 2 2 2 2 2 CRT_R_2 1
7 G 16
12 17
G
CRT_G_2 2 G 18
8 G 19
Place to Place to Place to Place to Place to CRT_HSYNC 13
pin 5 pin 20 pin 9 pin 24 pin 19 CRT_B_2 3
9
CRT_VSYNC 14
4
10
+3VS_2168 +3VS_2168_DA +3VS_2168 +3VS_2168_AV 15
Embedded LDO R156 R157
5
0_0603_5% 0_0603_5% C-K_80461-5K1-152

Select VCCK_V12 source from external 1.2V or embedded LDO 2 1 2 1 DC021407312
+3VS_2168 CRT@ CRT@

1 1
CZ26 CRT@ CZ24 CRT@
CRT Connector
1
10U_0603_6.3V6M 10U_0603_6.3V6M
RZ5 2 2
4.7K_0402_5%
CRT@
2
LDO_EN
LDO_EN(PIN21)
0 1
1
RZ6
4.7K_0402_5% VCCK_V12 from VCCK_V12 from
@ CRT_HSYNC
External 1.2V Embedded LDO
2
C C
CRT_VSYNC
+3VS_2168 +VDISPLAY_VCC
+3VS_2168_DA
10P_0402_50V8J
10P_0402_50V8J
1 1
CZ34
CZ33
1
1
2 2
RZ55 RZ54 CRT_EMI@
20
UZ1
5
<8,17> DP1_HPD 2.2K_0402_5% 2.2K_0402_5% CRT_EMI@

CRT@ CRT@
DVCC_33
DVCC_33
VDD_DAC_33
RZ42 2 CRT@ 1 100K_0402_5% DDI1_HPD 1

CRT Connector
2
CRT@ CZ16 HPD
CRB1.0 use 47ohm@100Mhz Bead
0.1U_0402_16V7K 2 1 DDI1_AUX_C_DN 27 6 CRT_DATA
<8> APU_HDMI_DATA_C AUX_N VGA_SDA
0.1U_0402_16V7K 2 1 DDI1_AUX_C_DP 26 4 CRT_CLK
<8> APU_HDMI_CLK_C AUX_P VGA_SCL 8
APU DP1 CZ17 HSYNC RZ47 1 CRT@ 2 36_0402_5% CRT_HSYNC
CRT@ DP1_TXP0_CRT 29 HSYNC 7 VSYNC RZ49 1 CRT@ 2 36_0402_5% CRT_VSYNC
<8> DP1_TXP0_CRT 30 LANE0P VSYNC
(2-Lane only) DP1_TXN0_CRT CRT_EMI@
<8> DP1_TXN0_CRT LANE0N 15 CRT_R 1 2 CRT_R_C LZ1 1 2 CRT_R_2
DP1_TXP1_CRT 31 RED_P RZ51 0_0402_5% SBY100505T-470Y-N_2P
<8> DP1_TXP1_CRT 32 LANE1P
DP1_TXN1_CRT CRT@ CRT_EMI@
<8> DP1_TXN1_CRT LANE1N 12 CRT_G 1 2 CRT_G_C LZ2 1 2 CRT_G_2
GREEN_P RZ52 0_0402_5% SBY100505T-470Y-N_2P
CRT@ CRT_EMI@
10 CRT_B 1 2 CRT_B_C LZ3 1 2 CRT_B_2
BLUE_P RZ53 0_0402_5% SBY100505T-470Y-N_2P
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
22 POL1_SDA CRT@
POL1_SDA
8
7
6
5
19 23 POL2_SCL 1 1 1 1 1 1 1 1 1
+VCCK_V12 VCCK_12 POL2_SCL RP62
CZ27
CZ28
CZ29
CZ18
CZ19
CZ20
CZ21
CZ22
CZ23
24 2 EC_SMB_CK2 75_0804_8P4R_1%
+3VS_2168_AV AVCC_33 SMB_SCL EC_SMB_CK2 <8,27,28,34>
3 EC_SMB_DA2 CRT@
SMB_SDA EC_SMB_DA2 <8,27,28,34> 2 2 2 2 2 2
25 CRT_EMI@ 2 2 2
RZ45
1
2
3
4
AVCC_12 CRT_EMI@ CRT_EMI@
2 CRT@ 1 28 CRT_EMI@ CRT_EMI@ CRT_EMI@ CRT_EMI@ CRT_EMI@ CRT_EMI@
B RRX 21 LDO_EN B
12K_0402_1% LDO_EN
11
13 BLUE_N 18 XTALOUT_2168 T4934
7/25 Add EMI Request
14 GREEN_N XO
16 GND_DAC 17 XTALIN_2168
RED_N XI/CKIN T4933
33
EPAD_GND
RTD2168-CG_QFN32_5X5 CRT@
Mode Configure Table(Power On Latch)

POL1_SDA(PIN22)
0 1
0 X EP MODE
POL2_SCL(PIN23)
1 ROM ONLY MODE EEPROM MODE
+3VS_2168 +3VS_2168
RTD2168 Supports three operation mode for system design.
1
@ Reserve 4.7K resistor pull high/low for mode selection

RZ1 RZ3
A 4.7K_0402_5% 4.7K_0402_5% A
CRT@
2
ROM ONLY Mode : PIN22 pull low, PIN23 pull high

1POL1_SDA
1POL2_SCL
EP Mode : PIN22 pull high, PIN23 pull low

EEPROM Mode : PIN22 pull high, PIN23 pull high
@
RZ2 RZ4
4.7K_0402_5% 4.7K_0402_5%
CRT@
VGA Translator-IT6513
2
0.3
5 4 3 2 1
5 4 3 2 1
2014/09/13 Boot Enter S3 S3 Resume Shut Down

ACIN
EC Pin 110 Intput
EC_ON
EC Pin 112 Output
Vinafix.com
+5VALW 6.645ms
6.769ms
AC Plug +3VALW
D D
7.541ms
POK
EC Pin 34 Input
0.95_1.8VALW_PWREN
EC Pin 127 Output 71.34ms
+1.8V_ALW 72.20ms
0.95VALW 72.20ms
72.20ms
0.95VALW_POK
EC Pin 114 Intput ON/OFF

42.71ms rising time:37.46ns
EC Pin 100 Output EC_RSMRST#
16.16ms
RTC_CLK
95.60ms
EC Pin 122 Output PBTN_OUT#
EC Pin 14 Intput SLP_S5# 217.6ms
EC Pin 6 Intput SLP_S3# 214.8ms
EC Pin 7 Output SYSON 194ms

C C
477.9 us
+1.35V 1.198ms
33.02ms
EC Pin 116 Output SUSP# 20.72 ms
EC Pin 99 Output 0.95VS_PWR_EN#

704.2µs 597.3us 573.5us 409.1us
+5VS
1.082ms 3.149ms 943.7us 3.216ms
+3VS
721.4µs 1.248ms 895.5us

+1.8VS 1.576ms
778.8µs
+1.5VS 4.505ms 856.6us 4.965ms
292.8µs 287.2us 400us

242.9us
+0.95VS
2.636µs 942.8µs 804.5us
704.2µs
0.675VS
118.0 ms 116ms 116ms

EC Pin 121 Output VR_ON
116ms
934.0us 157.9us 797.6us 89.29us

+APU_CORE
935.9us 321us 924.9us
+APU_CORE_NB 927.4us
B 1.276 ms B
-40us 1.202ms -12.2us
EC Pin 74 Intput VGATE
BC9 128.5 ms rising time:31.49ns 116.4ms
117.6ms 116ms
(APU Intput) EC Pin 32 Output APU_FCH_POK
107.9 ms 34ms 108ms 42.97ms
(APU Output) EC Pin 108 Input APU_PWRGD C19
111.2 ms 60.50 ms79.99ms 25ms 111.1ms 36.01ms
(APU Output) EC Pin 13 Intput PLT_RST#

111.2 ms 60.50 ms80.00 ms 28ms 111.1ms 39.01ms
AN7
(APU Output) APU_PCIE_RST#
113.6 ms 58.21 ms82.18 ms 31ms 113.1ms 42.97ms
APU_RST#
D15
(APU Output) EC Pin 118 Intput
5.57 ms
(APU Output) PXS_RST# 460ms
1.269 ms 3.462ms 1.165ms 3.981ms

PXS_PWREN
(APU Output)
65.75 us 62.5us -57.35us -166.7us
+3VGS
3.417ms 2.875ms 3.752ms 5.781ms
+VGA_PCIE
A <20ms 136.3us A
-2.708ms -87.12us -2.429ms
+1.8VGS
5.823ms -2.429ms 5.764ms 4.071ms
+VGA_CORE
5.818ms 4.625ms 5.759ms
+VDDCI 3.875ms

S5_MUX_CTRL
0.3
5 4 3 2 1
1 2 3 4 5
Main Func = dGPU

PEG_HTX_C_GRX_P[0..3]
<6> PEG_HTX_C_GRX_P[0..3]
PEG_HTX_C_GRX_N[0..3]
<6> PEG_HTX_C_GRX_N[0..3]
PEG_GTX_C_HRX_P[0..3]
<6> PEG_GTX_C_HRX_P[0..3]
PEG_GTX_C_HRX_N[0..3]
<6> PEG_GTX_C_HRX_N[0..3]
Vinafix.com @
UV1A
A A
PEG_HTX_C_GRX_P0 AF30 AH30 PEG_GTX_HRX_P0 DIS@ 2 1 CV1 .1U_0402_16V7K PEG_GTX_C_HRX_P0

PEG_HTX_C_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PEG_GTX_HRX_N0 DIS@ 2 1 CV2 .1U_0402_16V7K PEG_GTX_C_HRX_N0
PCIE_RX0N PCIE_TX0N
PEG_HTX_C_GRX_P1 AE29 AG29 PEG_GTX_HRX_P1 DIS@ 2 1 CV3 .1U_0402_16V7K PEG_GTX_C_HRX_P1

PEG_HTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PEG_GTX_HRX_N1 DIS@ 2 1 CV4 .1U_0402_16V7K PEG_GTX_C_HRX_N1
PCIE_RX1N PCIE_TX1N
PEG_HTX_C_GRX_P2 AD30 AF27 PEG_GTX_HRX_P2 DIS@ 2 1 CV5 .1U_0402_16V7K PEG_GTX_C_HRX_P2

PEG_HTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PEG_GTX_HRX_N2 DIS@ 2 1 CV6 .1U_0402_16V7K PEG_GTX_C_HRX_N2
PCIE_RX2N PCIE_TX2N
PEG_HTX_C_GRX_P3 AC29 AD27 PEG_GTX_HRX_P3 DIS@ 2 1 CV7 .1U_0402_16V7K PEG_GTX_C_HRX_P3

PEG_HTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PEG_GTX_HRX_N3 DIS@ 2 1 CV8 .1U_0402_16V7K PEG_GTX_C_HRX_N3
PCIE_RX3N PCIE_TX3N
No Use GPU Display Port outpud
AB30 AC25
AA31 PCIE_RX4P PCIE_TX4P AB25 @
PCIE_RX4N PCIE_TX4N UV1F
+VGA_CORE
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N AB11 0_0402_5% 2 TOPAZ@
TOPAZ@1 RV255
VARY_BL AB12 0_0402_5% 2 TOPAZ@1
TOPAZ@ RV254
Y30 AB27 DIGON
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N FOR TOPAS CORE POWER USE
W29 Y27 AL15

V28 PCIE_RX7P PCIE_TX7P Y26 TXCAP_DPA3P AK14
PCIE_RX7N PCIE_TX7N TXCAM_DPA3N
B B
AH16
V30 W24 TX0P_DPA2P AJ15
UV1 TOPAZ@ U31 NC#V30 NC#W24 W23 TX0M_DPA2N
NC#U31 NC#W23 AL17
TX1P_DPA1P AK16
U29 V27 TX1M_DPA1N
T28 NC#U29 NC#V27 U26 AH18
NC#T28 NC#U26 TX2P_DPA0P AJ17
TX2M_DPA0N
PCI EXPRESS INTERFACE

TOPAZ XT S3 FCBGA 631P GPU 0FD
T30 U24 AL19
SA000079N0L R31 NC#T30 NC#U24 U23 NC_TXOUT_L3P AK18
NC#R31 NC#U23 NC_TXOUT_L3N
R29 T26 TMDP

UV1 EXO@ P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 AH20
TXCBP_DPB3P AJ19
P30 T24 TXCBM_DPB3N
N31 NC#P30 NC#T24 T23 AL21
NC#N31 NC#T23 TX3P_DPB2P AK20
TX3M_DPB2N
EXO XT S3 FCBGA 631P 0FD
N29 P27 AH22
SA000089Y1L M28 NC#N29 NC#P27 P26 TX4P_DPB1P AJ21
NC#M28 NC#P26 TX4M_DPB1N
AL23
M30 P24 TX5P_DPB0P AK22
L31 NC#M30 NC#P24 P23 TX5M_DPB0N
NC#L31 NC#P23 AK24
NC_TXOUT_U3P AJ23
L29 M27 NC_TXOUT_U3N
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
2160856030-A0_FCBGA631
C ? C
CLOCK
CLK_PEG_VGA AK30
<10> CLK_PEG_VGA PCIE_REFCLKP
CLK_PEG_VGA# AK32
<10> CLK_PEG_VGA# PCIE_REFCLKN +0.95VSDGPU
CALIBRATION
Y22 RV1 1 DIS@ 2 1K_0402_1%
DIS@ PCIE_CALR_TX
RV2 1 2 1K_0402_1% N10 AA22 RV3 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
PLT_RST_VGA# AL27
PERSTB
2160856030-A0_FCBGA631
+3VGS
UV2 DIS@
DGPU_HOLD_RST#(GPIO191)
5
PXS_RST# 2
P
<9> PXS_RST# B 4 PLT_RST_VGA#

APU_PCIE_RST# 1 Y
<9,19,20> APU_PCIE_RST# A
G
1
3
RV4
100K_0402_5%
D D
DIS@
2
MC74VHC1G08DFT2G_SC70-5

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_PCIE/DP
Custom 0.3
Date:
Tulip AAL12
LA-C142P
of 56
1 2 3 4 5
1 2 3 4 5
Main Func = dGPU Resistor Divider Lookup Lable

+3VGS
@
R_pu (ohm) R_pd (ohm) Bitd [3:1]
UV1B +1.8VGS
U? PS_0[3:1]=001 Strap Name :
NC 4.75k 000
PS_0[5:4]=11
1
RV5 RV6 AF2
8.45k 2k 001 DIS@
PS_0[1] ROM_CONFIG[0]
NC#AF2
5
45.3K_0402_1% 45.3K_0402_1% AF4 4.53k 2k 010 RV8 PS_0[2] ROM_CONFIG[1]
G
NC#AF4 8.45K_0402_1%
DIS@ DIS@ DIS@ 1 N9 AG3 6.98k 4.99k 011 PS_0[3] ROM_CONFIG[2]
T201
2
DMN66D0LDW-7 2N SOT363-6 1 L9 DBG_DATA16 NC#AG3 AG5 PS_0
T202 DBG_DATA15 NC#AG5
3 4 VGA_SMB_DA3 1 AE9 DPA 4.53k 4.99k 100 PS_0[4] N/A
S
<8,27,28,31> EC_SMB_DA2
Vinafix.com
T203 DBG_DATA14
1
1 Y11 AH3
D
1
0.68U_0402_10V
T204 DBG_DATA13 NC#AH3
QV1B 1 AE8 AH1 DIS@
1 @ 2
T205
1 AD9 DBG_DATA12 NC#AH1 3.24k 5.62k 101 CV29 RV9
PS_0[5] AUD_PORT_CONN_PINSTRAP[0]
T206 DBG_DATA11
2
RV167 0_0402_5% 1 AC10 AK3 2K_0402_1%
3.4k 10k 110
G
T207 DBG_DATA10 NC#AK3 2
1 AD7 AK1 @
T208
2
DIS@ 1 AC8 DBG_DATA9 NC#AK1
A
DMN66D0LDW-7 2N SOT363-6
T209
1 AC7 DBG_DATA8 DVO
AK5
4.75k NC 111 A
T210 DBG_DATA7 NC#AK5
6 1 VGA_SMB_CK3 1 AB9 AM3 0402 1% resistors are equired
S
<8,27,28,31> EC_SMB_CK2 T211 DBG_DATA6 NC#AM3
1 AB8
D
T212 DBG_DATA5
QV1A 1 AB7 AK6
T213 DBG_DATA4 NC#AK6
1 @ 2 1 AB4 AM5
T214 DBG_DATA3 NC#AM5
RV166 0_0402_5% 1 AB2
T215
1 Y8 DBG_DATA2 DPB
AJ7
Capacitor Divider Lookup Lable
T216
1 Y7 DBG_DATA1 NC#AJ7 AH6 +1.8VGS Strap Name :
+3VGS T217 DBG_DATA0 NC#AH6 PS_1[3:1]=000
@ AK8
Cap (nF) Bitd [5:4]
RV146 NC#AK8 PS_1[5:4]=11 PS_1[1] STRAP_BIF_GEN3_EN_A
1
+3VGS AL7
1 2 THM_ALERT# NC#AL7 @
680nF 00 RV11
PS_1[2] TRAP_BIF_CLK_PM_EN
4.7K_0402_5% W6 82nF 01 8.45K_0402_1% PS_1[3] N/A
NC#W6
2
@ V6
2
RV58 NC#V6 V4 PS_1
+3VGS NC#V4 10nF 10 PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING
4.7K_0402_5% SA010320110 (S IC ADM1032ARMZ MSOP 8P TEMP SENSOR) AC6
NC#AC5 NC#U5
U5
1
AC5 NC 11 1 PS_1[5] STRAP_TX_DEEMPH_EN
0.68U_0402_10V
1000P_0402_50V7K NC#AC6 W3 DIS@
1
@ UV11 AA5 NC#W3 V2 CV28 RV12

1 2 VGA_DPLUS CV9 @ 1 2 AA6 NC#AA5 NC#V2 RV16 2G_S@ 4.75K_0402_1%
DPC
VDD1 D+ NC#AA6 Y4 @ 2
2
@ THM_ALERT# 6 3 VGA_DMINUS +1.8VGS NC#Y4 W5
1 ALERT# D- NC#W5
CV10
0.1U_0402_16V4Z 4 8 VGA_SMB_CK3_R 1 @ 2 VGA_SMB_CK3 RV82 2 TOPAZ@1
TOPAZ@ 4.7K_0402_5% BP_0 U1 AA3 PLL_Analog_out
THERM# SCLK RV164 0_0402_5% 1FB_VDDCI W1 NC#U1 NC#AA3 Y2
T222 NC#W1 NC#Y2
1
2 5 7 VGA_SMB_DA3_R 1 @ 2 VGA_SMB_DA3 RV81 2 TOPAZ@1
TOPAZ@ 4.7K_0402_5% BP_1 U3
GND SDATA NC#U3 4.75K_0402_1%
RV165 0_0402_5% Y6 J8 RV83
1PLL_Analog_in AA1 NC#Y6 NC#J8 16.2K_0402_1% SD034475180 +1.8VGS
ADM1032ARMZ_MSOP8
T221 NC#AA1 TOPAZ@
PS_2[3:1]=000 Strap Name :
RV15 2G_H@ RV16 2G_H@
PS_2[5:4]=01
1
Address:100_1101 @
PS_2[1] N/A
For 2nd I2C RV28
8.45K_0402_1%
PS_2[2] N/A
SA00001Z710 (S IC EMC1402-2-ACZL-TR MSOP 8P SENSOR) 1 R1 PS_2[3] STRAP_BIOS_ROM_EN
T223
2
SCL
+3VGS +3VGS +3VGS
SA00003PU00 (S IC W83L771AWG-2 TSSOP 8P SENSOR) T224
1 R3
SDA 8.45K_0402_1% 2K_0402_1% PS_2
+1.8VGS PS_2[4] STRAP_BIF_VGA_DIS
1
AM26 SD000000680 SD034200180 1
0.082U_0402_16V
+VGA_CORE R AK26 DIS@
U6
GENERAL PURPOSE I/O AVSSN#AK26 +3VGS RV15 2G_M@ RV16 2G_M@ CV11 RV13
PS_2[5] N/A
2 GPIO_0
2
2 U10 AL25 4.75K_0402_1%

CV166 @ RV71 RV72 T10 GPIO_1 G AJ25 DIS@ 2
2
GPIO_2 AVSSN#AJ25
1
0.1U_0402_10V7K 10K_0402_5% 10K_0402_5% @ CV170 VGA_SMB_DA3 U8
B 1 EXO@ EXO@ VGA_SMB_CK3 U7 SMBDATA AH24 RV162 B
0.1U_0402_10V7K
1 VGA_AC__BATT T9 SMBCLK B AG25 4.7K_0402_5%
1
@ PCC_GPIO_6 T8 GPIO_5_AC_BATT AVSSN#AG25 @

U1 GPIO_6 DAC1
4.53K_0402_1% 2K_0402_1%
EXO@ @ T7 AH26
2
0_0402_5% 1 8 33_0402_5% P10 GPIO_7_BLON HSYNC AJ27 WAKEB SD034453180 SD034200180
GPU_VID3 RV75 1 2 GPU_VID3_GPIO_15 2 VCCA VCCB 7 RV77 1 2 SVI2_SVD P4 GPIO_8_ROMSO VSYNC
A1 B1 SVI2_SVD <53> GPIO_9_ROMSI
1
GPU_VID1 RV76 1 2 GPU_VID1_GPIO_20 3 6 RV78 1 2 SVI2_SVC P2 RV15 2G_M2@ RV16 2G_M2@ +1.8VGS
DIR 5 A2 B2 4
SVI2_SVC <53>
N6 GPIO_10_ROMSCK AD22 RV163
PS_3[3:1]=000 Strap Name :
0_0402_5% DIR GND 33_0402_5% +VGA_CORE N5 GPIO_11 RSET 4.7K_0402_5%
GPIO_12 PS_3[5:4]=11
2
1
EXO@ @ N3 AG24 DIS@ PS_3[1] BOARD_CONFIG[0] (Memory ID)
S IC SN74AVC2T45DCTR_SM8 Y9 GPIO_13 AVDD AE22 @
2
GPU_VID3 N1 GPIO_14_HPD2 AVSSQ RV15
RV73 RV74 M4 GPIO_15_PWRCNTL_0 AE23 8.45K_0402_1%
PS_3[2] BOARD_CONFIG[1] (Memory ID)
GPIO_16 VDD1DI 6.98K_0402_1% 4.99K_0402_1%
10K_0402_5% 10K_0402_5% U1 CPN is phase out THM_ALERT# R6 AD23 PS_3[3] BOARD_CONFIG[2] (Memory ID)
1
2
@ @ W10 GPIO_17_THERMAL_INT VSS1DI SD000002680 SD034499180 PS_3
GPIO19_CTF M2 GPIO_18
GPIO_19_CTF FutureASIC/SEYMOUR/PARK PS_3[4] AUD_PORT_CONN_PINSTRAP[1]
1
GPU_VID3 1 EXO@ 2 SVI2_SVD GPU_VID1 P8 AM12 1
0.68U_0402_10V
RV169 0_0402_5% P7 GPIO_20_PWRCNTL_1 CEC_1 @
GPU_VID1 1 EXO@ 2 SVI2_SVC N8 GPIO_21 CV15 RV16
PS_3[5] AUD_PORT_CONN_PINSTRAP[2]
RV168 0_0402_5% AK10 GPIO_22_ROMCSB AK12 TOPAZ@ 1 RV155 2 0_0402_5% SVI2_SVD 4.75K_0402_1%
EXO@ AM10 GPIO_29 RSVD#AK12 AL11 TOPAZ@ 1 RV156 2 0_0402_5% SVI2_SVT @ 2 SD034475180
SVI2_SVT <53> 2G_H@ -->Hynix
2
+3VGS 10K_0402_5% CV169 10U_0603_6.3V6M 1 @ 2 PEG_CLKREQ#_G N7 GPIO_30 RSVD#AL11 AJ11 TOPAZ@ 1 RV157 2 0_0402_5% SVI2_SVC
<9> PEG_CLKREQ# CLKREQB RSVD#AJ11
RV79 2 1 DIR 2 1 RV153 0_0402_5%
3.3V TO 1.8V LEVEL SHIF JTAG_TRSTB L6 2G_S@ -->Samsung
EXO@ CV167 JTAG_TDI L5 JTAG_TRSTB
2 1 0.1U_0402_10V7K For JET/SUN to support SVI2 reaulator JTAG_TCK L3 JTAG_TDI 2G_M@ -->Micron
JTAG_TMS L1 JTAG_TCK AL13 Topaz SVI2 2G_M2@-->Micron
EXO@ DNI for TOPAZ T86 1 JTAG_TDO K4 JTAG_TMS
JTAG_TDO
GENLK_CLK
GENLK_VSYNC
AJ13
TESTEN K7
AF24 TESTEN +1.8VGS +1.8VGS
+VGA_CORE NC#AF24 AG13
SWAPLOCKA AH12
AB13 SWAPLOCKB Memory ID P/N Vendor Configuration Size
GENERICA
2
+3VGS +1.8VGS W8
W9 GENERICB RV84 RV87
W7 GENERICC AC19 PS_0 10K_0402_5% 10K_0402_5%
RV154 1 @ 2 5.1K_0402_1% RV152 @ AD10 GENERICD PS_0 TOPAZ@ @ SSI (default) 000 SA000076P2L SAMSUNG K4W4G1646E-BC1A 2GB
2 1 GPIO19_CTF AJ9 GENERICE AD19 PS_1
1
1 AL9 NC#AJ9 PS_1
RV17 1 DIS@ 2 1K_0402_1% TESTEN 10K_0402_5% T4935 NC#AL9 AE17 PS_2 001 SA00008DN1L HYNIX H5TC4G63CFR-N0C 2GB
PS_2
2
DIS@ AC14 SVI2_SVD

RV151 1 PX_EN AB16 HPD1 AE20 PS_3 SVI2_SVC
10K_0402_5%
T218 PX_EN PS_3 010 SA000065D1L Micron MT41K256M16HA-107G 2GB
C AE19 C
011 SA000077K1L Micron MT41J256M16HA-093G:E 2GB
1
TS_A
2
AC16
DBG_VREFG
+3VGS
RV89 RV88 100 NA NA NA
DDC/AUX 10K_0402_5% 10K_0402_5%
1
1 8 JTAG_TRSTB AE6 @ TOPAZ@
2 7 JTAG_TDI PLL/CLOCK DDC1CLK AE5 101 NA NA NA
3 6 JTAG_TMS DDC1DATA
4 5 JTAG_TCK AD2
RV20 DIS@ AUX1P AD4 +VGA_CORE
1M_0402_5% RP34 10K_8P4R_5% AUX1N Tulip AMD 2G VRAM Only
XTALOUT XTALIN @ AC11 RV60 1 @ 2
DDC2CLK AC13 0_0603_1%
DDC2DATA Short_pad
YV1 DIS@
27MHZ_10PF_7V27000050 XTALIN AM28 AD13
RV158
XTALOUT AK28 XTALIN AUX2P AD11 RV159
XTALOUT AUX2N
3
3 1
1 RV60
RV29 1 DIS@ 2 10K_0402_5% AC22 AD20 FB_GND RV158 1 TOPAZ@ 2 0_0402_5% VSSSENSE_VGA VSSSENSE_VGA <53>
1 GND GND 1 XO_IN NC#AD20
RV59 1 2 10K_0402_5% AB22 AC20 FB_VDDC RV159 1 2 0_0402_5% VCCSENSE_VGA VCCSENSE_VGA <53>
CV18 CV17 1 2 DIS@ XO_IN2 NC#AC20 TOPAZ@
4 2 +3VALW +V_UV4
DIS@ 8.2P_0402_50V 8.2P_0402_50V RV94 @ 0_0603_5% AE16
2 2 DIS@ NC#AE16 AD16
NC#AD16
SEYMOUR/FutureASIC AC1
1 @ 2 +1.8VGS VGA_DPLUS T4 DDCVGACLK AC3
+3VGS DPLUS THERMAL DDCVGADATA
RV93 0_0603_1% LV2 DIS@ VGA_DMINUS T2
1 2 13mA DMINUS
BLM15BD121SN1D_0402
GPIO28 R5 +VGA_CORE
CV19 2 DIS@
1 10U_0603_6.3V6M +TSVDD AD17 GPIO28_FDO
AC17 TSVDD DIS@
CV20 2 DIS@
1 1U_0402_6.3V4Z TSVSS VCCSENSE_VGA 1 2
VSSSENSE_VGA RV161 1 DIS@ 210_0402_5%
CV21 2 DIS@
1 0.1U_0402_10V6K RV160 10_0402_5%
+3VGS
2160856030-A0_FCBGA631
+3VGS RV21 1 EXO@ 2 10K_0402_5% ?
TOPAZ Thermal Address-->0x82

1
1
RV148
RV147 100K_0402_5%
Enable MLPS
@ DIS@
4.7K_0402_5% +V_UV4
2
VGA_AC__BATT
2
QV8A +3VGS
D 1 D
@ CV22
3
@ 0.1U_0402_25V6K
PACIN# 5 G
D
2 RV91
S 10K_0402_5%
@ TOPAZ@
Enable --> Low
4
QV8B UV4 DIS@

1
6
DMN66D0LDW-7_SOT363-6 1 Disenable --> High

G VCC
D <27,41,42> ACIN B
1 2 2 G 4 VGA_AC__BATT
<27,41,42> ACIN Y OCP_L <53>
S 2 PCC_GPIO_6 1 @ 2 OCP_L
<27> ACIN_65W A
RV149 2 RV90 0_0402_5%
1
0_0402_5% MC74VHC1G08DFT2G_SC70-5
3
@ 2 1 @
CVT90
<27> ACIN_65W
RV92 @ 0_0402_5% 0.1U_0402_10V7K 1 Security Classification Compal Secret Data
Title
Peak Current Control (PCC) CKT Issued Date 2014/06/10 Deciphered Date 2015/06/30 TOPAZ_MSIC
Reversed THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Custom 0.3
Date:
Tulip AAL12
LA-C142P
of 56
1 2 3 4 5
1 2 3 4 5
Main Func = dGPU
Vinafix.com
A A
@
UV1E U?
+1.35VS_VGA TO +1.35V_MEM_GFX +1.8VGS

370mA (HDMI) No Use GPU Display Port outpud AA27
AB24
AB32
GND
GND
GND
GND
A3
A30
AA13
@
188mA (Display Port) @ AC24 GND GND AA16
1 2 +DP_VDDR UV1G AC26 GND GND AB10
B
JP9 DEFAULT SHORT RV27 0_0603_5%
U?
AC27
AD25
GND
GND
GND
GND
AB15
AB6 B
CV26
CV27
CV35
DP POWER NC/DP POWER
AD32 GND GND AC9
1 1 1 GND GND
AG15 AE11 AE27 AD6
AG16 DP_VDDR#AG15 NC#AE11 AF11 AF32 GND GND AD8
AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
2 2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
AG18 DP_VDDR#AG17 NC#AF13 AG8 K28 GND GND AH10
Short_pad
DIS@
DIS@
DIS@
AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
RV27 DP_VDDR#AG19 NC#AG10 GND GND
AF14 L27 B10
RV30 DP_VDDR#AF14 M32 GND GND B12
N25 GND GND B14
N27 GND GND B16
P25 GND GND B18
AG20 AF6 P32 GND GND B20
AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
+0.95VSDGPU AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
@
280mA AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
1 2 +DP_VDDC AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
RV30 0_0603_5% DP_VDDC#AD14 U27 GND GND B8
V32 GND GND C1
CV30
CV33
CV34
W25 GND GND C32
1 1 1 GND GND
AG14 AE1 W26 E28
AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
AM18 DP_VSSR NC#AG6 AH5 GND GND F16
DIS@
DIS@
DIS@
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
C C
P9 GND GND G27
R12 GND GND G31
AF17 AE10 R15 GND GND G8
DPAB_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
2160856030-A0_FCBGA631 GND GND
? T18 H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND
Y20 GND
R11 GND A32
T11 GND VSS_MECH AM1
AA11 GND VSS_MECH AM32
M12 GND VSS_MECH
N11 GND
V11 GND
GND
2160856030-A0_FCBGA631
?
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_Power/GND
Custom 0.3
Date:
Tulip AAL12
LA-C142P
of 56
1 2 3 4 5
1 2 3 4 5
Main Func = dGPU
Vinafix.com
A
+VGA_CORE 10uF 1uF 0.1uF A
VDDC TBD 5 (1@) 10 (2@) 0 @

UV1D +1.8VGS
+1.35V_MEM_GFX
U?
100mA
AM30 +PCIE_PVDD
VDDCI 3.5A 1 3 0 1.5A MEM I/O PCIE_PVDD
PCIE
CV38
CV46
CV39
H13 AB23
CV196
VDDR1 NC#AB23 1 1 1 1
H16 AC23
H19 VDDR1 NC#AC23 AD24
CV43
CV44
CV45
CV40
CV47
CV48
CV41
CV42
CV49
CV50
CV51
CV52
CV53
J10 VDDR1 NC#AD24 AE24
CV174
CV175
CV176
CV177
CV178
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
0.01U_0402_16V7K
J23 VDDR1 NC#AE24 AE25 2 2 2 2
+0.95VSDGPU 10uF 1uF 0.1uF J24 VDDR1 NC#AE25 AE26
DIS@
DIS@
DIS@
DIS@
J9 VDDR1 NC#AE26 AF25
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 K10 VDDR1 NC#AF25 AG26
K23 VDDR1 NC#AG26
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
PCIE_VDDC 2.5A 2 (1@) 5 (1@) 0 K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25
BIF_VDDC 1.4A 0 1 0 L13 VDDR1 PCIE_VDDC L26
L20 VDDR1 PCIE_VDDC M22 +0.95VSDGPU
L21 VDDR1 PCIE_VDDC N22 2.5A
L22 VDDR1 PCIE_VDDC N23
SPLL_VDDC 100mA 1 1 1 VDDR1 PCIE_VDDC N24
CV54
CV55
CV56
CV57
CV58
CV59
CV60
CV198
CV197
PCIE_VDDC R22
PCIE_VDDC 1 1 1 1 1 1 1 1 1
T22
+1.8VGS 13mA LEVEL PCIE_VDDC U22
LV3 DIS@ TRANSLATION PCIE_VDDC V22
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2 +VDD_CT AA20 PCIE_VDDC 2 2 2 2 2 2 2 2 2
+1.35V_MEM_GFX 10uF 2.2uF 0.1uF 0.01uF BLM15BD121SN1D_0402 AA21 VDD_CT
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
AB20 VDD_CT AA15
CV61
CV62
CV63
B
AB21 VDD_CT CORE VDDC N15 B
1 1 1 VDD_CT VDDC N17
VDDR1 1.5A 3 5 5 5 +3VGS VDDC R13
LV4 DIS@ 25mA I/O VDDC R16
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 1 2 +VDDR3 AA17 VDDC R18
BLM15BD121SN1D_0402 AA18 VDDR3 VDDC Y21
DIS@
DIS@
DIS@
AB17 VDDR3 VDDC T12
CV64
CV65
CV66
CV192
AB18 VDDR3 VDDC T15 +VGA_CORE
+1.8VGS 10uF 1uF 0.1uF 1 1 1 1 VDDR3 VDDC T17 TBD
V12 VDDC T20
Y12 VDDR4 VDDC U13
CV67
CV68
CV69
CV70
CV71
CV72
CV73
CV74
CV75
CV76
CV77
CV78
CV79
CV80
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 U12 VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 1 VDDR4 VDDC U18
1 1 1 1 1 1 1 1 1 1 1 1 1 1
DIS@
DIS@
DIS@
DIS@
VDDC V21
VDDC V15
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDC V17 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MPLL_PVDD 130mA 1 1 1 VDDC V20
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDR4 (300mA) 0 0 0 VDDC
CV205
CV206
CV203
CV201
CV207
CV208
CV204
CV200
CV199
CV202
+1.8VGS
LV6 DIS@ 130mA PLL
1 1 1 1 1 1 1 1 1 1
1 2 +MPLL_PVDD
VDD_CT 13mA 1 1 1 BLM15BB221SN1D_2P
CV81
CV82
CV193
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2
1 1 1
R21 1.4A
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
BIF_VDDC U21 +BIF_VDDC
+TSVDD 13mA 1 1 1 BIF_VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 L8
+1.8VGS MPLL_PVDD
DIS@
DIS@
DIS@
C
LV7 DIS@ 75mA C
+DP_VDDR 0 0 0 1 2 +SPLL_PVDD
ISOLATED
CORE I/O
BLM15BD121SN1D_0402 M13
CV84
CV85
CV86
H7 VDDCI M15
1 1 1 SPLL_PVDD VDDCI M16
CV209
CV216
CV211
CV213
CV217
CV214
CV218
CV212
CV215
CV210
+DP_VDDC 0 0 0 VDDCI M17 1 1 1 1 1 1 1 1 1 1
+0.95VSDGPU VDDCI M18
100mA
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 LV8 DIS@ VDDCI M20

1 2 +SPLL_VDDC H8 VDDCI M21
DIS@
DIS@
DIS@
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 SPLL_VDDC VDDCI N20 2 2 2 2 2 2 2 2 2 2
CV91
CV92
CV93
J7 VDDCI
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
+3VGS 10uF 1uF 0.1uF 1 1 1 SPLL_PVSS
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2
VDDR3 25mA 0 2 (1@) 1 2160856030-A0_FCBGA631
?
DIS@
DIS@
DIS@
+0.95VSDGPU
+BIF_VDDC 1
@ 2
RV31 0_0805_5%
+VDDCI +VGA_CORE
CV195
CV194
CV168
1 2 2
3.5A (DDR3) LV25 DIS@
1 2
DIS@
DIS@
DIS@
BLM15BD121SN1D_0402
CV88
CV89
CV90
CV87
1 1 1 1 LV26
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 1 1 1 2
BLM15BD121SN1D_0402
DIS@
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2
DIS@
DIS@
DIS@
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_Power
Custom 0.3
Date:
Tulip AAL12
LA-C142P
of 56
1 2 3 4 5
1 2 3 4 5
Main Func = dGPU
M_DA[63..0]
<38,39> M_DA[63..0]
M_MA[15..0]
<38,39> M_MA[15..0]
<38,39> M_DQM[7..0]
M_DQM[7..0] Vinafix.com
M_DQS[7..0]
<38,39> M_DQS[7..0]
A A
M_DQS#[7..0]
<38,39> M_DQS#[7..0]
@
UV1C U?
GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M_MA0
M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M_MA1
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M_MA2
M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M_MA3
M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M_MA4
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M_MA6
+1.35V_MEM_GFX +1.35V_MEM_GFX M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_10
1
1
M_DA11 C28 J14 M_MA8
DIS@ DIS@ M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M_MA9
RV33 RV32 M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M_MA10
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M_MA12
2
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M_BA2

DQA0_16 MAA1_5/MAA_BA2 M_BA2 <38,39>
+MVREFDA +MVREFSA M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6/MAA_BA0 M_BA0 <38,39>
M_DA18 E25 L15 M_BA1
DQA0_18 MAA1_7/MAA_BA1 M_BA1 <38,39>
M_DA19 D24 G14 M_MA14
DQA0_19 MAA1_8/MAA_14
1
1 1 M_DA20 E23 L16
MEMORY INTERFACE
DIS@ DIS@ DIS@ DIS@ M_DA21 F23 DQA0_20 MAA1_9/RSVD
RV34 CV94 RV35 CV95 M_DA22 D22 DQA0_21 E32 M_DQM0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_DQM1
2 2 M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_DQM2
2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_DQM3

M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_DQM4
B
M_DA27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 M_DQM5 B
M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_DQM6
M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_DQM7
M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3
M_DA31 C17 DQA0_30 H28 M_DQS0
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_DQS1
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_DQS3
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_DQS4
M_DA36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 M_DQS5
DIS@ DIS@ M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_DQS6
RV36 RV37 M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_DQS7
49.9_0402_1% 10_0402_1% M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3
1 2 2 1 DRAM_RST_G M_DA40 E11 DQA1_7 H27 M_DQS#0
<38,39> DRAM_RST DQA1_8 DDBIA0_0/QSA0_0B
M_DA41 A11 A27 M_DQS#1
M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DQS#2
DQA1_10 DDBIA0_2/QSA0_2B
1
1 1 M_DA43 F11 C19 M_DQS#3

DIS@ DIS@ @ M_DA44 A9 DQA1_11 DDBIA0_3/QSA0_3B C15 M_DQS#4
CV96 RV38 CV97 M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DQS#5
120P_0402_50V8J 5.1K_0402_1% 68P_0402_50V8J M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DQS#6
2 2 M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DQS#7
2
M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B

M_DA49 A7 DQA1_16 L18 VRAM_ODT0
DQA1_17 ADBIA0/ODTA0 VRAM_ODT0 <38>
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1/ODTA1 VRAM_ODT1 <39>
M_DA51 F7
M_DA52 A5 DQA1_19 H26 M_CLK0
DQA1_20 CLKA0 M_CLK0 <38>
M_DA53 E5 H25 M_CLK#0
DQA1_21 CLKA0B M_CLK#0 <38>
M_DA54 C3
M_DA55 E1 DQA1_22 G9 M_CLK1
Place close to GPU (within 25mm) M_DA56 G7 DQA1_23 CLKA1 H9 M_CLK#1
M_CLK1 <39>
DQA1_24 CLKA1B M_CLK#1 <39>
and place componment close to each other M_DA57 G6
DQA1_25
M_DA58 G1 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 <38>
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 <39>
M_DA60 J6
M_DA61 J1 DQA1_28 G19 M_CAS#0
C C
DQA1_29 CASA0B M_CAS#0 <38>
M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <39>
M_DA63 J5
DQA1_31 H22 M_CS0B#0
CSA0B_0 M_CS#0 <38>
+MVREFDA K26 J22
+MVREFSA J26 MVREFDA CSA0B_1
MVREFSA G13 M_CS1B#0
CSA1B_0 M_CS#1 <39>
J25 K13
RV39 1 DIS@ 2 120_0402_1% K25 NC#J25 CSA1B_1
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <38>
J17 M_CKE1
CKEA1 M_CKE1 <39>
G25 M_WE#0
WEA0B M_WE#0 <38>
DRAM_RST_G L10 H10 M_WE#1
DRAM_RST WEA1B M_WE#1 <39>
RV40 @ 1 2 51.1_0402_1% CV98 @1
@ 2 0.1U_0402_16V4Z K8
RV41 @ 1 2 51.1_0402_1% CV99 @
@1 2 L7 CLKTESTA
0.1U_0402_16V4Z CLKTESTB
Route 50ohms single-ended/100ohm diff and keep short

2160856030-A0_FCBGA631
debug only, for clock observation,if not need, DNI. ?
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_MEM
Custom 0.3
Date:
Tulip AAL12
LA-C142P
of 56
1 2 3 4 5
1 2 3 4 5
Main Func = dGPU
Memory Partition A - Lower 32 bits

M_DA[63..0]
<37,39> M_DA[63..0]
<37,39> M_MA[15..0]
<37,39> M_DQM[7..0]
M_MA[15..0]
M_DQM[7..0]
Vinafix.com
+1.35V_MEM_GFX +1.35V_MEM_GFX
A M_DQS[7..0] A
<37,39> M_DQS[7..0]
1
M_DQS#[7..0]
<37,39> M_DQS#[7..0]
DIS@ DIS@
RV42 RV43
4.99K_0402_1% UV5 4.99K_0402_1% UV6
2
+FBA_VREF0 M8 E3 M_DA17 +FBA_VREF1 M8 E3 M_DA30
H1 VREFCA DQL0 F7 M_DA23 H1 VREFCA DQL0 F7 M_DA27
UV5 VREFDQ DQL1 F2 M_DA21 VREFDQ DQL1 F2 M_DA31
DQL2 DQL2
1
1 M_MA0 N3 F8 M_DA22 1 M_MA0 N3 F8 M_DA24
DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA18 DIS@ DIS@ M_MA1 P7 A0 DQL3 H3 M_DA29
RV44 CV100 M_MA2 P3 A1 DQL4 H8 M_DA19 RV45 CV101 M_MA2 P3 A1 DQL4 H8 M_DA26
4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA16 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA28
2 M_MA4 P8 A3 DQL6 H7 M_DA20 2 M_MA4 P8 A3 DQL6 H7 M_DA25
2
M_MA5 P2 A4 DQL7 M_MA5 P2 A4 DQL7
256M16 K4W4G1646E-BC1A FBGA 96P A5 A5
M_MA6 R8 M_MA6 R8
SA000076P2L M_MA7 R2 A6 D7 M_DA5 M_MA7 R2 A6 D7 M_DA8
M_MA8 T8 A7 DQU0 C3 M_DA3 M_MA8 T8 A7 DQU0 C3 M_DA14
M_MA9 R3 A8 DQU1 C8 M_DA4 M_MA9 R3 A8 DQU1 C8 M_DA9
2G_S@ A9 DQU2 A9 DQU2
M_MA10 L7 C2 M_DA1 UV6 M_MA10 L7 C2 M_DA12
M_MA11 R7 A10/AP DQU3 A7 M_DA6 M_MA11 R7 A10/AP DQU3 A7 M_DA10
UV5 M_MA12 N7 A11 DQU4 A2 M_DA0 M_MA12 N7 A11 DQU4 A2 M_DA15
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA11
M_MA14 T7 A13 DQU6 A3 M_DA2 M_MA14 T7 A13 DQU6 A3 M_DA13
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.35V_MEM_GFX A15/BA3 +1.35V_MEM_GFX
256M16 K4W4G1646E-BC1A FBGA 96P
256M16 H5TC4G63CFR-N0C FBGA 96P M_BA0 M2 B2 SA000076P2L M_BA0 M2 B2
<37,39> M_BA0 BA0 VDD BA0 VDD
M_BA1 N8 D9 M_BA1 N8 D9
SA00008DN1L M_BA2 M3 G7 M_BA2 M3 G7
<37,39> M_BA2 BA2 VDD 2G_S@ BA2 VDD
K2 K2
VDD K8 VDD K8
2G_H@ VDD VDD
N1 UV6 N1
M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9
B <37> M_CLK0 CK VDD CK VDD B
UV5 M_CLK#0 K7 R1 M_CLK#0 K7 R1
<37> M_CLK#0 CK VDD CK VDD
M_CKE0 K9 R9 M_CKE0 K9 R9
<37> M_CKE0 CKE/CKE0 VDD +1.35V_MEM_GFX CKE/CKE0 VDD +1.35V_MEM_GFX
VRAM_ODT0 K1 A1 256M16 H5TC4G63CFR-N0C FBGA 96P VRAM_ODT0 K1 A1

<37> VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
M_CS#0 L2 A8 M_CS#0 L2 A8
<37> M_CS#0 CS/CS0 VDDQ CS/CS0 VDDQ
256M16 MT41K256M16HA-107G:E FBGA 96P M_RAS#0 J3 C1 SA00008DN1L M_RAS#0 J3 C1
<37> M_RAS#0 RAS VDDQ RAS VDDQ
M_CAS#0 K3 C9 M_CAS#0 K3 C9
<37> M_CAS#0 CAS VDDQ CAS VDDQ
SA000065D1L M_WE#0 L3 D2 2G_H@ M_WE#0 L3 D2
<37> M_WE#0 WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
2G_M@ VDDQ VDDQ
M_DQS2 F3 H2 UV6 M_DQS3 F3 H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS1 C7 DQSL VDDQ H9
UV5 DQSU VDDQ DQSU VDDQ
M_DQM2 E7 A9 M_DQM3 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM1 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS 256M16 MT41K256M16HA-107G:E FBGA 96P VSS
G8 G8
M_DQS#2 G3 VSS J2 SA000065D1L M_DQS#3 G3 VSS J2
256M16 MT41J256M16HA-093G:E FBGA 96P DQSL VSS DQSL VSS
M_DQS#0 B7 J8 M_DQS#1 B7 J8
SA000077K1L DQSU VSS M1 DQSU VSS M1
VSS 2G_M@ VSS
M9 M9
VSS P1 VSS P1
2G_M2@ VSS VSS
T2 P9 UV6 DRAM_RST T2 P9
<37,39> DRAM_RST RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
M_CLK0 DIS@ L1 NC/ODT1 VSSQ B9 DIS@ L1 NC/ODT1 VSSQ B9
NC/CS1 VSSQ 256M16 MT41J256M16HA-093G:E FBGA 96P NC/CS1 VSSQ
M_CLK#0 RV46 J9 D1 RV47 J9 D1
243_0402_1% L9 NC/CE1 VSSQ D8 SA000077K1L 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2
2
VSSQ VSSQ
1
C E8 2G_M2@ E8 C
RV48 RV49 VSSQ F9 VSSQ F9
40.2_0402_1% 40.2_0402_1% VSSQ G1 VSSQ G1
DIS@ DIS@ VSSQ G9 VSSQ G9
VSSQ VSSQ
2
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C FBGA 96P H5TC2G63FFR-11C FBGA 96P
1 @ @
DIS@
CV102
0.01U_0402_16V7K
2 +1.35V_MEM_GFX
+1.35V_MEM_GFX
U1406 side
U1407 side
CV103
CV104
CV105
CV106
CV107
CV108
CV109
CV110
CV111
CV112
CV113
CV114
CV115
CV116
CV117
CV171
CV172
CV118
CV119
CV120
CV121
CV122
CV123
CV124
CV125
CV126
CV127
CV128
CV129
CV130
CV131
CV132
CV173
CV179
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_VRAM
A Lower Rev
Custom 0.3
Date:
Friday, February 13, 2015 Sheet 38 of 56
1 2 3 4 5
1 2 3 4 5
Main Func = dGPU

Memory Partition A - Upper 32 bits
+1.35V_MEM_GFX
+1.35V_MEM_GFX
1
Vinafix.com
1
DIS@
DIS@ RV51
RV50 4.99K_0402_1% UV8
4.99K_0402_1% UV7
2
A M_DA[63..0] +FBA_VREF3 M8 E3 M_DA49 A
<37,38> M_DA[63..0]
2
+FBA_VREF2 M8 E3 M_DA38 H1 VREFCA DQL0 F7 M_DA53
M_MA[15..0] H1 VREFCA DQL0 F7 M_DA36 VREFDQ DQL1 F2 M_DA51
<37,38> M_MA[15..0] VREFDQ DQL1 DQL2
1
F2 M_DA37 1 M_MA0 N3 F8 M_DA54
DQL2 A0 DQL3
1
M_DQM[7..0] 1 M_MA0 N3 F8 M_DA35 DIS@ DIS@ M_MA1 P7 H3 M_DA50
<37,38> M_DQM[7..0] A0 DQL3 A1 DQL4
DIS@ DIS@ M_MA1 P7 H3 M_DA39 RV53 CV134 M_MA2 P3 H8 M_DA55
M_DQS[7..0] RV52 CV133 M_MA2 P3 A1 DQL4 H8 M_DA32 4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 A2 DQL5 G2 M_DA48
<37,38> M_DQS[7..0] A2 DQL5 2 A3 DQL6
4.99K_0402_1% 0.1U_0402_10V6K M_MA3 N2 G2 M_DA34 M_MA4 P8 H7 M_DA52
2
M_DQS#[7..0] 2 M_MA4 P8 A3 DQL6 H7 M_DA33 M_MA5 P2 A4 DQL7
<37,38> M_DQS#[7..0]
2
M_MA5 P2 A4 DQL7 M_MA6 R8 A5
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA60
M_MA7 R2 A6 D7 M_DA41 M_MA8 T8 A7 DQU0 C3 M_DA59
UV7 M_MA8 T8 A7 DQU0 C3 M_DA44 M_MA9 R3 A8 DQU1 C8 M_DA63
M_MA9 R3 A8 DQU1 C8 M_DA43 M_MA10 L7 A9 DQU2 C2 M_DA56
M_MA10 L7 A9 DQU2 C2 M_DA45 M_MA11 R7 A10/AP DQU3 A7 M_DA62
M_MA11 R7 A10/AP DQU3 A7 M_DA42 UV8 M_MA12 N7 A11 DQU4 A2 M_DA57
M_MA12 N7 A11 DQU4 A2 M_DA46 M_MA13 T3 A12 DQU5 B8 M_DA61
M_MA13 T3 A12 DQU5 B8 M_DA40 M_MA14 T7 A13 DQU6 A3 M_DA58
M_MA14 T7 A13 DQU6 A3 M_DA47 M_MA15 M7 A14 DQU7
256M16 K4W4G1646E-BC1A FBGA 96P A14 DQU7 A15/BA3
M_MA15 M7 +1.35V_MEM_GFX
SA000076P2L A15/BA3 +1.35V_MEM_GFX
256M16 K4W4G1646E-BC1A FBGA 96P M_BA0 M2 B2
M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9
2G_S@ <37,38> M_BA0 BA0 VDD BA1 VDD
M_BA1 N8 D9 SA000076P2L M_BA2 M3 G7
M_BA2 M3 G7 K2
<37,38> M_BA2 BA2 VDD VDD
UV7 K2 K8
VDD 2G_S@ VDD
K8 N1
VDD N1 M_CLK1 J7 VDD N9
M_CLK1 J7 VDD N9 M_CLK#1 K7 CK VDD R1
<37> M_CLK1 CK VDD CK VDD
M_CLK#1 K7 R1 UV8 M_CKE1 K9 R9
<37> M_CLK#1 CK VDD CKE/CKE0 VDD +1.35V_MEM_GFX
M_CKE1 K9 R9
<37> M_CKE1 CKE/CKE0 VDD +1.35V_MEM_GFX
256M16 H5TC4G63CFR-N0C FBGA 96P
VRAM_ODT1 K1 A1
SA00008DN1L VRAM_ODT1 K1 A1 M_CS#1 L2 ODT/ODT0 VDDQ A8
<37> VRAM_ODT1 ODT/ODT0 VDDQ CS/CS0 VDDQ
M_CS#1 L2 A8 M_RAS#1 J3 C1
B <37> M_CS#1 CS/CS0 VDDQ RAS VDDQ B
M_RAS#1 J3 C1 256M16 H5TC4G63CFR-N0C FBGA 96P M_CAS#1 K3 C9
2G_H@ <37> M_RAS#1 RAS VDDQ CAS VDDQ
M_CAS#1 K3 C9 M_WE#1 L3 D2
<37> M_CAS#1 CAS VDDQ WE VDDQ
M_WE#1 L3 D2 SA00008DN1L E9
<37> M_WE#1 WE VDDQ VDDQ
UV7 E9 F1
VDDQ F1 M_DQS6 F3 VDDQ H2
VDDQ 2G_H@ DQSL VDDQ
M_DQS4 F3 H2 M_DQS7 C7 H9
M_DQS5 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
UV8 M_DQM6 E7 A9
M_DQM4 E7 A9 M_DQM7 D3 DML VSS B3
256M16 MT41K256M16HA-107G:E FBGA 96P DML VSS DMU VSS
M_DQM5 D3 B3 E1
SA000065D1L DMU VSS E1 VSS G8
VSS G8 M_DQS#6 G3 VSS J2
M_DQS#4 G3 VSS J2 M_DQS#7 B7 DQSL VSS J8
2G_M@ DQSL VSS DQSU VSS
M_DQS#5 B7 J8 256M16 MT41K256M16HA-107G:E FBGA 96P M1
DQSU VSS M1 VSS M9
VSS M9 SA000065D1L VSS P1
UV7 VSS P1 DRAM_RST T2 VSS P9
DRAM_RST T2 VSS P9 RESET VSS T1
<37,38> DRAM_RST RESET VSS 2G_M@ VSS
T1 L8 T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS
1
UV8 J1 B1
NC/ODT1 VSSQ
1
256M16 MT41J256M16HA-093G:E FBGA 96P J1 B1 DIS@ L1 B9

DIS@ L1 NC/ODT1 VSSQ B9 RV57 J9 NC/CS1 VSSQ D1
SA000077K1L RV56 J9 NC/CS1 VSSQ D1 243_0402_1% L9 NC/CE1 VSSQ D8
243_0402_1% L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2
NCZQ1 VSSQ E2 VSSQ E8
2G_M2@
2
VSSQ E8 VSSQ F9
VSSQ 256M16 MT41J256M16HA-093G:E FBGA 96P VSSQ
F9 G1
VSSQ G1 SA000077K1L VSSQ G9
M_CLK1 VSSQ G9 VSSQ
M_CLK#1 VSSQ 96-BALL
2G_M2@
96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C FBGA 96P C
1
H5TC2G63FFR-11C FBGA 96P @

RV54 RV55 @
40.2_0402_1% 40.2_0402_1%
DIS@ DIS@
2
1
DIS@
CV135
0.01U_0402_16V7K +1.35V_MEM_GFX +1.35V_MEM_GFX
2
U1408 side U1409 side
CV136
CV137
CV138
CV139
CV140
CV141
CV142
CV143
CV144
CV145
CV146
CV147
CV148
CV149
CV150
CV180
CV181
CV151
CV152
CV153
CV154
CV155
CV156
CV157
CV158
CV159
CV160
CV161
CV162
CV163
CV164
CV165
CV182
CV183
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
D D

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL TOPAZ_VRAM
A Upper Rev
Custom 0.3
Date:
1 2 3 4 5
5 4 3 2 1
Main Func = dGPU
Vinafix.com
D D
Power-Up/Down Sequence
1. All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/µs.
2. The external pull ups on the DDC/AUX signals (if applicable) should ramp up
before or after both VDDC and VDD_CT have ramped up.
3. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
should reach 90% before VDD_CT starts to ramp up (or vice versa).
4. For power down, reversing the ramp-up sequence is recommended.
C C
PLT_RST#
VDDR3(3.3VGS) AND
PCH GATE
PLT_RST_VGA# PERSTB GPU
PCIE_VDDC(0.95V)
GPIO50 DGPU_HOLD_RST
VDDR1(1.5VGS) GPIO54 DGPU_PWR_EN
TACH0/GPIO17 DGPU_PWROK
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
NOT DGPU_PWR_EN#
PERSTb
+3VS +3VS_VGA
REFCLK MOS 1
B B
Straps Reset +3VS +0.95VS_VGA +1.8VS +1.8VS_VGA

Regulator 2 MOS 5
Straps Valid
B+ +VGA_CORE +1.5VS +1.5VS_VGA
PWM 4 MOS 3
Global ASIC Reset
T4+16clock
CPU part
A A

TOPAZ_NOTE
0.3
5 4 3 2 1
A B C D
@ PJP1
2 1
2 1
JUMP_43X79
EMI@ PL1
+19V_VIN PR4 PSID@
FBMJ4516HS720NT_2P 33_0402_5%
@ PJPDC1 +19V_ADPIN 1 2 1 3 PSID-3 1 2 PS_ID <27>
S
8 PQ6 PSID@
GND 7 FDV301N_G 1N SOT23-3
GND
1000P_0402_50V7K
1000P_0402_50V7K
G
2
1
6
100K_0402_1%
100P_0402_50V8J
100P_0402_50V8J
6 PR8
2
5 PSID@ PR3 PSID@
5
Vinafix.com
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
PR6
4 2 1
PSID@
PSID-2 +5VALW 2.2K_0402_5%
4 3
2
3 2
2
2 1 1 2 10K_0402_1%
+3VALW
1
1
1
1 EMI@ PL4 C 1
FBMJ4516HS720NT_2P PSID-1 2 PQ5 PSID@

B
15K_0402_1%
ACES_50458-00601-001 MMST3904-7-F_SOT323
2
@ PJP2 E
3
PR9
2 1
PSID@
2 1
JUMP_43X79 PL2
BLM15AG102SN1D_2P
1
PSID 2 1
EMI@
+17.4V_BATT+ @ PJP3
2 1 +17.4V_BATT++
+17.4V_BATT+
2 1
JUMP_43X79
EMI@ PL3
FBMJ4516HS720NT_2P
1 2 +17.4V_BATT++
1
1000P_0402_50V7K
0.01U_0402_25V7K
1
PC8
1
EMI@ PC7
PD2 PD3
2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMI@
EMI@ EMI@
3
SMART
Battery: BATT_TEMP <27,42>
@ PBATT1
01.GND 1
2
1 2
02.GND 2
2 PR15 PR16
3 SYS_PRES PR20 200_0402_5% 10K_0402_1%
03.SYS_PRES 3 4 BATT_PRS 100_0402_5% 1 2 1 2
04.BATT_PRS 4 5 DAT_SMB 1 2 +3VALW
5 6 CLK_SMB 1 2
05.DAT_SMB 6 7
7 8
06.CLK_SMB 8
PR18
9 100_0402_5%
07.BATT1+ GND 10 EC_SMB_CK1 <27,42>
GND
08.BATT2+
SUYIN_200277GR008M270ZR
EC_SMB_DA1 <27,42>
Other component (37.1)
ADP_I(with selector) to H_PROCHOT# AD_I_HW1 AD_I_HW2

Delay adaptor OC H_PROCHOT# PH1 under CPU bottem side :(Carrizo) PH1 under CPU bottem side :(Carrizo-L)
support "PWC" function. 35W 0 0
<27,42> ADP_I 2ms while hybrid power CPU thermal protection at 98 +/- 3 degree C CPU thermal protection at 90 +/- 3 degree C
45W 1 0 transition +EC_VCCA
55W 0 1 H_PROCHOT# H_PROCHOT# <8,9,27,42,48,49> PR24 CZL@ +19VB
2
2
PR23 65W 1 1 CZ@
100K_0402_1% PR24
14K_0402_1%
2
1
@ PR30 17.8K/0402 @ PR34
1
2
160K_0402_1% 80.6K_0402_1%
L2N7002DW1T1G_SC88-6
<27> VCIN0_PH
PQ3A
PR27 PR38
<27> VCIN1_PH 383K_0402_1% 187K_0402_1% 1 2 2
1
@ PR36
0.01U_0402_25V7K
1
0_0402_5%
6 1
3 1
1
1
VCIN1_BATT_DROP <27>
PC15
3
1 2 3
@.1U_0402_16V7K
2
PR26
2
@ PH1
1
PC13
887K_0402_1% 2 5 VCOUT1_PH <27> 100K_0402_1%_TSM0B104F4251RZ

1
1
@ PR35
1
AD_I_HW1 <27> AD_I_HW2 <27> <27> ECAGND @ PC6 10K_0402_1%

1
2
0.1U_0402_25V6
2
PQ4A PQ4B
L2N7002DW1T1G_SC88-6 L2N7002DW1T1G_SC88-6
Adapter protection: Battery protection: Erp lot6 Circuit +19V_VIN

if battery removed, adaptor only, asserts H_PROCHOT# when adaptor is
then trigger the H_PROCHOT#, unplugged, keep low for 10ms
3.3K_1206_5%
keep @ in BOM since battery can not till SW PROCHOT# is issued by EC
1
ERP_LOT6 <27>
be removed by end user
PR5
H_PROCHOT#
+19V_VIN +3VALW PR7
2
ACIN <27,34,42>
10K_0402_1%
3 2
1
H_PROCHOT# 1M_0402_1%
+3VALW
PR28
6
10K_0402_1%
PR31 PC16
1
.1U_0402_16V7K PQ1B
1
1
PQ2A
PR37
1M_0402_1% 5
3 2
3
PC14 1 2 2 @ PR1
6
.1U_0402_16V7K
4
PQ3B
PQ2B
100K_0402_1%
@ 200K_0402_1%
2
1
1
PQ1A
BATT_TEMP 1 2 5 PR10
2
PR29
5 2
100K_0402_1%
10K_0402_1%
PR33 1M_0402_1%
4
1
1
PR2 1
@ PC5
4
1
PR32
1M_0402_1%
2
0.1U_0402_25V6
2
4 4
2
DELL CONFIDENTIAL/PROPRIETARY
PWR_DCIN/BATT CONN/OTP
0.1
LA-C142P
A B C D
A B C D
2 1 2 1
@ PR739 @ PR746 Iada=0~3.33A(65W)

1M_0402_1% 1M_0402_1%
Iada=0~2.30A(45W)
5
2 1 3 4 ADP_I = 32*Iadapter*Rsense
@ PR744 @
1M_0402_1% PQ709B
Vinafix.com @
PD706
1 1
+19VB
PQ709A
ACIN_CHG 2 1
SDMK0340L-7-F_SOD323-2
2
1
2 1 2 1
PR738 PR737
1M_0402_1% 3M_0402_5%
PR703
PQ740 PQ718 0.01_1206_1%
AON7426_DFN3X3EP8-5 AON6414AL_DFN8-5 EMI@ PL704
1 1 1 4 1 2
2 2
5 3 3 5 2 3 1UH_PCMB053T-1R0MS_7A_20%
2200P_0402_25V7K
0.1U_0402_25V7K
+19V_VIN
EMI@
EMI@
3.3K_1206_5%
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
5600P_0402_25V7K
1
PC764
@ PJP701
14
4
2
1
PR721
PC744
PC760
PC762
PC763
1 2
0_0402_5%
1 2
PC765
PC705
1
1
PC742
PR778
0_0402_5%
2_0402_5%
JUMP_43X118
1
2
PR740
@ @
2
PR772
2
@ @
6
2
@
PQ707A
2
<27> ACOFF
PC747
0.1U_0402_25V6
1
@ 2 1
0.1U_0402_25V6
0.1U_0402_25V6
2
2
4.02K_0402_1%
4.02K_0402_1%
2 2
PC745
PC746
For DT Mode
1
1
1
@ @
PR745
100_0402_1%
2
2
1
5
PR762
PR763
287K_0402_1%
AON6414AL_DFN8-5
+17.4V_BATT+
PR729
1 2
PC750 0.22U_0603_25V7K
PR773 0_0603_5%
2
1 2 4
PQ717
0.01UF_0402_25V7K
1
49.9K_0402_1%
1
PR732
0.1U_0402_25V7K
3
2
1
PC711
2
PC779
CMSRC
1
2
1 VDD_CHG
2
ASGATE
1
5
@
AON7408L_DFN8-5
100K_0402_1%
32
31
30
29
28
27
26
25
PU703 ISL95520HRZ-T_QFN32_4X4
PQ704
PR741
4S1P: CV = 17.7V CC: 1.6A
CSIN
CMSRC
OPCN
VBAT
CSIP
ASGATE
QPCP
BGATE
PC721 4
@ PR771
0_0603_5% 0.22U_0603_25V7K
ACIN_CHG 1 24 1 2 1 2
2
ACIN BOOT @ PR761 0_0603_5% PR765

PL700
ACIN 2 23 UGATE_CHG 1 2 0.01_1206_1%
3
2
1
<27,34,41> ACIN @ PR769 0_0402_5% ACOK UGATE 4.7UH_5.5A_20%_7X7X3_M +17.4V_BATT+
1
1 2 3 22 PHASE_CHG 1 2 1 4
158K_0402_1%
<27,41> EC_SMB_DA1 SDA PHASE

PR731
@ PR770 0_0402_5%
1 2 4 21 LGATE_CHG 2 3
680P_0603_50V7K 4.7_1206_5%
<27,41> EC_SMB_CK1 SCL LGATE
EMI@ PR766
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V7K
5
3
1 2 5 20 VDDP_CHG 3
AON7506_DFN33-8-5
2
<8,9,27,41,48,49> H_PROCHOT# @ PR774 0_0402_5% PROCHOT# VDOP
1
PC775
PC776
PC777
PC761
PC766
@ PR777 0_0402_5% 1 2 6 19 VDD_CHG 1 2
<27,41> ADP_I @ PR775 0_0402_5% AMON VDO
2
PQ708
1 2 7 18 PR760 4.7_0402_5%
2
<27> BATT_I BMON DCIN 4
1U_0402_16V6K
1U_0402_16V6K
2
2
8 17
BATGONE
PSYS NTC
EMI@ PC767
100K_0402_1%
CCLIM
ACLIM
COMP
PROG
AGND
CSON
CSOP
PC768
PC769
FSET
2200P_0402_25V7K
2200P_0402_25V7K
1
2
1K_0402_1%
3
2
1
2
1
PR757
1
2
PC748
PC749
PR727
33
10
11
12
13
14
15
16
3
PQ710
LMUN5113T1G PNP SOT323-3
2
0_0603_5%
@
2
PR780
2
1 2
0_0402_5%
1U_0603_25V6
+19V_VIN
2
VDD_CHG PR743 10_1206_5%
1
PR779
1 2 PD704 SDMK0340L-7-F_SOD323-2
1
2
PC757
@
1 2 BA
LMUN5236T1G NPN SOT323-3
1
PQ711
200K_0402_1%
200K_0402_1%
@ PR781 0_0603_5%
1
1
PD705 SDMK0340L-7-F_SOD323-2 PM_SLP_S5# 32 1 2 2
CCLIM
2
2
PR749
PR750
1 2
BA
ACIN
10K_0402_1%
ACLIM @ PC758 0.1U_0402_25V6
3
PROG 1 2
1
COMP PR742 2_0402_5%
2
@ PR722 PC708
5
147K_0402_1%
499_0402_1%
3.3K_1206_5% 0.1U_0402_25V6
66.5_0402_1%
2
1
PR764
4 3 2 1
560P_0402_50V7K
@ PR776 0_0402_5%
1
2
PR753
PR754
PR755
1 2
2
127K_0402_1%
95.3K_0402_1%
PQ707B
PC751
@ PR756
1
4 L2N7002DW1T1G_SC88-6 10K_0402_1% 1 2 4
1
2
2
PR751
PR752
1 2
0.015U_0402_25V7K
+3VALW
1
@ PC759 0.1U_0402_25V6
2
10P_0402_50V8J
PC752
PC753
1
BATT_TEMP <27,41>

PWR_CHARGER
0.1
LA-C142P
A B C D
A B C D E
Vinafix.com
1 1
+3VLP
PC109
1U_0603_10V6K
1 2
Output capacitor ESR need follow

@ PC102 @ PC108
100P_0402_50V8J 100P_0402_50V8J below equation to make sure feed back
1 2 1 2 loop stability
PR109 PR104 ESR=20mV*L*fsw/2V
6.49K_0402_1% 15K_0402_1%
1 2 1 2
VFB=2V VFB=2V
PR107 PR106
10K_0402_1% 10K_0402_1%
1 2 1 2
@ PJP104
1 2
1 2 +19VB_3/5V
JUMP_43X118
2 PR105 2
1
EMI@ PL102 POK need pull high, it 1 2
FBMJ4516HS720NT_2P PR108
+19VB 1 2 +19VB_3/5V will pull high on VS 100K_0402_1%
10U_0805_25V6K
CS2_3V
CS1_5V
130K_0402_1%
FB_3V
FB_5V
transfer circuit
PC112
+3VALWP
2
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
2
1
1
EMI@ PC113
EMI@ PC114
PC115
MDV1528URH-1N-PDFN33-8
5
5
PU100 21
CS2
VFB2
VREG3
VFB1
CS1
2
TP
PR115
10K_0402_5% EN_3V 6 20 EN_5V
EN2 EN1
PQ101
PQ103
@ PR114
4 POK <27> 200_0402_5% 4
2
7 19 1 2
PGOOD VCLK
LX_3V 8 18 LX_5V
1
2
3
3
2
1
PL100 PC104 PR103 SW2 SW1 PR111 PC110 PL101
2.2UH_7.8A_20%_7X7X3_M 0.1U_0603_25V7K 2.2_0603_5% TPS51225CRUKR_QFN20_3X3 2.2_0603_5% 0.1U_0603_25V7K 2.2UH_7.8A_20%_7X7X3_M
2 1 1 2 1 2 BST_3V 9 17 BST_5V 1 2 1 2 1 2 +5VALWP
+3VALWP VBST2 VBST1
UG_3V 10 16 UG_5V
DRVH2 DRVH1
1
4.7_1206_5%
680P_0402_50V7K 4.7_1206_5%
VREG5
DRVL2
DRVL1
1
EMI@ PR113
EMI@ PR112
VO1
5
5
VIN
FDMC7692S-1N-MLP
ESR=15m ohm
150U_D2_6.3VY_R15M
150U_D2_6.3VY_R15M
ESR=15m ohm
1 1
2
11
12
13
14
15
FDMC7692S-1N-MLP
2
PQ102
PQ104
+ +
PC101
PC107
4 LG_3V LG_5V 4
680P_0402_50V7K
1
1
2 2
EMI@ PC103
EMI@ PC111
3 +5VALWP 3
2
1
2
3
3
2
1
2
+19VB_3/5V
VL
1U_0603_25V6K
1U_0603_10V6K
1
1
PC105
PC106
2
Change to 4.7u for TPS51285
2
@
@ PR100 0_0402_5%
3VALWP EN_3V 1 2
TDC 4.9A
@ PR101 0_0402_5%
Peak Current 7A EN_5V 1 2
OCP current 9.1A
TYP MAX 5VALWP
H/S Rds(on):23.2mohm ,27.8mohm TDC 6A
PR102
L/S Rds(on):10.8mohm ,13.6mohm 2.2K_0402_5% Peak Current 10A
<27> EC_ON 1 2
OCP current 12A
TYP MAX
EN_3V
@ PJP100 @ PJP101
H/S Rds(on):23.2mohm , 27.8mohm
EN_5V
+3VALWP
1 2 +3VALW +5VALWP
1 2
+5VALW L/S Rds(on):10.8mohm , 13.6mohm
4 4
<27,28> VCOUT0_PH#
PAD-OPEN 4x4m PAD-OPEN 4x4m
@ PJP102 @ PJP103
4.7U_0603_6.3V6K
@ 1 2 1 2
3
PC100
PR110
@EMI@ 20K_0402_1% PAD-OPEN 4x4m PAD-OPEN 4x4m
2
PD101
2
TVNST52302AB0_SOT523-3
1
PWR_3.3VALWP/5VALWP
Place PD101 close to PU100 Size Document Number Rev
0.1
LA-C142P
A B C D E
5 4 3 2 1
Vinafix.com
D D
@ PJP204
2 1
2 1
JUMP_43X79
0.675Volt +/- 5%
EMI@ PL201
FBMJ4516HS720NT_2P
TDC 0.7A
+19VB 1 2 +19VB_1.35V @ PR200 Peak Current 1A
0_0603_5%
BST_1.35V_R 1 2 BST_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
EMI@ PC208
EMI@ PC201
PC206
PC212
UG_1.35V +0.675VSP
2
LX_1.35V
10U_0805_6.3V6K
10U_0805_6.3V6K
1
1
PC200
PC205
PC211
5
0.1U_0603_25V7K
16
17
18
19
20
2
PU200
2
VLDOIN
BOOT
VTT
PHASE
UGATE
21
PAD
PQ200
4 LG_1.35V 15 1
LGATE VTTGND
14 2
PL200 PR205 PGND VTTSNS
1
2
3
1UH_11A_20%_7X7X3_M 10.2K_0402_1%
+1.35VP 1 2 1 2 CS_1.35V 13
CS GND
3
PC204 RT8207MZQW_WQFN20_3X3
1
1U_0603_10V6K
5
EMI@ PC207 1 2 12 4 VTTREF_1.35V
FDMC7692S-1N-MLP
680P_0402_50V7K PR206 VDDP VTTREF
220U_D2_2VY_R15M
2
C 1 5.1_0603_5% C
1 2 VDD_1.35V 11 5
+5VALW VDD VDDQ +1.35VP
1
+
PC213
PQ201
PGOOD
1
1
4 PC210
TON
1
PR210 0.033U_0402_16V7K
FB
S5
S3
2
2 EMI@ PR203 PC209 2.2_0603_5%
4.7_1206_5% 1U_0603_10V6K @ PC214
10
6
220P_0402_25V8J
2
1
2
3
1 2
EN_0.675VSP
FB_1.35V
TON_1.35V
EN_1.35V
PR207
+5VALW 54.9K_0402_1%
PR208 1 2 +1.35VP
887K_0402_1%
+19VB_1.35V 1 2
1.35VP
1
TDC 4.9A
Peak Current 7A @ PR201 PR204
0_0402_5% 68.1K_0402_1%
OCP current 9.1A <26,27> SYSON
1 2
2
1
@ PC202
0.1U_0402_10V7K
H/S Rds(on):23.2mohm ,27.8mohm
2
L/S Rds(on):10.8mohm ,13.6mohm @ PR202
0_0402_5%
1 2
<26,27,45> SUSP#
1
@ PJP200
@ PC203 +1.35VP 1 2 +1.35V
0.1U_0402_10V7K 1 2
2
JUMP_43X118
B @ PJP201 B
1 2
1 2
JUMP_43X118
@ PJP203
2 1
+0.675VSP 2 1 +0.675VS
JUMP_43X79
A A
PWR_+1.35VP/0.675VSP
0.1
Date:
LA-C142P
5 4 3 2 1
A B C D
Vinafix.com
1 1
2 2
+3VALW +5VALW
PJP402 @
1 2
+1.5VSP 1 2 +1.5VS
1
JUMP_43X79
1
PC402
1
1U_0402_6.3V6K
JUMP_43X79
2
2
@ PJP401
Ultra Low Dropout 0.23V(typical) at 3A Output Current
2
PC403 PU400
1
4.7U_0603_6.3V6K G971ADJF11U_SO8
6
5 VCNTL 3
2
PR401 9 VIN VOUT 4
42.2K_0402_1% VIN VOUT +1.5VSP
1
<26,27,44> SUSP#
PR402
1 2 8
1.58K_0402_1%
EN
1
7 2
GND
POK FB PC404
1
1
0.01U_0402_25V7K
Rup
0.1U_0402_16V7K
1
PC401
PR403 PC405
2
20K_0402_1% 22UF_0805_6.3V6M
2
2
1
PR404
1.74K_0402_1%
Rdown
2
3 3
Vout=0.8V* (1+Rup/Rdown)
4 4

PWR_1.5VSP
0.1
LA-C142P
A B C D
5 4 3 2 1
Vinafix.com
D D
PJP602 @
1 2
+1.8V_ALWP 1 2 +1.8V_ALW
JUMP_43X79
@ PR601
0_0402_5%
EN_1.8V_ALWP 1 2 0.95_1.8VALW_PWREN
0.95_1.8VALW_PWREN <27,47>
0.1U_0402_16V7K
1
PC601
1
PR602
1M_0402_5%
@
2
PU600
9
1 PGND 8
FB SGND
PJP601 @ 2 7 PL601
PG EN 1UH_2.8A_30%_4X4X2_M
1 2 3 6 LX_1.8V_ALWP 1 2
+3VALW 1 2 IN LX +1.8V_ALWP
1
4 5
68P_0402_50V8J
JUMP_43X79 PGND NC
1
PC602
4.7_0603_5%
1
22UF_0805_6.3V6M
@EMI@ PR603
PC603
22UF_0805_6.3V6M
22UF_0805_6.3V6M
2
1
SY8003DFC_DFN8_2X2 PR604
20K_0402_1%
Rup
PC604
PC605
2
2
2
FB_1.8V_ALWP
1
C C
1
FB=0.6V
680P_0402_50V7K
Note:Iload(max)=3A PR605
@EMI@ PC606
10K_0402_1%
Rdown
2
B B
A A

PWR_+1.8V_ALWP
C 1.0
LA-C142P
5 4 3 2 1
5 4 3 2 1
@ PJP303
2 1
2 1
JUMP_43X79
EMI@ PL301
FBMJ4516HS720NT_2P
+19VB_VDDP_ALWP 1 2
+19VB
Vinafix.com
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
1
1
PC302
EMI@ PC303
PC304
PC308
+3VS
2
D D
@EMI@
TDC=9.3A
5
1
Peak Current=13.3A @ PJP301
AON6552_DFN5X6-8-5
@ +0.95VALWP 1 2 +0.95VALW
OCP=16A PR302 1 2
100K_0402_5% JUMP_43X118
4 @ PJP302
PQ301
2
1 2
@ PR303 PC305 1 2
PU300 0_0603_5% 0.1U_0603_25V7K JUMP_43X118
PR304 1 10 1
BST_VDDP_ALWP 2 1 2
3
2
1
42.2K_0402_1% PGOOD VBST
@ PR301 1 2 TRIP_VDDP_ALWP 2 9 UG_VDDP_ALWP PL302
0_0402_5% TRIP DRVH 1UH_PCMB104T-1R0MH_18A_20%
1 2 EN_VDDP_ALWP3 8 LX_VDDP_ALWP 1 2
<27,46> 0.95_1.8VALW_PWREN EN SW +0.95VALWP
FB_VDDP_ALWP4 7
VFB V5IN +5VALW
1
0.1U_0402_16V7K
RF_VDDP_ALWP5 6 LG_VDDP_ALWP
AON6554_DFN5X6-8-5
TST DRVL
220U_D2_2VY_R15M
220U_D2_2VY_R15M
@ PC301 PR305 @EMI@ 1 1
1
11 4.7_1206_5%
TP
1
+ +
PC307
PC310
2
2
PR306 S IC RT8237EZQW(2) WDFN 10P PC306 4
PQ302
470K_0402_1% 1U_0603_10V6K
1
PC309 @EMI@ 2 2
2
680P_0402_50V7K
3
2
1
2
PR307
3.48K_0402_1%
1 2
C C
1
PR308
10K_0402_1%
2
B B
A A

P45-PWR_VDDP_ALWP(+0.95V)
C 1.0
LA-C142P
5 4 3 2 1
5 4 3 2 1
@ PJP1001
2 1
2 1
JUMP_43X79
+19VB_APU EMI@ PL1001

FBMJ4516HS720NT_2P
1 2
+19VB
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
1 1 1
S ELE CAP 33U 25V
S ELE CAP 33U 25V
S ELE CAP 33U 25V

0.1U_0402_25V6K
+ + +
PC1000
PC1001
PC1005
Vinafix.com
1
PC1002
PC1003
PR1012=3.65K, PR1003=1.5K and
1
PC1004
@EMI@ PC1071
@EMI@ PC1072
PR1000
330P_0402_50V7K 2K_0402_1% PR1013=301 to set loadline -4mV/A 2 2 2
2
1 2 1 2 @ @ @
2
PR1002 UG_NB
<8> APU_VDDNB_SEN @ PR1005
D PR1003 PR1004 PC1006 D
10_0402_5% 1.5K_0402_1% 137K_0402_1% 390P_0402_50V7K 41.2K_0402_1%
SH000011H00 (DCR:0.98m± 5%)
1
1 2 1 2 1 2 1 2 1 2
+APU_CORE_NB
D1
G1
PL1002
@ PR1006 PC1007 PC1008 0.22UH_24A_20%_7X7X4_MOLDING
0_0402_5% 1000P_0402_50V7K 220P_0402_50V8J LX_NB 7 LX_NB 1 4
VSUMP_NB
1 2 1 2 1
PR1007
2 1 2
@ PR1008 PC1009
D2/S1
2 3
+APU_CORE_NB
1
PC1010 301_0402_1% 0_0603_5% 0.22U_0603_25V7K PQ1001 @EMI@
2.61K_0402_1%
G2
S2
S2
S2
1
0.01U_0402_50V7K BST_NB 1 2 1 2 AON6970_DFN5X6D-8-7 PR1010

10K_0402_5%_ERTJ0ER103J
PR1009
4.7_1206_5%
0.022U_0402_25V7K
6
1 2
0.1U_0603_16V7K
680P_0603_50V7K
11K_0402_1%
PC1011
1 2
1
PR1012
1 2
PC1012 3.65K_0603_1%
PR1011
@EMI@ VSUMP_NB 1 2
LG_NB PC1013
2
2
PR1013 PR1014
2
PH1000
301_0402_1% 1_0402_1%
PR1013 set 301 ohm to OCP 21.25A VSUMN_NB 1 2
2
VSUMN_NB 1 2
1
@ PR1015 @PC1015
@PC1015
PH1000 near APU_CORE_NB choke 100_0402_1% 220P_0402_50V7K LG_NB
APU_CORE_NB
PC1014 1 2 1 2
2
0.1U_0603_50V7K
LX_NB TDC 12A
UG_NB Peak Current 17A
PR1086
150K_0402_1% 13.3K_0402_1%
BST_NB OCP current 21.25A
PR1016
1 2 1 2 Load line -4mV/A
FSW=300kHz
41
40
39
38
37
36
35
34
33
32
31
1 2 PU1001
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
@ PH1001 470K_0402_5%_TSM0B474J4702RE
1 30
PH1001 near APU_CORE_NB H/S mos NTC_NB BOOT2
1 2 IMON_NB 2 29
PC1018 1000P_0402_50V7K IMON_NB UGATE2
C 3 28 C
PR1018 133K_0402_1% <8> APU_SVC SVC PHASE2
1 2
4 27 +5VS
<8,9,27,41,42,49> H_PROCHOT# VR_HOT_L LGATE2
@ PR1021 100K_0402_1%
+3VS
1 2 5 26
<8> APU_SVD SVD VDDP
ISL62771HRTZ-T_TQFN40_5X5 PR1026
1@ PR1023 2 0_0402_5% VDDIO_APU6 25 1 2
+1.8VS VDDIO VDD 1_0603_5%
1U_0603_10V6K
@PR1028
@PR1028
1
0_0402_5% @ PR1085 7 24 LG1_APU

<8> APU_SVT SVT LGATE1
1
1 2 0_0402_5%
1U_0603_10V6K
+1.5VS
PC1064 1 2 8
ENABLE_APU 23 LX1_APU
<27,49> VR_ON
2
ENABLE PHASE1
PC1063
PC1055
0.1U_0402_25V6K
2
VDDIO pin: 1.8VS for DDRII voltage level<8,9,49> APU_PWRGD 9 22 UG1_APU
PWROK UGATE1
1.5VS for DDRIII voltage level
1 2 10
IMON_APU 21 BST1_APU
IMON BOOT1 +3VS
PR1076
PGOOD
133K_0402_1%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
NTC
RTN
1 2 PC1062 FB
1
1000P_0402_50V7K
PR1087 PR1080
11
12
13
14
15
16
17
18
19
150K_0402_1% 13.3K_0402_1% 20 PR1070

1 2 1 2 100K_0402_5%
2
PH1002 near APU_CORE H/S mos 1 2 +5VS
VGATE <9,26,27,49>
2
@ PH1002
APU_core
10K_0402_1%
TDC 22A
PR1081
470K_0402_5%_TSM0B474J4702RE
Peak Current 35A

1
OCP current 42A

Load line -2.1mV/A
PC1068
PC1060 PR1073 150P_0402_50V8J @ PR1078
FSW=300kHz
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1%
VSUM+_APU 1 2 1 2 1 2 1 2
330P_0402_50V7K
+19VB_APU
@ PC1059
2.61K_0402_1%
1
B PR1047 PR1077 PC1057 B

10K_0402_5%_ERTJ0ER103J
0.022U_0402_25V7K
0.1U_0603_16V7K
PR1079
1.62K_0402_1% 137K_0402_1% 390P_0402_50V7K

11K_0402_1%
1
1 2 1 2 1 2
PC1066
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2
1
1
PR1071
PC1053
0.1U_0402_25V6K
1 2
PR1065 PC1037
2
1
PC1070
PC1039
PC1067
@EMI@ PC1056
EMI@ PC1069
2K_0402_1% 330P_0402_50V7K
2
PR1084=3.65K, PR1047=1.62K and 1 2 1 2

PH1003 near APU_CORE_NB choke
AON6552_DFN5X6-8-5
PH1003
PR1066=619 to set loadline -2.1mV/A
2
PQ1007
PR1066 PR1051
2
619_0402_1% 10_0402_5% UG1_APU 4

VSUM-_APU 1 2 1 2
+APU_CORE
@ PC1061 @ PR1075 SH000011H00 (DCR:0.98m± 5%)
1
@ PR1072 820P_0402_50V7K 0_0402_5%
3
2
1
PC1065 100_0402_1% 1 2 PL1004
0.1U_0603_50V7K 1 2 1 2 APU_VDD_SEN <8> 0.22UH_24A_20%_7X7X4_MOLDING
2
LX1_APU 1 4
PR1066 set 619 ohm to OCP 42A 1 2 @ PR1082 PC1038 2 3
+APU_CORE
APU_VDD_RUN_FB_L <8>
0.01U_0402_50V7K
PR1067 0_0603_5% 0.22U_0603_25V7K @EMI@
1
0_0402_5% 10_0402_5% 1
BST1_APU 2 1 2 PR1074
1
PC1058
@ PR1069 1 2 4.7_1206_5% PR1084

3.65K_0603_1%
5
VSUM+_APU1 2
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
2
@EMI@
1 2
PC1054
PQ1008
PQ1009
680P_0603_50V7K PR1068
1_0402_1%
LG1_APU 4 4 1
VSUM-_APU 2
2
3
2
1
3
2
1
A A

PWR_APU_CORE/APU_CORE_NB
Custom 0.1
LA-C142P
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
10K_0402_1%
10K_0402_1%
1
1
+5VALW
GFX@ PR502
GFX@ PR503
2
2
GFX@
VDDGFX
41
40
39
38
37
36
35
34
33
32
31
PU500
TDC 22A
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
Peak Current 35A
GFX@ PR501 100K_0402_1%
1 2 1
NTC_NB BOOT2
30 OCP current 42A
GFX@ PR504 100K_0402_1%
1 2 2 29 Load line -2.1mV/A
IMON_NB UGATE2 @ PJP501
3 28 2 1 FSW=300kHz
<8> GFX_SVC SVC PHASE2 2 1
4 27 +5VS JUMP_43X79
<8,9,27,41,42,48> H_PROCHOT# VR_HOT_L LGATE2
@ PR505 100K_0402_1%
1 2 5 26
+3VS <8> GFX_SVD SVD VDDP
@ PR506 0_0402_5% ISL62771HRTZ-T_TQFN40_5X5 GFX@ PR507
GFX@PR507 GFX@_EMI@ PL501
+1.8VS 1 2 VDDIO_GFX6 25 1 2 FBMJ4516HS720NT_2P
VDDIO VDD 1_0603_5% 1 2
1U_0603_10V6K
@PR508
@PR508 +19VB
1
0_0402_5% @ PR509 7 24 LG1_GFX
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
<8> GFX_SVT SVT LGATE1
1
C 1 2 C
0_0402_5%
0.1U_0402_25V6
1U_0603_10V6K
0.1U_0402_25V6
+1.5VS
GFX@ PC501 1 2 8 23
GFX@ PC503
EN_GFX ENABLE_GFX LX1_GFX
2
ENABLE PHASE1
GFX@ PC502
0.1U_0402_25V6K
1
5
GFX@_EMI@ PC508
9 22
@EMI@ PC522
PC504
PC505
PC506
@EMI@ PC507
UG1_GFX
<8,9,48> APU_PWRGD PWROK UGATE1
AON6552_DFN5X6-8-5
1 2 IMON_GFX 10 21 BST1_GFX
2
2
2
GFX@ PR510 IMON BOOT1 +3VS
PGOOD
GFX@ PQ501
133K_0402_1%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
UG1_GFX 4
NTC
RTN
1 2 FB
1
1000P_0402_50V7K
GFX@ PC509 GFX@ PR512 GFX@ PR513 SH000011H00 (DCR:0.98m± 5%)
11
12
13
14
15
16
17
18
19
150K_0402_1% 13.3K_0402_1% 20 @ PR511
3
2
1
1 2 1 2 100K_0402_1% GFX@ PL502
0.22UH_24A_20%_7X7X4_MOLDING
2
LX1_GFX 1 4
PH501 near VDDGFX H/S mos 1 2 VGATE <9,26,27,48> @ PR514 GFX@PC510
GFX@ PC510 2 3
+APU_CORE_GFX
@ PH501 +5VS
0_0603_5% 0.22U_0603_25V7K @EMI@
2
1
470K_0402_5%_TSM0B474J4702RE GFX_PWRGD <9,26,27,48> BST1_GFX 1 2 1 2 PR516
4.7_1206_5%
10K_0402_1%
GFX@ PR515
GFX@PR517
GFX@ PR517
5
3.65K_0603_1%
@EMI@ VSUM+_GFX1 2
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
1
1 2
PC511
680P_0603_50V7K GFX@PR518
GFX@ PR518
GFX@ PQ502
GFX@ PQ503
1_0402_1%
GFX@ PC513 LG1_GFX 4 4 1
VSUM-_GFX 2
2
GFX@ PC512 GFX@ PR519 150P_0402_50V8J @ PR520
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1%
VSUM+_GFX 1 2 1 2 1 2 1 2
330P_0402_50V7K
3
2
1
3
2
1
@ PC514
GFX@ GFX@
2.61K_0402_1%
1
GFX@ PR521 PR522 PC515

10K_0402_5%_ERTJ0ER103J
0.1U_0603_16V7K
GFX@ PR523
0.022U_0402_25V7K
1.62K_0402_1% 137K_0402_1% 390P_0402_50V7K

11K_0402_1%
1
1 2 1 2 1 2
2
1
1
GFX@ PR524
GFX@ PC517
GFX@ PC516
GFX@ GFX@
1 2
PR525 PC518
2
2K_0402_1% 330P_0402_50V
2
1 2 1 2
PH502 near VDDGFX choke
GFX@ PH502
B B
GFX@ PR526 GFX@ PR527
2
619_0402_1% 10_0402_5%
VSUM-_GFX 1 2 1 2 +APU_CORE_GFX
@ PC520 @ PR529
1
@ PR528 820P_0402_50V7K 0_0402_5%

PC519 GFX@ 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 APU_COREGFX_SEN_H <8>
2
1 2
APU_COREGFX_SEN_L <8>
0.01U_0402_50V7K
GFX@ PR531
@ PR530
0_0402_5% 10_0402_5%
1
GFX@ PC521
1 2
2
GFX@ PR532
47K_0402_1%
1 2
<27,48> VR_ON
EN_GFX
GFX@ PR533
1
10K_0402_1% D
1 2 2 GFX@
<9> GFX_VR_ON
G PQ504
2N7002W-T/R7_SOT323-3
1000P_0402_50V7K
S
3
1
PC523
A A
PWR_VDDGFX
Custom 0.1
LA-C142P
5 4 3 2 1
A B C D
+3VALW
1
PJP801
1
JUMP_43X79
2
@
GFX@
2
Vinafix.com 1
2
PU800
VIN NC
8
7
+3VALW
GND NC
1
1 GFX@ 1
1
GFX@ PC801 3 6 PC802
4.7U_0805_6.3V6K GFX@ PR802 VREF VCNTL
2
3.24K_0402_1% 4 5 1U_0603_10V6K
VOUT NC
9
2
TP
G2992F1U_SO8
@ PR801
.1U_0402_16V7K
VDDCR_FCH_S5
1
0_0402_5% D
GFX@ PC803
1 2 2
<27> 0.775PW_EN
1K_0402_1%
1
G GFX@ GFX@
2
1
S PR803 PC804
3
@ PC805 PQ801 10U_0603_6.3V6M
2
.1U_0402_16V7K GFX@
2
2N7002W-T/R7_SOT323-3
PJP802
VDDCR_FCH_S5
2 1 +0.775VALW
2 1
@ JUMP_43X79
2 2
3 3
4 4

PWR_1.5V/VDDCR_FCH_S5
0.1
LA-C142P
A B C D
5 4 3 2 1
EN pin don't floating

If have pull down resistor at HW side, pls delete PR1403
Vinafix.com VGA@ PR1402

47K_0402_5%
D EN_1.35VGPU 1 2 D
PXS_PWREN <9,26,52,53>
1
VGA@
VGA@ PC1402 @ PJP1401
1M_0402_1% 1 2
0.22U_0402_10V6K +1.35VGPUP +1.35V_MEM_GFX
2
PR1403 1 2
JUMP_43X118
2
@ PJP1403
2 1
2 1
JUMP_43X79 @EMI@ PR1404 @EMI@ PC1403
4.7_1206_5% 680P_0603_50V7K
VGA@_EMI@ PL1401 VGA@ 1 2SNB_1.35VGPU
1 2
FBMJ4516HS720NT_2P PU1400 VGA@
+19VB 1 2 +19VB_1.35VGPU 8
IN EN
1 @ PR1405 PC1404
0_0603_5% 0.1U_0603_25V7K
10U_0805_25V6K
10U_0805_25V6K
6 1
BST_1.35VGPU 2 1 2 VGA@ PL1402
2200P_0402_50V7K
0.1U_0402_25V6
BS
1
0.68UH_7.9A_20%_5X5X3_M
@EMI@ PC1405
PC1406
VGA@ PC1407
LDO_3V_1.35VGPU 9 10 LX_1.35VGPU 1 2
+1.35VGPUP
VGA@_EMI@ PC1401
GND LX
PC1408 VGA@
24.9K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
1
1
@
330P_0402_50V7K
1
1
4 FB_1.35VGPU
VGA@ PR1406
@ PR1401 FB @ PJP1402
Rup
VGA@ PC1409
VGA@ PC1410
VGA@ PC1411
@ PC1412
0_0402_5% ILMT_1.35VGPU 3 7 2 1
+3VALW
2
ILMT BYP 2 1
4.7U_0603_6.3V6K
2
2
ILMT_1.35VGPU
+3VS 1 2 PGOOD_1.35VGPU 2
PG LDO
5LDO_3V_1.35VGPU JUMP_43X39
1
@ PR1407
VGA@ PC1414
4.7U_0603_6.3V6K
1
1
C 10K_0402_5% SYX198DQNC_QFN10_3X3 C
VGA@ PC1413
1K_0402_1%
FB = 0.6V
PR1409
2
VGA@ PR1408
VGA@
0_0402_5%
2
2
1
Pin 7 BYP is for CS. PR1410 VGA@
The current limit is set to 8A, 12A or 16A when this pin Common NB can delete +3VALW and PC1414 Rdown 20K_0402_1%
is pull low, floating or pull high
2
VFB=0.6V
Vout=1.35V
+1.35VGPU
B TDC 3.5A B
Peak Current 5A
OCP current 8A
A A

PWR_+1.35VGPU
0.1
LA-C142P
5 4 3 2 1
A B C D
Vinafix.com
1 1
+3VALW +5VALW
PJP1202 @
1 2
+1.8VGSP 1 2 +1.8VGS
1
JUMP_43X79
1
VGA@ PC1202
1
1U_0402_6.3V6K
JUMP_43X79
2
2
@ PJP1201
Ultra Low Dropout 0.23V(typical) at 3A Output Current
2
VGA@ PC1203 VGA@ PU1200
1
4.7U_0603_6.3V6K G971ADJF11U_SO8
6
5 VCNTL 3
2
VGA@ PR1201 9 VIN VOUT 4
42.2K_0402_1% VIN VOUT +1.8VGSP
1
<9,26,51,53> PXS_PWREN 1 2 8
VGA@ PR1202
2.21K_0402_1%
EN
1
7 2
GND
POK FB VGA@ PC1204
1
1
0.01U_0402_25V7K
2.2U_0402_10V6M
Rup
1
PC1201
VGA@ PR1203 VGA@ PC1205
2
20K_0402_1% 22UF_0805_6.3V6M
2
2
2
1
2 2
VGA@ VGA@ PR1204

1.74K_0402_1%
Rdown
2
3 3
4 4

PWR_1.8VGS
0.1
LA-C142P
A B C D
5 4 3 2 1
+19VB_GPU @ PJP1101
2 1
2 1
JUMP_43X79
VGA@_EMI@ PL1101
FBMJ4516HS720NT_2P
1 2
+19VB
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
Vinafix.com
0.1U_0402_25V6K
1
5
VGA@_EMI@ PC1107
VGA@ PC1103
VGA@ PC1104
VGA@ PC1105
@EMI@ PC1106
AON6552_DFN5X6-8-5
D D
2
2
2
VGA@ PQ1101
UG2_VGA 4
SH000011H00 (DCR:0.98m± 5%)
3
2
1
10K_0402_1% VGA@
10K_0402_1% VGA@
PL1102
0.22UH_24A_20%_7X7X4_MOLDING
LX2_VGA 1 4
@ PR1103
VGA@
PC1108 VGA@ PR1104 2 3
+VGA_CORE
0_0603_5% 0.22U_0603_25V7K @EMI@ 10K_0402_1%
1
BST2_VGA 1 2 1 2 PR1107 ISEN2_VGA1 2
1
4.7_1206_5%
VGA@ PR1108
5
3.65K_0603_1%
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
+5VALW 1 2
PR1105
PR1106
@EMI@ VSUM+_VGA
1 2
PC1109
VGA@ PQ1102
VGA@ PQ1103
680P_0603_50V7K VGA@ PR1110
1_0402_1%
LG2_VGA 4 4 1
VSUM-_VGA 2
2
VGA@
41
40
39
38
37
36
35
34
33
32
31
PU1100
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
3
2
1
3
2
1
VGA_CORE
VGA@ PR1101 100K_0402_1% TDC 34A
1 2 1 30 BST2_VGA
VGA@ PR1111 100K_0402_1% NTC_NB BOOT2 Peak Current 51A
1 2 2 29 UG2_VGA
IMON_NB UGATE2 OCP current 61.2A
3 28 LX2_VGA
<34> SVI2_SVC SVC PHASE2 Load line XXmV/A (no need)
+5VALW
<34> OCP_L
4
VR_HOT_L LGATE2
27 LG2_VGA FSW=300kHz
@ PR1112 100K_0402_1%
1 2 5 26
+3VS <34> SVI2_SVD SVD VDDP +19VB_GPU
ISL62771HRTZ-T_TQFN40_5X5 VGA@ PR1114
+1.8VGS 1@ PR1113 2 0_0402_5% 6
VDDIO_VGA 25 1 2
VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
VGA@ PR1115 0_0402_5% @ PR1116 7 24 LG1_VGA
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
<34> SVI2_SVT SVT LGATE1
1
C 1 2 C
0_0402_5%
0.1U_0402_25V6
1U_0603_10V6K
+3VGS
PC1101 1 2 8 23
VGA@ PC1111
ENABLE_VGA LX1_VGA
<9,26,51,52> PXS_PWREN
2
ENABLE PHASE1
VGA@ PC1110
0.1U_0402_25V6K
1
5
VGA@_EMI@ PC1116
PWRGD_VGA 9 22 UG1_VGA
VGA@ PC1112
VGA@ PC1113
VGA@ PC1114
@EMI@ PC1115
VGA@
PWROK UGATE1
AON6552_DFN5X6-8-5
1 2 IMON_VGA 10 21 BST1_VGA
2
2
2
IMON BOOT1 +3VS
PR1117 VGA@
PGOOD
VGA@ PQ1104
133K_0402_1%
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
UG1_VGA 4
NTC
RTN
1 2 VGA@ FB
1
1000P_0402_50V7K VGA@ VGA@
PC1117 PR1120 PR1121
@ PR1122 SH000011H00 (DCR:0.98m± 5%)
11
12
13
14
15
16
17
18
19
150K_0402_1% 13.3K_0402_1% 20 @ PR1119 0_0402_5%
3
2
1
1 2 1 2 100K_0402_1% 1 2 PL1103
DGPU_PWROK <27> 0.22UH_24A_20%_7X7X4_MOLDING
2
LX1_VGA 1 4
PH1101 near GPU_CORE H/S mos 1 2 PWRGD_VGA <9> @ PR1123
VGA@
PC1118 VGA@ PR1124 2 3
+VGA_CORE
@ PH1101 0_0603_5% 0.22U_0603_25V7K @EMI@ 10K_0402_1%
1
470K_0402_5%_TSM0B474J4702RE PC1119 VGA@ BST1_VGA 1 2 1 2 PR1125 ISEN1_VGA1 2
0.22U_0402_10V6K 4.7_1206_5%
1 2 ISEN2_VGA VGA@ PR1126
5
3.65K_0603_1%
AON6554_DFN5X6-8-5
AON6554_DFN5X6-8-5
PC1120 VGA@ @EMI@ VSUM+_VGA1 2
1 2
0.22U_0402_10V6K PC1121
1 2
VGA@ PQ1105
VGA@ PQ1106
VSUM-_VGA ISEN1_VGA 680P_0603_50V7K VGA@ PR1128
1_0402_1%
VGA@ VGA@ VGA@ PC1123 LG1_VGA 4 4 1
VSUM-_VGA 2
2
PC1122 PR1129 270P_0402_50V7K @ PR1130
1000P_0402_50V7K 301_0402_1% 32.4K_0402_1%
VSUM+_VGA 1 2 1 2 1 2 1 2
PR1131 VGA@
330P_0402_50V7K
3
2
1
3
2
1
@ PC1124
VGA@ VGA@
2.61K_0402_1%
VGA@ PR1133
1
PR1134 PC1127
10K_0402_5%_ERTJ0ER103J
0.033U_0402_16V7K
0.15U_0603_16V7K
1.47K_0402_1% 137K_0402_1% 390P_0402_50V7K

11K_0402_1%
1
1 2 1 2 1 2
2
1
1
VGA@ PR1132
VGA@ PC1125
VGA@ PC1126
VGA@ VGA@
1 2
PR1135 PC1128
2
2K_0402_1% 330P_0402_50V
2
1 2 1 2
PH1102 near GPU_CORE choke
VGA@
PH1102
B VGA@ B
PR1136
2
562_0402_1%
VSUM-_VGA 1 2
@ PC1130 @ PR1138
1
VGA@ @ PR1137 820P_0402_50V7K 0_0402_5%

PC1129 100_0402_1% 1 2
0.1U_0603_50V7K 1 2 1 2 VCCSENSE_VGA <34>
2
1 2
VSSSENSE_VGA <34>
0.01U_0402_50V7K
@ PR1139
0_0402_5%
1
VGA@ PC1131
2
A A
PWR_VGA_CORE
Custom 0.1
LA-C142P
5 4 3 2 1
5 4 3 2 1
APU_CORE
+APU_CORE_NB APU_CORE_NB +VDDGFX +VDDGFX
+APU_CORE 330uF*3+1(reserve)
330uF*2 330uF*3
+APU_CORE +APU_CORE_NB +APU_CORE_GFX
Vinafix.com
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
D 1 1 1 1 1 1 1 1 1 D
+ + + + + + + + +
PC953
PC954
PC955
PC956
PC959
PC960
GFX@ PC967
GFX@ PC969
GFX@ PC968
2@ 2 2 2 2 2 2 2 2
C C
B B
+VGA_CORE
VGA@ 330U_D2_2V_Y
VGA@ 330U_D2_2V_Y
VGA@ 330U_D2_2V_Y
VGA@ 330U_D2_2V_Y
1 1 1 1
PC836
PC837
PC838
PC839
+ + + +
2 2 2 2
A A
PWR_PROCESSOR DECOUPLING
0.1
LA-C142P
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D Power block D
APU OTP
Page 41
Turn Off
+19VB
Input +3VALWP: TDC:4.9A
DC IN Switch Page 42 EC_ON
+5VALWP: TDC:6A
TPS51285BRUKR Page 43
C +3VALW +1.8V_ALWP: TDC:2A 0.95_1.8VALW_PWREN C
SY8003DFC
Page 46
CHARGER (HPB)
CV:17.7V CC:1.54A (4S1P) - 40Wh
CV:17.7V CC:1.76A (4S1P) - 47Wh +3VALW +1.5VSP: TDC:0.3A SUSP#
ISL95520HRZ-T
G971ADJF11U
Page 42 Page 45
+3VALW +1.8VGSP: TDC:0.5A PXS_PWREN

Battery
G971ADJF11U
Page 52
+3VALW +VDDCR_FCH_S5: TDC:0.2A EC_ON

+VGA_CORE G2992F1U
PXS_PWREN
B TDC: 34A Page 50 B
ISL62771HRTZ-T
Page 53
+VDDP_ALWP: TDC:9.3A 0.95_1.8VALW_PWREN

RT8237EZQW Page 47
+APU_CORE
VR_ON
TDC: 22A +1.35VP/+0.675VSP: TDC:4.9A/0.7A SYSON
ISL62771HRTZ-T RT8207MZQW
Page 48
Page 44
+1.35VGPUP: TDC:3.5A PXS_PWREN

+APU_CORE_NB SYX198DQNC
VR_ON
TDC: 12A Page 51
ISL62771HRTZ-T
A Page 48 A
+VDDGFX
GFX_VR_ON Security Classification Compal Secret Data Compal Electronics, Inc.
TDC: 22A Issued Date 2014/01/20 Deciphered Date 2015/01/19 Title
ISL62771HRTZ-T THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
PWR_POWER BLOCK DIAGRAM
Document Number Rev
Page 49 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
LA-C142P
5 4 3 2 1
5 4 3 2 1
V ersion Change L ist ( P. I. R . L ist )

Vinafix.com Page 1
R equest
D
Item P age# Title D ate Issue D escription Solution D escription R ev. D
O w ner
1 45 +1.5VSP 14/12/04 Morris design change change PR401 from 47K to 42.2K 0.2
change PR403 from 47K to 20K
2 52 1.8VGSP 14/12/04 Morris revise sequence from EE requirement change PR1201 from 47K to 42.2K 0.2
add PC1201 2.2uF
3 51 +1.35VGPUP 14/12/04 Morris revise sequence from EE requirement change PR1402 from 0 to 47K 0.2
4 42 CHARGER 14/12/04 Morris from EMI requirement add PC765 0.1uF 0.2
add PR766 4.7
add PC767 680P
5 43 +3.3VALWP/+5VALWP 14/12/04 Morris from EMI requirement change PR103 and PR111 from 0 to 2.2 0.2
change PL102 from SH00000Z200 to SM010009C80
6 42 CHARGER 14/12/04 Morris improve S5 power consumption delete PR780 0.2

add PQ710,PQ711,PR781
C C
7 41 DCIN/BATT CONN/OTP 14/12/04 Morris improve PWC function change PQ4 from SB000009Q80 to SB00000PV00 0.2
add PR38 187K
8 41 DCIN/BATT CONN/OTP 15/01/14 Morris adjust OTP setting point from thermal requirement change PR24 from 14K to 17.8K only for CZL 0.3
9 41 DCIN/BATT CONN/OTP 15/01/14 Morris from ESD requirement change PR15 from 100 to 200 1.0
B B
A A

PWR-PIR
1.0
LA-C142P
5 4 3 2 1

Dell Inspiron 17 5755 Compal LA-C142P r1.0 AMD

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Dell Inspiron 17 5755 Compal LA-C142P r1.0 AMD

Uploaded by

Copyright:

Available Formats

5 4 3 2 1

PROJECT NAME : Tulip 14",15", 17" / Van Gogh 14", 15"

Dell / Compal Confidential

Security Classification Compal Secret Data Compal Electronics, Inc.

VRAM 256M*16 FCBGA631 PEG 2.0 x4

USB 3.0 Port 1

Port 0 Card Reader

Port 3 I2C I2C

SATA ODD Conn. Port 1 SATA3.0

SPI ROM SPI

Int.KBD ENE KBC PS/2

Security Classification Compal Secret Data Compal Electronics, Inc.

Q2516 ,Q2507 Q135, Q12513 AO3416L

10d PLT_RST# R662

Security Classification Compal Secret Data Compal Electronics, Inc.

Board ID Table for AD channel

Lane 5 PEG (AMD)EXO UL

Security Classification Compal Secret Data Compal Electronics, Inc.

SMBus Block Diagram R677 2.2K

Carrizo R686 4.7K

R680 0, CZL@ +3VS

R16 DIS@ RV5 45.3K

Security Classification Compal Secret Data Compal Electronics, Inc.

Main Func = CPU

U10 P_GPP_RXP[0] P_GPP_TXP[0] R1 PCIE_ATX_DRX_P0 C224 1 2 .1U_0402_16V7K

PEG_GTX_C_HRX_P0 P10 P_GFX_RXP[0] P_GFX_TXP[0] M2 PEG_HTX_GRX_P0 C185 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_P0

PEG_GTX_C_HRX_P1 N6 P_GFX_RXP[1] P_GFX_TXP[1] L1 PEG_HTX_GRX_P1 C215 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_P1

PEG_GTX_C_HRX_P2 N9 P_GFX_RXP[2] P_GFX_TXP[2] L4 PEG_HTX_GRX_P2 C223 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_P2

PEG_GTX_C_HRX_P3 L7 P_GFX_RXP[3] P_GFX_TXP[3] J1 PEG_HTX_GRX_P3 C196 1 2 DIS@ .1U_0402_16V7K PEG_HTX_C_GRX_P3

L10 P_GFX_RXP[4] P_GFX_TXP[4] J4

PEG_GTX_C_HRX_P[3..0] K9 P_GFX_RXP[6] P_GFX_TXP[6] G1 PEG_HTX_C_GRX_P[3..0]

FP4 REV 0.93

UC1 CZL_2P2G@ UC1 CZ_2P1G@

S IC CARRIZO-L AM7310JBY44JBA 2G BGA S IC A10-8700P AM870PAAY43KA 1.8G BGA 968P APU

CARRIZO-L AM7210JBY44JB 1.8G BGA 968P

S IC CARRIZO-L EM7110JBY44JBA 1.8G BGA

S IC CARRIZO-L EM7010JCY23JBA 1.5G BGA

Main Func = CPU

MA_DATA[16] G22 MB_DATA[16] E30 DDRAB_SDQ16

B19 AD29 +VREF_DQ APU_MAB_VREFDQ A19 AF32 MEM_MAB_ZVDDIO 1 2

FP4_BGA968 FP4_BGA968 Place them close to APU within 1"

RZ1049 1 CZ@ 2 0_0402_5% APU_MAB_VREFDQ

Carrizo: Carrizo-L(CHANNEL B ONLY):

EVENT# pull high +1.35V 0.675V reference voltage ‧

A R5 uDIMM and SO-DIMM/DRAM down uDIMM and SO-DIMM/DRAM down A

DP2: VGA Translator

TEST17 C11 APU_TEST17 Carrizo-L: VDD_33 level at the APU

TEST28_L B13 APU_TEST28_L

TEST37 A17 APU_TEST37 1K_0804_8P4R_5%

+1.8VS <9> APU_RST# 1 2 300_0402_5% APU_RST# D15 1

RP25 EC_SMB_CK2 3 4 APU_SIC 0_0402_5%

3 8 1 APU_SID Q79A CZ@ FP4 REV 0.93 3

7 2 APU_ALERT# DMN63D8LDW_SOT363-6 FP4_BGA968

Q79B CZ@ APU_TRST#_R

R159 R51 1 2 15 16 APU_DBREQ#_R 1 HDT@ 2 APU_DBREQ# APU_TEST19 3 6

U63 @ 19 20 APU_TEST18 HDT@

4.7K_0402_5% SAMTE_ASP-136446-07-B @ C141

U62 @ NL17SZ07DFT2G_SC70-5 0.01U_0402_16V7K

SA00004BV00 Issued Date 2014/06/10 2015/06/30 Title

Main Func = CPU

<19,20,27> PLT_RST# Vinafix.com

AY15 As close as possible to UC1D

+3.3VS <27> KB_RST# ESPI_RESET_L/KBRST_L/AGPIO129

AN8 IR_RX1/AGPIO15 AGPIO9 AK5