http://en.verysource.com/code/4535740_1/bldcmmain.c.

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/ / ************************************************ ******** / / / / / / / / / / / / / / /
1 / / / ** Mc ch : . S dng PWM kim sot BLDCM ********** / / / / /
. 2 / / / *** d liu : 2008/08/20 *********** / / /
. 3 / / / *** tc gi : XieZu Su ******** / / / / / /
4 . # Bao gm <iom48v.h>
5 . # Bao gm <macros.h>
6 . # Xc nh speed0 0x20
7.
8 . Port_init Void (void)
9{
. 10 PORTB = 0x00; / / PB1 ~ PB3 u ra, tng ng vi ba cnh tay thp tt
. 11 DDRB = 0x0E ;
. 12 PORTC = 0x07 ; / / PC0 , PC1 , cm bin v tr PC2 trng u vo, ko ln
. 13 DDRC = 0x00;
. 14 PORTD = 0x00;
. 15 DDRD = 0x68 ; / / PD6 PD5 PD3 tng ng tn hiu PWM trn cy cu t cnh tay
16 . }
17.
18 .
19 .
20 . Timer0_init Void (void)
21 {
. 22 / / TCCR0B = 0x00; / / dng
. 23 / / TCNT0 = 0x01; / / thit lp s
24 .
. 25 / / TCCR0A = 0xA3 ; / / Fast PWM

. 26 / / TCCR0B = 0x01; / / bt u m thi gian chn yu t phn chia

. 27 / / OCR0A = 0x30;
. 28 / / OCR0B = 0x30;
29 .
. 30 TCCR0B = 0x00; / / dng
. 31 TCNT0 = 0x01; / / thit lp s
. 32 / / TCCR0A = 0xA3 ; / / ch CTC
. 33 / / TCCR0B = 0x01; / / bt u hn gi
. 34 OCR0A = speed0 ;
. 35 OCR0B = speed0 ;
36. }
37 .
38. Timer2_init Void (void)
39 {
40 .
. 41 TCCR2B = 0x00; / / dng
. 42 ASSR = 0x00; / / thit lp ch async
. 43 TCNT2 = 0x01; / / thit lp
. 44 OCR2A = speed0 ;
. 45 OCR2B = speed0 ;
46. }
47.
48 . Void Start_PWMAB (void)
49 {
. 50 TCCR0B = 0x00;
. 51 TCCR0A = 0xA3 ; / /
. 52 TCCR0B = 0x01; / / bt u hn gi
} 53.
54.
55 . Start_PWMA_Close_PWMB Void (void)

56 {
. 57 TCCR0B = 0x00;
. 58 TCCR0A = 0x83 ; / /
. 59 TCCR0B = 0x01; / / bt u hn gi
60 . }
61.
62. Void Start_PWMB_Close_PWMA (void)
63 {
. 64 TCCR0B = 0x00;
. 65 TCCR0A = 0x23; / /
. 66 TCCR0B = 0x01; / / bt u hn gi
} 67.
68.
69. Shut_PWMAB Void (void)
70 {
. 71 TCCR0B = 0x00;
. 72 TCCR0A = 0x02;
73. }
74.
75 . Void Start_PWMC (void)
76 {
. 77 TCCR2B = 0x00; / / dng
. 78 TCCR2A = 0x23;
. 79 TCCR2B = 0x01; / / bt u
} 80 .
81.
82 . Void Shut_PWMC (void)
83 {
. 84 TCCR2B = 0x00; / / dng
. 85 TCCR2A = 0x03 ;

86 . }
87.
88 . Phase_one_five Void (void)
89 {
90 . PORTB = PORTB &0xF5; / / tt 4,6 cnh tay cu
91 Shut_PWMC (); . / / ng cnh tay cu 3
92 Start_PWMA_Close_PWMB (); . / / ng cnh tay cu 2 , m trn mt chn
. 93 PORTB = PORTB | 0x04; / / m cnh tay thp hn 5
94. }
95 .
96 . Phase_one_six Void (void)
97 {
98. PORTB = PORTB &0xF9; / / tt 4,5 cnh tay cu
99 Shut_PWMC (); . / / ng cnh tay cu 3
100 Start_PWMA_Close_PWMB (); . / / ng cnh tay cu 2 , m trn mt chn
. 101 PORTB = PORTB | 0x08; / / m cnh tay thp hn 6
102 . }
103 .
104 . Phase_two_six Void (void)
105 {
106 . PORTB = PORTB &0xF9; / / tt 4,5 cnh tay cu
107 Shut_PWMC (); . / / ng cnh tay cu 3
108 Start_PWMB_Close_PWMA (); . / / ng cnh tay cu mt cnh tay m 2
. 109 PORTB = PORTB | 0x08; / / m cnh tay thp hn 6
110 } .
111.
112 . Phase_two_four Void (void)
113 {
114 . PORTB = PORTB &0xF3; / / tt 4,6 cnh tay cu
115 Shut_PWMC (); . / / ng cnh tay cu 3

116 Start_PWMB_Close_PWMA (); . / / ng cnh tay cu mt cnh tay m 2

. 117 PORTB = PORTB | 0x02; / / m cnh tay thp hn 4
118 } .
119.
120 . Phase_three_four Void (void)
121 {
122 . PORTB = PORTB &0xF3; / / tt 6,5 cnh tay cu
123 Shut_PWMAB (); . / / ng cnh tay cu 1,2
124 Start_PWMC (); . / / M PWMC tay cu
. 125 PORTB = PORTB | 0x02; / / m cnh tay thp hn 4
126 . }
127.
128 . Phase_three_five Void (void)
129 {
130 . PORTB = PORTB &0xF5; / / tt 6,4 cnh tay cu
131 Shut_PWMAB (); . / / ng cnh tay cu 1,2
132 Start_PWMC (); . / / M PWMC tay cu
. 133 PORTB = PORTB | 0x04; / / m cnh tay thp hn 5
134. }
135.
136 .
137.
138. Uart0_init Void (void)
139 {
. 140 UCSR0B = 0x00; / / v hiu ha trong khi thit lp tc truyn
. 141 UCSR0A = 0x00;
. 142 UCSR0C = 0x06; / / 8-bit truyn d liu
. 143 UBRR0L = 0x33 ; / / thit lp tc truyn lo
. 144 UBRR0H = 0x00; / / thit lp tc truyn hi
. 145 UCSR0B = 0x18; / /

146 . }
147.
148 init_devices Void . (Void)
149 {
150 . / / Stop ngt lang thang cho n khi thit lp
151 CLI (); . / / V hiu ho tt c cc ngt
. 152 port_init ();
. 153 timer0_init ();
. 154 timer2_init ();
. 155 uart0_init ();
156 .
. 157 MCUCR = 0x00;
. 158 EICRA = 0x00; / / ints ext m rng
. 159 EIMSK = 0x00;
160 .
Ngun / / timer 0 ngt; . 161 TIMSK0 = 0x00
Ngun / / timer 1 b gin on ; . 162 TIMSK1 = 0x00
Ngun / / b m thi gian gin on 2 ; . 163 TIMSK2 = 0x00
164 .
. 165 PCMSK0 = 0x00; / / pin mt n thay i 0
. 166 PCMSK1 = 0x00; / / pin mt n thay i 1
. 167 PCMSK2 = 0x00; / / pin mt n thay i 2
. 168 PCICR = 0x00; / / pin cho php thay i
. 169 PRR = 0x00; / / iu khin in
170 SEI (); . / / Kch hot li ngt
171 . / / Tt c cc thit b ngoi vi ang khi to
172 . }
173 .
174 .
175 . Void USART_Transmit (unsigned char d liu )

176 {
177 / / Ch cho b m pht trng
178 Trong khi . ( ( UCSR0A & (1 << UDRE0 ) ) )
179 .
180 .
181 / / gi d liu
. 182 UDR0 = d liu ;
183 . }
184 .
185 .
186 . Unsigned char USART_Receive (void)
187 {
188 / / ch i nhn d liu
189 Trong khi . ( ( UCSR0A & (1 << RXC0 ) ) )
190 .
. 191 tr li UDR0 ;
192 . }
193 .
194 . Set_speed Void (unsigned char tc )
195 {
. 196 OCR0A = tc ;
. 197 OCR0B = tc ;
. 198 OCR2B = tc ;
199 . }
200 .
201 . Void main (void)
202 {
. 203 int Pos_Val , Speed_Val ;
. 204 init_devices ();
. 205 / / Start_PWMA_Close_PWMB ();

. 206 / / Start_PWMC ();

. 207 / / Start_PWMAB ();
208 .
209 . / * Trong khi (1)
210 {
. 211 Speed_Val = USART_Receive ();
. 212 set_speed ( Speed_Val ) ;
213 } * /
214 Trong khi . (1)
215 {
216 .
217 . Nu ( ( UCSR0A & 0x80) = 0!)
218 {
. 219 Speed_Val = UDR0 ;
. 220 OCR0A = Speed_Val ;
. 221 OCR0B = Speed_Val ;
. 222 OCR2B = Speed_Val ;
223. }
224 . Pos_Val = Pinc &0x07;
225 . / * / / 500W ng c trung tm
226 Switch. ( Pos_Val )
227 {
228 trng hp 3 : .
. 229 phase_three_five ();
230 ngh .
. 231 Trng hp 2:
. 232 phase_one_five ();
233 ngh .
234 trng hp 6 : .
. 235 phase_one_six ();

236 ngh .
237 trng hp 4 : .
. 238 phase_two_six ();
239 ngh .
. 240 trng hp 5 :
. 241 phase_two_four ();
242 ngh .
243 trng hp 1: .
. 244 phase_three_four ();
245 ngh .
. 246 mc nh :
247 ngh .
248 .
249. }
250 * /
251 .
252 . / / ng c 2.2kw
253 Switch. ( Pos_Val )
254 {
255 trng hp 1: .
256 phase_three_five (); . / / C + B257 ngh .
258 trng hp 3 : .
259 phase_one_five (); . / / A + B 260 ngh .
. 261 Trng hp 2:
262 phase_one_six (); . / / A + C263 ngh .
264 trng hp 6 : .
265 phase_two_six (); . / / B + C -

266 ngh .
267 trng hp 4 : .
268 phase_two_four (); . / / B + A269 ngh .
. 270 trng hp 5 :
271 phase_three_four (); . / / C + B272 ngh .
. 273 mc nh :
274 ngh .
275 .
276 . }
277 .
278 .
279. }
280 . }

//********************************************************///////////////

1.

///**purpose: use PWM to control BLDCM**********/////

2.

///***data: 2008.8.20***********///

3.

///***author: XieZu Su********//////

4.

#include <iom48v.h>

5.

#include <macros.h>

6.

#define speed0 0x20

7.
8.

void port_init(void)

9.

10.

PORTB = 0x00; //PB1~PB3 3

11.

DDRB = 0x0E;

12.

PORTC = 0x07; //PC0,PC1,PC2

13.

DDRC = 0x00;

14.

PORTD = 0x00;

15.

DDRD = 0x68; //PD6 PD5 PD3 PWM

16. }
17.
18.
19.
20. void timer0_init(void)
21. {
22.

//TCCR0B = 0x00; //stop

23.

// TCNT0 = 0x01; //set count

24.
25.

// TCCR0A = 0xA3; // PWM

26.

// TCCR0B = 0x01; //start timer

27. // OCR0A = 0x30;

28. // OCR0B = 0x30;
29.
30.

TCCR0B = 0x00; //stop

31.

TCNT0 = 0x01; //set count

32.

//TCCR0A = 0xa3; //CTC mode

33.

//TCCR0B = 0x01; //start timer

34.

OCR0A = speed0;

35.

OCR0B = speed0;

36. }
37.
38. void timer2_init(void)
39. {
40.
41.

TCCR2B = 0x00; //stop

42.

ASSR = 0x00; //set async mode

43.

TCNT2 = 0x01; //setup

44.

OCR2A = speed0;

45.

OCR2B = speed0;

46. }
47.
48. void Start_PWMAB(void)
49. {
50.

TCCR0B = 0x00;

51.

TCCR0A = 0xA3; //

52.

TCCR0B = 0x01; //start Timer

53. }
54.
55. void Start_PWMA_Close_PWMB(void)
56. {
57.

TCCR0B = 0x00;

58.

TCCR0A = 0x83; //

59.

TCCR0B = 0x01; //start Timer

60. }
61.
62. void Start_PWMB_Close_PWMA(void)
63. {
64.

TCCR0B = 0x00;

65.

TCCR0A = 0x23; //

66.

TCCR0B = 0x01; //start Timer

67. }
68.
69. void Shut_PWMAB(void)
70. {
71.

TCCR0B = 0x00;

72.

TCCR0A = 0x02;

73. }

74.
75. void Start_PWMC(void)
76. {
77.

TCCR2B = 0x00; //stop

78.

TCCR2A = 0x23;

79.

TCCR2B = 0x01; //start

80. }
81.
82. void Shut_PWMC(void)
83. {
84.

TCCR2B = 0x00; //stop

85.

TCCR2A = 0x03;

86. }
87.
88. void phase_one_five(void)
89. {
PORTB = PORTB&0xF5; // 46

90.
91.

Shut_PWMC(); // 3

92.

Start_PWMA_Close_PWMB(); // 2 1

93.

PORTB = PORTB|0x04;

// 5

94. }
95.
96. void phase_one_six(void)
97. {
PORTB = PORTB&0xF9; // 45

98.
99.

Shut_PWMC(); // 3

100. Start_PWMA_Close_PWMB(); // 2 1
101. PORTB = PORTB|0x08;
102. }
103.

// 6

104. void phase_two_six(void)

105. {
106.

PORTB = PORTB&0xF9; // 45

107. Shut_PWMC(); // 3
108. Start_PWMB_Close_PWMA(); // 1 2
109. PORTB = PORTB|0x08;

// 6

110. }
111.
112. void phase_two_four(void)
113. {
114.

PORTB = PORTB&0xF3; // 46

115. Shut_PWMC(); // 3
116. Start_PWMB_Close_PWMA(); // 1 2
117. PORTB = PORTB|0x02;

// 4

118. }
119.
120. void phase_three_four(void)
121. {
122.

PORTB = PORTB&0xF3; // 65

123. Shut_PWMAB(); // 1,2

124. Start_PWMC(); // PWMC
125. PORTB = PORTB|0x02;

// 4

126. }
127.
128. void phase_three_five(void)
129. {
130.

PORTB = PORTB&0xF5; // 64

131. Shut_PWMAB(); // 1,2

132. Start_PWMC(); // PWMC
133. PORTB = PORTB|0x04;

// 5

134. }
135.
136.
137.
138. void uart0_init(void)
139. {
140. UCSR0B = 0x00; //disable while setting baud rate
141. UCSR0A = 0x00;
142. UCSR0C = 0x06; //8
143. UBRR0L = 0x33; //set baud rate lo
144. UBRR0H = 0x00; //set baud rate hi
145. UCSR0B = 0x18; //
146. }
147.
148. void init_devices(void)
149. {

150.

//stop errant interrupts until set up

151.

CLI(); //disable all interrupts

152.

port_init();

153.

timer0_init();

154.

timer2_init();

155. uart0_init();
156.
157.

MCUCR = 0x00;

158.

EICRA = 0x00; //extended ext ints

159.

EIMSK = 0x00;

160.
161.

TIMSK0 = 0x00; //timer 0 interrupt sources

162.

TIMSK1 = 0x00; //timer 1 interrupt sources

163.

TIMSK2 = 0x00; //timer 2 interrupt sources

164.

165.

PCMSK0 = 0x00; //pin change mask 0

166.

PCMSK1 = 0x00; //pin change mask 1

167.

PCMSK2 = 0x00; //pin change mask 2

168.

PCICR = 0x00; //pin change enable

169.

PRR = 0x00; //power controller

170.

SEI(); //re-enable interrupts

171.

//all peripherals are now initialized

172. }
173.
174.
175. void USART_Transmit(unsigned char data)
176. {
177.
178.

//
while(!(UCSR0A&(1<<UDRE0)))

179. ;
180.
181. //
182. UDR0 = data;
183. }
184.
185.
186. unsigned char USART_Receive(void)
187. {
188.

//

189. while(!(UCSR0A&(1<<RXC0)))
190. ;
191. return UDR0;
192. }
193.

194. void set_speed(unsigned char speed)

195. {
196.

OCR0A = speed;

197. OCR0B = speed;

198. OCR2B = speed;
199. }
200.
201. void main(void)
202. {
203.

unsigned int Pos_Val,Speed_Val;

204. init_devices();
205. //Start_PWMA_Close_PWMB();
206. // Start_PWMC();
207. // Start_PWMAB();
208.
209. /* while(1)
210. {
211.

Speed_Val = USART_Receive();

212. set_speed(Speed_Val);
213. }*/
214. while(1)
215. {
216.
217. if((UCSR0A&0x80)!=0)
218. {
219. Speed_Val = UDR0;
220. OCR0A = Speed_Val;
221. OCR0B = Speed_Val;
222. OCR2B = Speed_Val;
223. }

224. Pos_Val = PINC&0x07;

225. /* // 500w
226. switch(Pos_Val)
227. {
228.

case 3:

229. phase_three_five();
230. break;
231. case 2:
232. phase_one_five();
233. break;
234. case 6:
235. phase_one_six();
236. break;
237. case 4:
238. phase_two_six();
239. break;
240. case 5:
241. phase_two_four();
242. break;
243. case 1:
244. phase_three_four();
245. break;
246. default:
247. break;
248.
249. }
250. */
251.
252. // 2.2kw
253. switch(Pos_Val)

254. {
255.

case 1:

256. phase_three_five(); //C+ B257. break;

258. case 3:
259. phase_one_five();

//A+ B-

260. break;
261. case 2:
262. phase_one_six();

//A+ C-

263. break;
264. case 6:
265. phase_two_six();

//B+ C-

266. break;
267. case 4:
268. phase_two_four();

//B+ A-

269. break;
270. case 5:
271. phase_three_four();
272. break;
273. default:
274. break;
275.
276. }
277.
278.
279. }
280. }

//C+ B-