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  • Design Equations: Input Pin: Treshold Vdd/2

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    lapbr
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    The document provides steps to design a comparator circuit with resistors (R1, R2, R3, R4) and a capacitor (C). Step 1 selects the input voltage ranges (Uinmax, Uinmin) and resistor R1, then calculates R2. Step 2 determines whether to include R3 based on the input voltage sums and supply voltage Vdd. Step 3 similarly determines whether to include R4 based on resolution requirements and input voltage ranges. Step 4 calculates R3 or the common resistance Rp if R3 is excluded, and calculates the capacitor C for a given sample frequency Fs and resolution N.

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    Sigma Delta Adc

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    The document provides steps to design a comparator circuit with resistors (R1, R2, R3, R4) and a capacitor (C). Step 1 selects the input voltage ranges (Uinmax, Uinmin) and resistor R1, then calculates R2. Step 2 determines whether to include R3 based on the input voltage sums and supply voltage Vdd. Step 3 similarly determines whether to include R4 based on resolution requirements and input voltage ranges. Step 4 calculates R3 or the common resistance Rp if R3 is excluded, and calculates the capacitor C for a given sample frequency Fs and resolution N.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    6 views1 page

    Design Equations: Input Pin: Treshold Vdd/2

    Uploaded by

    lapbr
    The document provides steps to design a comparator circuit with resistors (R1, R2, R3, R4) and a capacitor (C). Step 1 selects the input voltage ranges (Uinmax, Uinmin) and resistor R1, then calculates R2. Step 2 determines whether to include R3 based on the input voltage sums and supply voltage Vdd. Step 3 similarly determines whether to include R4 based on resolution requirements and input voltage ranges. Step 4 calculates R3 or the common resistance Rp if R3 is excluded, and calculates the capacitor C for a given sample frequency Fs and resolution N.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    Vdd

    R3

    C Port

    input pin: treshold = Vdd/2 output pin: new state each 1/Fs (eg. interrupt cycle time)

    R1 Uin R4 C

    R2 Port

    GND

    Design Equations
    Vdd Uinmax = 2 R1 R2 R1 R3 R1 R4

    * 1 +

    Vdd Uinmin = 2

    * 1 -

    R1 R2

    R1 R3

    R1 R4

    Step 1
    Select Uinmax, Uinmin and R1 and calculate R2 Vdd R2 = Uinmax - Uinmin * R1

    R1 Uinmax - Uinmin = Vdd * R2

    Uinmax + Uinmin = Vdd * 1 -

    R1 R3

    R1 R4

    Step 2
    If (Uinmax + Uinmin) > Vdd R3 = (eg. leave R3 out) Vdd (Uinmax + Uinmin) - Vdd Rp = 1 R1 + 1 1 R2 + 1 R4 = Vdd 2*Uinmax * R1 * R1 8 8

    Step 3
    R4 = Check Uinmax and Uinmin for bit resolution N Uinmax must comply to : Uinmax < 2 N-1 * (Uinmax - Uinmin) Uinmin must comply to : Uinmin > Vdd - 2 N-1

    * (Uinmax - Uinmin)

    If (Uinmax + Uinmin) < Vdd R4 = (eg. leave R4 out) Vdd Vdd - (Uinmax + Uinmin) Rp = 1 1 R1 + 1 R2 + 1 R3 = Vdd 2*Vdd - 2*Uinmin * R1 * R1

    Step 4
    R3 = Calculate C for sample frequency Fs and bit resolution N 2N C= 4 * R2 * Fs R2 2 N * Rp * 1 + 1 1 *k2

    k =

    3 (note: k < 1 if step 3 succeeded) R3 = R4 = Rp = 1 1 R1 + 1 R2

    If (Uinmax + Uinmin) = Vdd (eg. leave R3 out) (eg. leave R4 out) Vdd Vdd + Uinmax - Uinmin * R1 = Vdd 2*Uinmax * R1 8 = 8

    Step 5
    Calculate total conversion time Tc 2N Tc = Fs

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