02 Goi Thieu Kiên Truc MCS - 51

ICTU 03-2010
Chng 3 Vi iu khin 8051 v lp trnh hp ng Kin trc 8051

Pham Quoc Thinh, ictu.edu.vn. 1
Department of Electronics & Telecommunications
Ni dung bi ging
Tng quan c im chung v hot ng S khi S chn
M t phn cng
M t chn c im c-sa i-ghi
Pham Quoc Thinh, ictu.edu.vn.
Tng quan v 8051

Sn xut bi Intel nm 1981 Vi iu khin n chp 8-bit, c ti u cho cc ng dng iu khin 128 byte RAM, 4096 byte (4KB) ROM, 2 timer, 1 serial port, 4 I/O port 40 Chn c ng gi theo chun DIP)
Cc c im chung
4KB ROM 128 bytes RAM ni
4 x 8 = 32 16 80 -----------128
4 bank thanh ghi vi 8 byte mi bank (R0-R7) 16 byte c nh a ch bit 80 byte b nh a dng
Bn cng I/O 8-bit (P0-P3) Hai b timer 16-bit (Timer0 v Timer1) Mt b giao din truyn nhn ni tip Nm ngun ngt (2 ngt ngoi v 3 ngt ni)
B nh d liu v chng trnh ca 8051 c th c m rng ti 64K ROM v 64K RAM

S khi 8051
External Interrupts 4K byte ROM 128 byte RAM
Timer 1 Timer 0
Interrupt Control
Counter Inputs
CPU
OSC
Bus Control
I/O Ports
Serial Port
TXD RXD P0 P2 P1 P3 (Address/Data)

S chn
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 P0.1 P0.2 P0.3 P0.4 (AD0) (AD1) (AD2) (AD3) (AD4)
8051
P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
S chn vi cc chc nng tch hp, cc chn tn hiu

VSS XTAL1 XTAL2 VCC RST P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P O R T 0 Bus a ch v d liu
EA PSEN ALE
P O R T 1
SECONDARY FUNCTIONS
RxD TxD INT0 INT1 T0 T1 WR RD
P O R T 3
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P O R T 2
Bus a ch
Mch reset Power-on vi phm bm
M t phn cng
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Mch dao ng B m chng trnh (PC) Con tr d liu (DPTR) Thanh ghi A Thanh ghi B Cc c T trng thi chng trnh (PSW) B nh ni(ROM, RAM, b nh m rng) Stack v con tr stack (SP) Thanh ghi chc nng c bit (SFR)
9
Mch dao ng
Tri tim ca 8051 Cung cp xung ng h ng b tt c cc hot ng ni ca 8051
Mt chu k my bao gm 12 xung t tn s thch anh!
10
V d
Tnh chu k my vi tn s thch anh tng ng: (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz (c) XTAL = 20 MHz
Ta c: (a) 11.0592 MHz / 12 = 921.6 kHz Chu k my= 1 / 921.6 kHz = 1.085 s (b) 16 MHz / 12 = 1.333 MHz Chu k my = 1 / 1.333 MHz = 0.75 s (c) 20 MHz / 12 = 1.667 MHz Chu k my = 1 / 1.667 MHz = 0.60 s
11
B m chng trnh (PC)

PC l mt thanh ghi 16-bit PC khng c a ch ni. PC tr ti a ch ca lnh k tip cn c thc hin. PC s t ng tng thm 1 (+1) mi khi CPU nhn m lnh t ROM Khi bt ngun PC c gi tr 0000, ngha l 8051 lun thc hin t m lnh u tin ti a ch 0000h PC rng 16 bit, 8051 c th truy cp c a ch chng trnh t 0000h n FFFFh (64 kbyte)
12
Con tr d liu (DPTR)

DPTR l mt thanh ghi 16 bit DPTR c to bi 2 thanh ghi 8-bit: DPH v DPL DPTR gi a ch b nh cho cc truy cp d liu v m trong b nh ni v b nh ngoi
(v d: MOVC A,@A+DPTR MOVX A,@DPTR MOVX @DPTR,A )
DPTR khng c a ch; DPH v DPL c gn a ch ring (83H and 82H)
13
Thanh ghi tch lu A

L thanh ghi c s dng nhiu nht trong 8051. N c s dng nhiu trong cc hot ng nh cng, tr, nhn, chia, cc lnh x l bit Thanh ghi A c s dng cho tt c d liu c truyn gia 8051 v b nh ngoi
14
Thanh ghi B
Thanh ghi B c s dng vi thanh ghi A cho cc hot ng nhn v chia (V d: MUL AB DIV AB) Khng c chc nng c bit khc, c th l ni lu tr d liu.
15
Cc c
Cc c c nm trong thanh ghi t trng thi chng trnh (PSW) v thanh ghi iu khin ngun (PCON) Cc c ton hc: CY, AC, OV, P Cc c ngi s dng: Cc c ngi lp trnh ghi mt vi s kin trong chng (F0, GF0, GF1)
16
T trng thi chng trnh(PSW)

PSW bao gm cc c ton hc, c ngi s dng F0, v cc bit la chn bank thanh ghi (RS1, RS0)
7 CY
6 AC
5 4 3 2 F0 RS1 RS0 OV
1 --
0 P
17
T trng thi chng trnh (PSW)

Bit K hiu Chc nng
7 6 CY AC C nh; c s dng trong cc lnh s hc, nhy, quay v logic C nh ph; c s dng cho s hc BCD
5
4 3 2 1 0
F0
RS1 RS0 OV -P
C ngi s dng 0
Bit 1 la chon bank thanh ghi Bit 0 la chon bank thanh ghi C trn; s dng trong cc lnh s hc Dnh cho tng lai s dng C chn l; Ch ra tnh chn l ca thanh ghi A: 1 = Tnh l
18
Cc lnh nh hng n c
Lnh ADD ADDC SUBB MUL CY X X X 0 OV X X X X AC X X X Lnh SETB C CLR C CPL C ANL C, bit CY 1 0 X X OV AC
DIV DA
RRC RLC MOV C, bit
0 X
X X X
ANL C, /bit ORL C, bit

ORL C, /bit CJNE
X X
X X
Ch : X c th 0 hoc 1
19
B nh ni
Mt my tnh chc nng phi c b nh cho cc
byte m chng trnh, thng trong ROM v b nh cho d liu thay i c th thay i khi chy chng trnh 8051 c RAM ni (128 byte) v ROM (4Kbyte) 8051 s dng a ch tng t nhng khc loi b nh cho m v d liu Mch truy cp ni b s truy cp chnh xc b nh da trn hot ng x l. C th m rng b nh nu cn
20
T chc RAM ni 8051

1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0
128 byte RAM ni Department of Electronics & Telecommunications 4 bank thanh ghi v 8 byte mi bank(R0-R7) 16 byte c nh a ch bit 80 byte vng RAM a dng
7F
Bank 2
Bank 3
2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20
7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07
78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
Bank 0
Bank 1
30
Cc thanh ghi lm vic

nh a ch bit
Mc ch chung
21
22
23
V d 1
Trng thi cc thnh phn ca RAM sau khi thc hin chng trnh sau: MOV R0, #99H Cho rng bank thanh ghi MOV R1, #85H 0 c la chn! MOV R2, #3FH MOV R7, #63H MOV R5, #12H Sau khi thc thi chng trnh trn:
V tr 0 trong RAM c gi tr 99 V tr 2 trong RAM c gi tr 3FH V tr 5 trong RAM c gi tr 12H V tr 1 trong RAM c gi tr 85H V tr 7 trong RAM c gi tr 63H
24
Program Status Word (PSW)

Bank Select Bits, RS1, & RS0 to select 1 of 4 register bank
25
V d 2
S dng a ch RAM thay v tn cc thanh ghi
Ci ny c gi l nh a ch trc tip v s dng v tr a ch RAM cho a ch ch MOV 00, #99H MOV 01, #85H MOV 02, #3FH MOV 07, #63H MOV 05, #12H
26
V d 3
Trng thi cc thnh phn trong RAM sau khi thc hin on chng trnh sau:
SETB MOV MOV MOV MOV MOV PSW.4 R0, #99H R1, #85H R2, #3FH R7, #63H R5, #12H
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
--
0
P
PSW
CY
Mc nh PSW.3=0 v PSW.4=0; v th, lnh SETB PSW.4 t RS1=1 v RS0=0, do bank thanh ghi 2 c la chn . Bank thanh ghi 2 a ch 10H 17H trong RAM. Sau khi thc thi chng trnh trn chng ta s c: V tr RAM 10 c gi tr 99H V tr RAM 12 c gi tr 3FH V tr 15 c gi tr 12H
V tr RAM 11 c gi tr85H V tr RAM 17 c gi tr 63H

27
Ngn xp v con tr ngn xp (SP)

SP l mt thanh ghi 8 bit c s dng gi a ch trong RAM ni ci c gi l nh ca ngn xp Stack l mt khu vc trong RAM ni c s dng lu tr d liu v ly ra mt cch nhanh chng SP gi a ch RAM ni ni m byte d liu c lu bi hot ng ca stack Khi d liu c lu trong stack, con tr SP s tng ln trc khi d liu c lu. Khi ly d liu t stack ra, SP s gim tr ti byte d liu c lu tr nh stack SP = 07H sau khi reset
28
Hot ng
Lu tr d liu
Nhn d liu
SP = 0A
a ch 0A
SP = 0A
Lu tr d liu
Nhn d liu
SP = 09
a ch 09
SP = 09
Lu tr d liu
SP = 08
a ch 08
Nhn d liu
SP = 08
SP = 07
Lu d liu trn stack (tng khi lu)
Address 07 RAM ni (Ly d liu sau gim)
SP = 07
Nhn d liu t stack
29
V d 4
Ch ra stack v con tr stack khi thc hin cc lnh sau y: MOV R6, #25H MOV R1, #12H MOV R4, #0F3H PUSH 6 PUSH 1 PUSH 4
Sau khi PUSH 6
Sau khi PUSH 1
Sau khi PUSH 4
0B 0A 09 08
0B 0A 09 08 25 SP = 08
0B 0A 09 12 08 25
0B 0A F3 09 12 08 25
SP = 07
SP = 09
SP = 0A
30
V d 5
Kim tra stack, Ch ra cc thanh phn ca cc thanh ghi v SP sau khi thc thi cc lnh sau y. Tt c cc gi tr l kiu hex. POP 3 ;POP stack vo R3 POP 5 ;POP stack vo R5 POP 2 ;POP stack vo R2
Sau POP 3 0B 0A 09 08 54 F9 76 6C 0B 54 0A F9 09 76 08 6C SP = 0A Sau POP 5 0B 54 0A F9 09 76 08 6C SP = 09 Sau POP 2 0B 54 0A F9 09 76 08 6C SP = 08
Bt u SP = 0B
05 04 03 02
?? ?? ?? ??
05 04 03 02
?? ?? 54 ??
05 04 03 02
F9 ?? 54 ??
05 04 03 02
F9 ?? 54 76
31
V d 6
Ch ra stack v con tr stack khi thc hin cc lnh sau: MOV SP, #5FH MOV R2, #25H MOV R1, #12H MOV R4, #0F3H PUSH 2 PUSH 1 PUSH 4
Sau PUSH 2 63 62 61 60 Bt u SP = 5F
Sau PUSH 1 63 62 61 12 60 25 SP = 61
Sau PUSH 4 63 62 F3 61 12 60 25 SP = 62
32
63 62 61 60 25 SP = 60
Cc thanh ghi chc nng c bit (SFR)

8051 c 21 thanh ghi SFR gi a ch 80H n FFH (128bytes) Khng phi tt c cc a ch t 80H n FFH c s dng cho SFR Vic c gng s dng "trng" a ch c th nhn c kt qu khng th on trc c
33
Thanh ghi chc nng c bit

nh a ch bit
34
Gi tr ca cc thanh ghi SFR khi reset
35
ROM ni (Internal ROM)

ROM ni chim khng gian a ch t 0000H n 0FFFH (Size = 4K byte) a ch chng trnh cao 0FFFH s t ng tm np cc byte m t b nh chng trnh ngoi Cc byte m cng c th c tm np ring t b nh ngoi bi vic kt ni pin (EA) xung t
36
Cc chn quan trng

VCC (pin 40 Cung cp in p +5V) GND (pin 20) XTAL1 & XTAL2 (pins 19 & 18 ni ti thch anh v t) RST (pin 9- reset) EA (pin 31 truy xut ngoi) PSEN (pin 29 Cho php lu tr chng trnh) ALE (pin 30 Cho php cht a ch) Ports 0-3
37
I/O Ports (P0 - P3)

Mt trong cc c im hu ch nht ca 8051 bao gm 4 cng I/O (P0 - P3)
Tt c cc cng c hai hng (c th l vo hoc ra) Cc cng c a chc (tr cng P1) Tt c cc cng c nh a ch bit
Khi RESET tt c cc cng c cu hnh l output Khi mt PIN c s dng nh l input, 1 phi c vit ra tng ng vi bit PIN chng trnh cu hnh n nh mt ng u vo (vi d: MOV P1,
#0FFH)
38
Port 0
C 8 PIN (Pins 32-39) C th c s:
Ch l u vo Ch l u ra Vo v ra(chn c cu hnh l u vo cn chn khc th cu hnh l u ra )
C th c s dng iu khin c a ch v d liu Cn in tr ko

39
Port 0 nh mt cng ra
AAH = 101010102 55H = 010101012
M sau y s lin tc gi ra cng P0 gi tr 55H v AAH

MOV MOV ACALL CPL SJMP A, #55H P0, A DELAY A BACK
BACK:
40
Port 0 nh mt cng vo
FFH = 111111112
Trong m sau y, port 0 u tin c cu hnh l mt cng vo bi vic vit 1 ra n sau d liu c c vo P0 v xut ra cng P1
MOV MOV MOV MOV SJMP A, #0FFH P0, A A, P0 P1, A BACK
BACK:
41
Vai tr th hai ca Port 0

Khi kt ni 8051 vi b nh ngoi,P0 cung cp c a ch v d liu (AD0 AD7)
Khi ALE = 0, n cung cp d liu D0 D7

Khi ALE = 1, n cung cp a ch A0 A7 ALE c s dng phn knh a ch v d liu vi vi mch cht 74LS373
42
Port 1
C 8 pin (Pins 1-8) C th c s dng nh cng vo hoc ra Khng cn tr treo khi reset, port 1 c cu hnh nh mt cng ra
Khng c chc nng khc
43
Port 1 cu hnh nh mt cng ra

M sau y s gi lin tc ti P1 gi tr 55H v AAH
BACK:
44
Cng P1 nh mt cng vo
P1 mt cu hnh nh mt cng vo bi vic ghi bit 1 ra tng ng v sau d liu c c vo v ghi vo thanh ghi R7, R6 v R5
MOV MOV MOV MOV ACALL MOV MOV ACALL MOV MOV
A, #0FFH P1, A A, P1 R7, A DELAY A, P1 R6, A DELAY A, P1 R5, A

45
Port 2

C 8 chn (Chn 21 n28) C th c s dng nh u vo hoc u ra Khng cn ni tr treo Sau khi reset, port 2 c cu hnh nh mt cng ra Khi kt ni 8051 vi b nh ngoi, cng P2 cung cp a ch (A8-A15) N c s dng cng vi P0 cung cp 16 bit a ch Khi P2 c s dng cho 8 bit cao ca 16 bit a ch th n khng c s dng vi chc nng I/O
46
Cng P2 nh mt cng ra
Gii ra cng P2 gi tr 55h v AAh thc hin lp i lp li
BACK:
47
P2 nh mt cng vo
u tin P2 c cu hnh l cng input v sau then d liu nhn c cng ny gi ti cng P1
MOV MOV MOV MOV SJMP A, #0FFH P2, A A, P2 P1, A BACK
BACK:
48
Chc nng tch hp ca P2

S dng 8051 s dng b nh ngoi P2 cung cp c a (A8 A15) N c s dng cung cp a ch 16 bit
Khi P2 c s dng cho 8 bit cao ca 16 bit a ch
49
Cng P3

C 8 chn (Cc chn t 10 n17) C th c s dng nh u vo hoc du ra Khng cn tr treo Sau khi reset, cng P3 c cu hnh nh mt cng ra Cc chn c th c lp trnh cho nhng ngi s dng khc nhau Hu ht thng c s dng cung cp mt s tn hiu quan trng(v d: cc ngt)
50
Cc chc nng tch hp thm trn cng P3

P3 Bit
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Function
RxD TxD INT0 INT1 T0 T1 WR RD
Pin
10 11 12 13 14 15 16 17
51
c im c- sa i- ghi
Mt phng php c s dng truy xut cc cng 8051 Thc hin 3 hnh ng trong mt lnh:
c d liu cng Sa d liu trn cng Ghi kt qu ra cng
MOV XRL ACALL SJMP P1, #55H P1, #0FFH DELAY AGAIN
Vi d: ANL P1, A ORL P2, A XRL P3, A JBC P1.1, LABEL CPL P3.0 INC P2 DEC P2 DJNZ P3, LABEL
AGAIN:
52
nh a ch bit tng chn trong mt cng y l mt trong nhng tnh nng mnh m nht ca 8051 C th truy sut mt hoc mt vi bit trong mt cng
BACK: CPL ACALL SJMP
;bit 2 ca cng1 P1.2 DELAY BACK
53
V d 7
Vit mt chng trnh thc hin nhng yu cu sau:
(a) Kim tra chn P1.2 cho n khi P1.2 c mc cao; (b) Khi P1.2 c mc cao, ghi gi tr 45H ra cng P0 (c) Gi tn hiu xung high-to-low (H-to-L) ti P2.3 SETB MOV AGAIN: JNB ; Khi P1.2 = 1 P1.2, AGAIN ; Ch P1.2=1 P1.2 ;Cu hnh chn P1.2 thnh input A, #45H
MOV SETB CLR

P0, A P2.3 P2.3

54
Summary
Cc c im vt l v hot ng
M t phn cng 8051 M t cc chn 8051 Cc lnh c ghi Read-modify-write cc cng
55

02 Goi Thieu Kiên Truc MCS - 51

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ICTU 03-2010

Chng 3 Vi iu khin 8051 v lp trnh hp ng Kin trc 8051

Department of Electronics & Telecommunications

Pham Quoc Thinh, ictu.edu.vn.

Department of Electronics & Telecommunications

Tng quan v 8051

Pham Quoc Thinh, ictu.edu.vn.

Department of Electronics & Telecommunications

B nh d liu v chng trnh ca 8051 c th c m rng ti 64K ROM v 64K RAM

Department of Electronics & Telecommunications

TXD RXD P0 P2 P1 P3 (Address/Data)

Department of Electronics & Telecommunications

Pham Quoc Thinh, ictu.edu.vn.

Department of Electronics & Telecommunications

S chn vi cc chc nng tch hp, cc chn tn hiu

RxD TxD INT0 INT1 T0 T1 WR RD

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

Pham Quoc Thinh, ictu.edu.vn.

Department of Electronics & Telecommunications

Mch reset Power-on vi phm bm

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Department of Electronics & Telecommunications

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Department of Electronics & Telecommunications

Tri tim ca 8051 Cung cp xung ng h ng b tt c cc hot ng ni ca 8051

Mt chu k my bao gm 12 xung t tn s thch anh!

Pham Quoc Thinh, ictu.edu.vn.

Department of Electronics & Telecommunications

Department of Electronics & Telecommunications

B m chng trnh (PC)

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Department of Electronics & Telecommunications

Con tr d liu (DPTR)

DPTR khng c a ch; DPH v DPL c gn a ch ring (83H and 82H)

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Department of Electronics & Telecommunications

Thanh ghi tch lu A

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Department of Electronics & Telecommunications

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Department of Electronics & Telecommunications

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Department of Electronics & Telecommunications

T trng thi chng trnh(PSW)

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Department of Electronics & Telecommunications

T trng thi chng trnh (PSW)

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Department of Electronics & Telecommunications

ANL C, /bit ORL C, bit

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Department of Electronics & Telecommunications

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T chc RAM ni 8051

Cc thanh ghi lm vic

Department of Electronics & Telecommunications

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Department of Electronics & Telecommunications

Pham Quoc Thinh, ictu.edu.vn.

Department of Electronics & Telecommunications

Pham Quoc Thinh, ictu.edu.vn.

Department of Electronics & Telecommunications