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Lab 1 - Huong Dan Thiet Ke Verilog (Quartus II 7.2)
Lab 1 - Huong Dan Thiet Ke Verilog (Quartus II 7.2)
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Nhp ng dn th mc ca project ( c th to trc hoc nu cha to s c t ng to ). Nhp tn ca project. Nhp top-level ca thit k cho project ( nn cho ging tn ca project ). Nhn Next > Nu ng dn th mc ca project cha c to trc :
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Nhn Yes
Chn Family : Cyclone II Chn Available devices : EP2C35F672C6 ( H ca Chip FPGA Cyclone II trn Kit DE2 ). Nhn Next >
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2. Thit k mt mch in n gin ( cng XOR ) dng Verilog trn Quartus II:
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Nhp Verilog design cho cng XOR vo ca s Text Editor. Nh phi tn ca top-level module phi ging tn ca Project. ( Trong th d ny l light).
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a File vo project ( c th a mt hoc nhiu File vo Project, chng hn nh File cha top-level module v nhng Files cha sub-level module ). + Assignments -> Settings + Chn Category : Files
+ Nhn vo button
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+ Ch ng dn ca nhng Files verilog cn a vo Project. Compiling design : Processing -> Start Compilation Review Compilation report : Processing -> Compilation Report
Gn pin cho design : Assignments -> Pins Double click on Location, chn pin trn Chip FPGA cho design.
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Re- compiling design : Processing -> Start Compilation Review Compilation report : Processing -> Compilation Report
Nhn OK
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Chn thi gian thc hin m phng : Edit -> End Time Nhp thi gian thc hin m phng. Fit windown : View -> Fit in Windown To waveform cho inputs : Edit -> Insert Node or Bus
Chn Filter : Pins : all Nhn button List Chn signal bn Nodes found ; nhn >> chuyn sang bn Selected Nodes Nhn OK
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Chn mt input signal bng cch nhp chut vo signal . Chn biu tng mi tn con tr Di chuyn con tr sang mn hnh waveform . Nhn v gi chut v ko r ( left ) trong mt khong thi gian ( gi s ta mun trong khong thi gian t 40ns -> 60 ns , SW0 signal c gi tr 1, th ta nhn , gi v r chut trong khong thi gian t 40ns -> 60ns.
Tng t cho nhng tn hiu inputs khc, khng to waveform cho outputs ( XXX). Save File Waveform : File -> Save As
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Chn Simulator Settings Chn Simulation mode : Functional / Timing Ch ng dn ca input waveform va to. Nhn OK To simulation netlist : Processing -> Generate Functional Simulation Netlist Chy m phng : Processing -> Start Simulation. Quan sat output waveform.
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Nhn Hardware Setup , chn USB-Blaster[USB-0] ( Ch : phi ci t driver cho USB-Blater trc ).
Nhn Close Chn Mode JTAG Nhn Add File , ch ng dn n File .sof (c to ra khi chy Compilation). Check box Program/Configure Page 13
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Nhn Start. Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.
Chn Family : Cyclone II Chn Available devices : EP2C35F672C6 Nhn Device & Pin Option Chn Tab Configuration
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Chn Configuration device : EPCS64 ( h EPPROM trn Kit DE2 , dng lu chng trnh np cho FPGA mi khi power on ). Tng t JTAG nhng bc k tip . Trn Kit DE2 , chuyn Switch RUN/PROG v v tr RUN Trn mn hnh chnh Quantus II, chn Tools -> Programmer Chn Hardware Setup : USB-Blaster[USB-0] Chn Mode : Active Serial Programming Nhn Add File, ch ng dn n File .pof ( File c to ra trong qu trnh chy Compilation ).
Check box Program/Configure. Nhn Start programming chng trnh cho EPPROM. Nhn Phm Restart trn Kit DE2, Quan st trn Kit DE2, switch SW0, SW1 v quan st LED.
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