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HCM KHOA IN IN T B MN IN T
TP.HCM, 2011
Ni dung
1. Gii thiu KIT DE1 2. Hng dn thit k vi phn mm Quartus II 3. V d
Ni dung
1. Gii thiu KIT DE1 2. Hng dn thit k vi phn mm Quartus II 3. V d
Ni dung
1. Gii thiu KIT DE1 2. Hng dn thit k vi phn mm Quartus II 3. V d
Click vo hp (box) Dont show me this introduction again Tip theo nhp Next
Nhn Yes
Chn chip Cyclone II EP2C20F484C7 (FPGA c s dng trn board DE1) Chn chip Cyclone II EP2C35F672C6 (FPGA c s dng trn board DE2) Nhn Next
f = x1 x2
File name: lu tn trng vi tn ca module Save as type: Verilog HDL File Check chn Add file to current project
Click chut vo biu tng khoanh vng trn mu (Start Compilation) Hoc vo Processing Start compilation
Chn ng dn cha file DE1_pin_assignments.csv (nu dng KIT DE1) hoc file DE2_pin_assignments.csv (nu dng KIT DE2) Nhn OK
Lu : nu ta t tn cc bin ng vo, ra ca module trng vi tn cc chn trn KIT th ta b qua bc ny (tn cc chn trn KIT xem file DEx_pin_assignments.csv, vi x l 1 hoc 2)
Ca s Waveform Editor
Simulation result
Ni dung
1. Gii thiu KIT DE1 2. Hng dn thit k vi phn mm Quartus II 3. V d
V d
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