Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

FEATURES Low-noise, wide dynamic range amplifier Very low noise figure Dual balanced mixer for up to 60 dB on-chip image rejection Programmable IF I/Q combiner On-chip programmable quadrature network Very fast 3-wire control bus Down-conversion mixer for closed-loop transmitters Independent TX/RX fast ON/OFF power-down modes Very small outline packaging Very small application (no image filter). APPLICATIONS 900 MHz front-end for GSM hand-portable equipment Compact digital mobile communication equipment TDMA receivers. GENERAL DESCRIPTION UAA2072M contains both a receiver front-end and a high frequency transmit mixer intended to be used in the GSM (Global System for Mobile communications) cellular telephones. Designed in an advanced BiCMOS process it combines high performance with low power consumption and a high degree of integration, thus reducing external component costs and total front-end size. The main advantage of the UAA2072M is its ability to provide at least 30 dB of image rejection. Consequently, the image filter between the LNA and the mixer is suppressed and the duplexer design is eased, compared with a conventional front-end design. Image rejection is achieved in the internal architecture by two RF mixers in quadrature and two all-pass filters in I and Q IF channels that phase shift the IF by 45 and 135 QUICK REFERENCE DATA SYMBOL VCC ICCRX ICCTX ICCPD Tamb supply voltage receive supply current transmit supply current supply current in power-down operating ambient temperature PARAMETER 26 10 30 MIN. 4.5 TYP. 4.8 31.5 12 +25

UAA2072M
respectively. The two phase shifted IFs are recombined and buffered to furnish the IF output signal. For instance, signals presented at the RF input at LO + IF frequency are rejected through this signal processing while signals at LO IF frequency can form the IF signal. An internal switch allows the use of infradyne or supradyne reception. The precision needed for this signal processing is achieved by compensating for process spreads and trimming for the choosen IF frequency and the LO band centre frequency via a 3-wire serial bus interface. The receiver section consists of a low-noise amplifier that drives a quadrature mixer pair. The IF amplifier has on-chip 45 and 135 phase shifting and a combining network for image rejection. The overall phase rotation is programmable for maximum image rejection at a given IF. The IF output drivers have differential open-collector type outputs. The LO part consists of an internal all-pass type phase shifter to provide quadrature LO signals to the receive mixers. The centre frequency of the phase shifter is adjustable for maximum image rejection in a given band. The all-pass filters outputs are buffered before being fed to the receive mixers. The transmit section consists of a down-conversion mixer and a transmit IF driver stage. In the transmit mode an internal LO buffer is used to drive the transmit IF down-conversion mixer. All RF and IF inputs or outputs are balanced, and 200 is used as standard RF impedance. A 3-pin unidirectional serial interface is used to program the circuits, using 16-bit words. This data bus allows compensation of process spreads, and is used to adjust for maximum image rejection performance at a given IF. It also offers a selection to reject the upper or lower image frequency and control over the different power-down modes. Special care has been taken for fast power-up switching.

MAX. 5.3 38 14 50 +85 V

UNIT mA mA A C

November 1994

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UAA2072M BLOCK DIAGRAM SSOP20 DESCRIPTION

UAA2072M

VERSION SOT266-1

plastic shrink small outline package; 20 leads; body width 4.4 mm

Fig.1 Block diagram.

November 1994

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

PINNING SYMBOL CLK DATA E VCC1 RFINA RFINB GND1 TXINA TXINB TEST RXON TXON TXOIFB TXOIFA VCC2 GND2 LOINB LOINA IFB IFA PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION serial bus clock serial bus data serial bus enable (active LOW) supply voltage for LNA, IF parts and TX mixer RF balance input A RF balance input B ground for synthesizer buffer and logic transmit mixer input A (balanced) transmit mixer input B (balanced) reserved for test purposes, should be connected to ground hardware power-on for receive parts hardware power-on for transmit mixer transmit mixer IF output B (balanced) transmit mixer IF output A (balanced) supply voltage for local oscillator parts ground for LO parts LO input B (balanced) LO input A (balanced) IF output (balanced) IF output (balanced)

UAA2072M

Fig.2 Pin configuration.

November 1994

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

FUNCTIONAL DESCRIPTION Receive section The circuit contains a low-noise amplifier followed by two high dynamic range mixers. These mixers are of the Gilbert-cell type, the whole internal architecture is fully differential. The local oscillator, shifted in phase to 45 and 135, mixes the amplified RF to create I and Q channels. The two I and Q channels are buffered, phase shifted by 45 and 135 respectively, amplified and recombined internally to realize the image rejection. The serial bus interface is used for tuning to maximum image rejection at a given IF. The contents of registers ip5 to ip0 and qp5 to qp0 (named IF phase adjustment words) are digital-to-analog converted in the DACI and DACQ blocks. The obtained internal voltages control the phase shift in I and Q; thus allowing them to be trimmed precisely to 45 and 135 at any given IF between 30 and 90 MHz. The gain in the I channel is slightly adjustable using the four bits ga3 to ga0 to allow compensation of small gain mismatches between I and Q.

UAA2072M
One bit (sbs) allows selection between infradyne or supradyne reception. Balanced signal interfaces are used for minimizing crosstalk due to package parasitics. The RF impedance level is 200 , choosen to minimize current consumption at best noise performance. The IF output is differential and of the open-collector type. Typical application will load the output with a differential 1 k load; i.e. a 1 k resistor load at each IF output, plus a 2 k resistor to x narrow band matching network (x being the input impedance of the IF filter). The path to VCC for the DC current is achieved via tuning inductors. The output voltage is limited to VCC + 3Vbe or 3 diode forward voltage drops. In the event of only one output being used, a 1 k resistive load in parallel with a tuning inductor to VCC, provides a matched 1 k output to the external IF filter. Fast switching, ON/OFF, of the receive section is controlled by the hardware input RXON or via the bus interface by changing the srx-bit in the internal register.

Fig.3 Block diagram, receive section.

November 1994

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

Local oscillator section The local oscillator (LO) input directly drives the two internal all-pass networks to provide quadrature LO to the receive mixers. The centre frequency of the receive band is adjustable by programming via the serial bus. The word lo5 to lo0 named LO Quad Centre Frequency Adjustment word is converted to an analog voltage in a digital-to-analog converter (DACL, see Fig.6). This voltage trims the all-pass network to the selected LO frequency range. To obtain the 30 dB specified image rejection the precision required on this trimming remains low. The LO input impedance is 100 differential. Switching from RX to TX or power-down mode has little influence on the LO input impedance. Transmit mixer

UAA2072M

This mixer is used for down-conversion to the transmit IF. Its inputs are coupled to the transmit RF and down-convert it to a modulated transmit IF frequency which is phase locked with the baseband modulation. The transmit mixer provides a differential input at 200 and a differential output driver buffer for a 1 k load. The IF outputs are low impedance (common collector type). Fast switching, ON/OFF, of the transmit section is controlled by the hardware input TXON or via the serial bus interface by changing the stx-bit in the internal register.

Fig.4 Block diagram, LO section.

Fig.5 Block diagram, transmit mixer.

November 1994

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

Serial bus interface The 3-wire serial bus interface allows control over the selective power-up of the transmit, receive and LO buffer circuits, the tuning of the LO quadrature and IF quadrature circuits and the selection of sideband rejection. The interface consists of a 16-bit programming register, three working latches and three DACs which provide the tuning voltages for the image rejection of the receive quadrature circuits. BUS FORMAT A 3-wire unidirectional bus is used to program the circuit, the 3 wires being: DATA, CLOCK (CLK) AND ENABLE (E). The timing diagram is illustrated in Fig.6. The data sent to the device is loaded in bursts framed by E. Programming clock edges and their corresponding data bits are ignored until E goes active LOW. The programmed information is loaded into the addressed working latch when E returns HIGH. Only the last 16 bits clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. If E returns HIGH while CLK is still LOW, the extra clock edge produced will cause data shift. The bus interface will not output any address recognition. Data is entered with the most significant bit first. The leading 12 bits make up the data field, while the trailing 4 bits comprise the address. The first bit entered is p1, the last bit p16. The bits in the programming registers and addresses are arranged as shown in Table 1.

UAA2072M

Fig.6 Block diagram, serial bus interface.

November 1994

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

Table 1 Register bit allocation REGISTER BIT ALLOCATION FIRST p1 dt11 X ga3 ip5 Table 2 BIT stx srx hpn sbs ga3 to ga0 lo5 to lo0 ip5 to ip0 qp5 to qp0 X p2 dt10 X ga2 ip4 p3 dt9 X ga1 ip3 p4 dt8 X ga0 ip2 p5 dt7 sbs X ip1 p6 dt6 X X ip0 p7 dt5 X lo5 qp5 p8 dt4 X lo4 qp4 p9 dt3 X lo3 qp3 p10 dt2 hpn lo2 qp2 p11 dt1 srx lo1 qp1 p12 dt0 stx lo0 qp0 p13 ad3 0 0 0 0

UAA2072M

LAST p14 ad2 0 0 0 0 p15 ad1 0 0 1 1 p16 ad0 0 1 0 1 DATA FIELD ADDRESS

This register is reserved for test purposes and should not be programmed

Bit allocation description REMARKS software transmit power-on software receive power-on hardware priority not (selects if power status of blocks is controlled via hardware or software) sideband select IF I channel gain adjustment LO quadrature centre frequency adjustment IF I channel phase adjustment IF Q channel phase adjustment not used 1 = power-up 1 = power-up 1 = soft priority 1 = upper sideband selected LOGIC 0 = power-down 0 = power-down 0 = hard priority 0 = lower sideband selected PRESET 0 0 0 0 0111 011111 011111 011111

November 1994

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

UAA2072M

Table 3 details the different power-up modes of the circuit. Attention should be paid to the hpn-bit. This bit enables the RXON and TXON pins to take any logic position when software programming for power-up is used. Table 3 Control of power status (note 1) REGISTER BIT STATUS hpn 0 0 0 0 1 1 1 1 Notes 1. X = dont care; x = HIGH or LOW logic voltage level applied at designated pin. 2. Circuit is operative in this mode but specification is NOT guaranteed. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC GND Pl(max) Tj(max) Pdis(max) Tstg supply voltage maximum power input maximum operating junction temperature maximum power dissipation in quiet air storage temperature PARAMETER 65 difference in ground supply voltage applied between GND1 and GND2 MIN. 9 0.6 +20 +150 250 +150 MAX. v V dBm C mW C UNIT stx X X X X 0 0 1 1 srx X X X X 0 1 0 1 EXTERNAL PIN LEVEL TXON LOW LOW HIGH HIGH x x x x RXON LOW HIGH LOW HIGH x x x x CIRCUITS POWER STATUS TRANSMIT off off on on (2) off off on on(2) RECEIVE off on off on(2) off on off on(2)

THERMAL CHARACTERISTICS SYMBOL Rth j-a HANDLING Every pin withstands the ESD test in accordance with MIL-STD-883C class 2 (method 3015.5). PARAMETER thermal resistance from junction to ambient in free air VALUE 120 UNIT K/W

November 1994

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

DC CHARACTERISTICS VCC = 4.8 V; Tamb = 25 C; unless otherwise specied. SYMBOL PARAMETER CONDITIONS MIN.

UAA2072M

TYP.

MAX.

UNIT

Pins: VCC1, VCC2, LOINA and LOINB VCC ICCRX ICCTX ICCPD Vth VIH VIL IIH IIL VI IO VI VO Note 1. The referenced inputs should be connected to a valid CMOS input level. supply voltage supply current supply current supply current in power-down mode over full temperature range receive mode active; DC tested transmit mode active; DC tested DC tested 4.5 26 10 3 0.3 pin at VCC 0.4 V pin at 0.4 V 1 1 4.8 31.5 12 5.3 38 14 50 VCC 0.8 +1 +1 V mA mA A

Pins: CLK, DATA, E, RXON, TXON and TEST CMOS threshold voltage HIGH level input voltage LOW level input voltage HIGH level static input current LOW level static input current note 1 1.25 V V V A A

Pins: RFINA and RFINB DC input voltage level receive mode enabled 1.7 2.1 2.4 V

Pins: IFA and IFB DC output current receive mode enabled 2.0 2.5 3.5 mA

Pins: TXINA and TXINB DC input voltage level transmit section enabled 1.8 2.2 2.5 V

Pins: TXOIFA and TXOIFB DC output voltage level transmit section enabled 2.5 2.9 3.4 V

November 1994

10

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

AC CHARACTERISTICS VCC = 4.8 V; Tamb = 30 to +85 C; unless otherwise specied. SYMBOL PARAMETER CONDITIONS MIN. 925 note 1 RF impedance to 1 IF output matched to 500 RF impedance to differential IF outputs matched to 1 k differential Grip G/T CP1RX IP2RX IP2DRX gain ripple as a function of RF frequency gain variation with temperature 1 dB input compression point 2nd order intercept point referenced to the RF input 2nd order intercept point referenced to the RF input differential 3rd order intercept point referenced to the RF input overall noise gure typical application IF output load impedance IF output load capacitance IF frequency range image frequency rejection image rejection at preset note 2 note 2 note 1 single-ended output; note 2 differential output; note 2 15 20 23 TYP.

UAA2072M

MAX. 960 26 29

UNIT MHz dB dB dB

Receive section (receive section enabled) ZRFI fRFI RLRF GCP RF input impedance RF input frequency return loss on matched RF input impedance conversion power gain balanced 200 20 23 26

20 26 +15

0.1 15 24.5 +22 +32

0.5 10

dB mdB/K dBm dBm dBm

IP3RX FRX ZL(IF) CL(IF) fIF fIR fIRp

note 2

18

15 4 500 71 45 35

5 2 90 50

dBm dB pF MHz MHz dB dB

RF input to differential IF output; notes 2 and 3 unbalanced unbalanced RF < LO RF > LO note 4 superheterodyne; fIF = 71 MHz; note 1 30 30 30 30

Local oscillator section (receive section enabled) fLO ZLO RLLO Pi(LO) RILO LO input frequency LO input impedance return loss on matched input (including standby mode) LO input power level reverse isolation LOIN to RFIN at LO frequency; note 1 balanced note 2 875 10 7 40 100 15 4 1050 +3 MHz dB dBm dB

November 1994

11

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

SYMBOL PARAMETER CONDITIONS MIN. balanced note 2 from 200 to 1 k output 880 15 8 40 20 10 double sideband; note 2 TXIN to LOIN; note 2 LOIN to TXIN; note 2 40 40 1000 200 20 10 15 +20 7 TYP.

UAA2072M

MAX.

UNIT pF MHz dB dB MHz dBm dBm dBm dB dB dB s

Transmit section (transmit section enabled) ZO ZL CL Zi(RF) fTXmix RLTX GCP fo(TX) CP1TX IP2TX IP3TX FTX RITX ITX Timing tstu Notes 1. Measured and guaranteed only on UAA2072M demonstration board at Tamb = +25 C. 2. Measured and guaranteed only on UAA2072M demonstration board. 3. This value includes printed-circuit board and balun losses. 4. This value might be dependent upon control values sent by a microcontroller via the serial bus. This performance is maintained over the RF band for a fixed phase rotation control word. start-up time of each block 1 5 20 TX IF output impedance TX IF load impedance maximum TX IF load capacitance TX RF input impedance TX mixer input frequency return loss on matched TX input conversion power gain TX mixer output frequency 1 dB input compression point 2nd order intercept point 3rd order intercept point noise gure reverse isolation isolation 200 2 915 12 200 12

November 1994

12

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

UAA2072M

TIMING CHARACTERISTICS Typical values measured at VCC = 4.8 V; Tamb = 25 C; maximum value conditions under maximum clock speed; unless otherwise specied. SYMBOL Serial bus interface fclk tr tf Tcy tSTART tEND tW tNEW tsu th clock frequency 75 13 MHz PARAMETER MIN. TYP. MAX. UNIT

Serial programming clock (pin CLK) rise time fall time clock period 10 10 40 40 ns ns ns

Enable programming (pin E) delay to rising edge of clock delay from last edge of clock minimum inactive pulse width delay from E inactive to new data 30 10 75 150 ns ns ns ns

Register serial input data (pin DATA) input data to CLK set-up time input data to CLK hold time 20 20 ns ns

Fig.7 Serial bus timing diagram.

November 1994

13

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

APPLICATION INFORMATION

UAA2072M

Figure 8 illustrates the electrical diagram of the UAA2072M Philips demonstration board. All matching is to 50 for measurement purposes. Different values will be used in a real application. Component manufacturers All surface mounted resistors and capacitors are manufactured by Philips Components. The small value capacitors are multi-layer ceramic with NPO dielectric. The inductors are manufactured by Coilcraft UK.

Fig.8 Application diagram.

November 1994

14

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

UAA2072M

R11 C30 C22 R7 R6 C20 C35 C33 L15 C36 C21 R5 L16 C34 C17 C18 L2 L1 C3 C2 L3 C4 C1 L5 L6 C8 C7 C6 IC1 L8 C12 C9 L7 C11 L9 C10 R1 R2 L14 C13 C14 L10

C29

C24 C23

C32 L4 C5 L13 C31

C28

SMD SIDE

C26 C25 C27 R9 R8 R10

UAA2072
MSB265

Fig.9 Printed-circuit board, SMD side.

SMD & SoIC - SOLDER SIDE

E 5 D OC 5V 7.5 V

Tx Rx Tx

UAA2072
MSB268

Fig.10 Printed-circuit board, SMD solder side.

November 1994

15

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

UAA2072M

IFB

IF out

IFA

X2

X1 UAA2072

IC2 R4 R3 L11 C16 C15 LO in RF in 5V

IMAGE REJECT RF FRONT END FOR GSM

C19 L12

Fig.11 Printed-circuit board, component side for image reject RF front-end for GSM.

CLK GND DATA BUS 5 V ENB NC

COMPONENT SIDE

7.5 V

GND

Fig.12 Printed-circuit board, component solder side for image reject RF front-end for GSM.

PHILIPS SEMICONDUCTORS IFB

X3

TX in TXoIF

COMPONENT SIDE
MSB266

UAA2072

IF

IFA

IMAGE REJECT RF FRONT END FOR GSM

PHILIPS SEMICONDUCTORS

5V LO in RF in

TXoIF

TX in

MSB267

November 1994

16

Philips Semiconductors

Product specication

Image rejecting front-end for GSM applications

DEMONSTRATION BOARD - PARTS LIST COMPONENT Resistors R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Capacitors C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 1.5 pF 33 pF 1.5 pF 33 pF 1.5 pF 1.5 pF 39 pF 39 pF 2.7 pF 2.7 pF 33 pF 33 pF 390 pF 390 pF 1 nF 120 pF 10 pF 10 pF 1 nF 33 pF 33 pF 33 pF 100 pF 1 nF 120 pF 120 pF 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 RFIN RFIN RFIN RFIN TXIN TXIN TXIN TXIN LOIN LOIN LOIN LOIN TXOIF TXOIF VCC2 VCC2 IFO IFO IF / 5 V CLK DATA E VCC1 VCC1 RXON TEST 180 180 1.2 k 1.2 k 560 k 560 k 560 k 680 k 680 k 680 k 120 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 TXOIF TXOIF IF IF CLK DATA E RXON TEST TXON 5 V BUS VALUE SIZE LOCATION COMPONENT Capacitors C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 Inductors L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 15 nH 15 nH 15 nH 15 nH 15 nH 27 nH 8.2 nH 8.2 nH 12 nH 10 H 390 nH 390 nH 220 nH 220 nH 150 nH 150 nH 0805 0805 0805 0805 0805 0805 0805 0805 0805 1008 1008 1008 1008 1008 0805 0805 120 pF 1 nF 100 nF 100 nF 8.2 pF 8.2 pF 33 pF 33 pF link link 0805 0805 1206 1206 0805 0805 0805 0805 0805 0805 VALUE SIZE

UAA2072M

LOCATION

TXON 5V 5 V regulator 5 V regulator TXOIF TXOIF IFO IFO IF/NOT USED IF/NOT USED

RFIN RFIN RFIN TXIN TXIN TXIN LOIN LOIN LOIN TXOIF/OPTIONAL IFO IFO TXOIF TXOIF IFO IFO

Other components COMPONENT IC1 IC2 SMA/RIM SMB X1, X2 and X3 DESCRIPTIONS UAA2072M 5 V regulator; type 78L05 sockets for RF and IF inputs/outputs 5 V socket (optional, in place of IC2) various 2.54 mm (0.1 inch) connectors

November 1994

17