A 2.

5dB NF Direct Conversion Receiver for 3G WCDMA

A 2.5dB NF Direct Conversion

Receiver for 3G WCDMA

Yen-Horng Chen

High Frequency IC Design Dept.

receiver operates from 2110 to 2170MHz and the

Abstract

transmitter operates from 1920 to 1980MHz, with a

A 2-GHz direct conversion receiver for wide-

bandwidth of 5MHz.

band code division multiple access (WCDMA) is

The choice of receiver architecture affects

presented. It integrates two low noise amplifiers

receiver performance [2], including sensitivity,

(LNAs),

selectivity, and power consumption. The super-

quadrature

mixer,

quadrature

LO

generation divider, baseband 5th-order channel-

heterodyne

select filters with programmable gain, and cutoff

sensitivity and selectivity, but the required off-chip

frequency auto calibration scheme. The chip was

filters make the receiver bulky and expensive. In

fabricated in TSMC 0.35m SiGe process with

direct conversion architecture, the channel-select

2.7V power supply. The noise figure is 2.5dB at the

filtering can be performed on-chip and the problem

102dB maximum voltage gain, and the iIP3 and

of image is circumvented, which is a promising

iIP2 are 19dBm and +25dBm, respectively. This

candidate that offers the highest level of integration.

receiver achieves 100dB programmable gain in 1dB

However, this architecture suffers from several

steps.

drawbacks [3], including dc offsets, LO self-mixing,

architecture

offers

the

highest

flicker noise, and even-order nonlinearities, which

1. Introduction

make the design of a high performance receiver a

challenging task.

The wide-band code division multiple access

This paper presents the design of a 2.5dB NF

(WCDMA) standard has been developed by the

direct

Third Generation Partnership Project as a standard

WCDMA RF system performance requirements

for

phone

with design margin. The paper is organized as

applications [1]. The WCDMA standard achieves

follows. Section 2 and section 3 describe the

higher data rates, channel capacity, and more

receiver architecture and the building blocks design

efficiency than current 2G systems. It uses a

in detail, respectively. Die photograph and the

frequency domain duplex (FDD) scheme, with the

measured results are given in section 4, and section

transmitter and receiver work simultaneously. The

5 summarizes this work.

116

next

generation

002

digital

mobile

conversion

receiver,

which

meets

all

A 2.5dB NF Direct Conversion Receiver for 3G WCDMA

2. Direct Conversion
Receiver Architecture

capacitive, substrate or bond wire coupling, which

brings about dc and low frequency distortion at
baseband, the LO port of this IC is drove at twice

In direct conversion topology, there is no

the desired channel frequency. The 2x LO is

significant filtering of RF signals outside the

divided on-chip to generate differential quadrature

receiving band before the mixer and baseband

LO signals for the mixers.

circuitry except in the duplexer, and the most

3. Building Blocks Design

serious signal may come from Tx leakage. These

lead to high linearity requirements, which burden
the system. In the implemented receiver this work,
as shown in Fig. 1, an external interstage filter is

3.1 LNA1 Design

inserted after the LNA1 to provide additional Tx

The

and out-of-band attenuation and thus relaxes the

first

LNA

(LNA1)

must

meet

linearity requirements. The resulting loss in the

simultaneous low noise and high linearity. A

signal path degrades system NF, therefore, a second

single-ended topology with two amplifier stages is

LNA is needed after the filter to scale down the

chosen to fulfill the gain, linearity requirements and

noise of the following circuit. The LNA2 provides

minimize the number of external components. Fig.

switched-gain function, depending on the strength

2 shows the simplified schematic of LNA1. The

of the input signal level. Channel selection and

designed

programmable gain are implemented at baseband.

common-emitter stages with inductive emitter

Gain resolution of 1dB and 77dB control range are

degeneration, mainly realized with the bonding

specified to keep the ADC margin and minimize

wires to the bonding pads. The selected transistor

the gain mis-adjustment. A passive pole at the

size in the first stage enables the trade-off between

output of the quadrature mixers also attenuates high

noise match and 50

frequency distortion terms such as the Tx leakage

collector current density is chosen to achieve the

and both in-band and out-of-band interference.

minimum noise figure. The second stage is

In order to minimize LO-RF leakage by

LNA1

is

composed

of

two

input match, and the

optimized for linearity. The output of each stage is

1/2
Duplexer

LNA1

Rx filter

2x LO

LNA2

Q
Quadrature Baseband filter
mixer
& PGA

Fig. 1

WCDMA direct conversion receiver architecture

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A 2.5dB NF Direct Conversion Receiver for 3G WCDMA

connected to the supply through an on-chip load

SAW filter output under high and low gain

inductor.

conditions.

In

order

to

minimize

the

noise

contribution from the lossy pad, ground-shielding

technique is used on the input signal pad.

The gain difference between the high and low

gain mode is about 23dB. In the high mode,

A linearizing bias circuit improving the gain

transistors Q1-Q4 act as cascode devices to provide

compression is used in the second stage design.

high gain. Resistors are added in parallel with the

Without the chock resistor (as R1 in the first stage),

resonator loads to mitigate the gain degradation

the average dc baseemitter voltage of Q6 decreases

resulted from the resonant frequency variation. In

as the input power increases, which compensates

the low gain mode, transistors Q1-Q4 are off and

the decreasing of the average dc baseemitter

MOS switches M1-M4 are on. The switches, M1 and

voltage of Q2 in large signal condition [4]. R2 is

M2, pass the input signal to the output directly. The

used to prevent the large input signal from

transistors M3 and M4 in series with capacitors are

changing the bias point of Q5. This active bias

used to improve the input match. LNA2 consumes

circuit provides a constant base bias voltage to Q2

no power in the low gain mode and hence reduces

and improves the gain compression.

the system power consumption. The LNA2 is

ac-coupled to the quadrature mixers, which can
filter out the low frequency distortion generated by
the second-order nonlinearities of the LNA.

Fig. 2

Simplified schematic of LNA1

Fig. 3

Simplified schematic of LNA2

3.2 LNA2 Design

The LNA2, as shown in Fig. 3, provides a high

3.3 Quadrature Mixers Design

gain mode amplifying the weak RF signal to

increase the receiver sensitivity and a low gain

Fig. 4 shows the double-balanced Gilbert cell

mode attenuating the strong RF signal and easing

down-conversion mixer. The bipolar input devices

the linearity requirements for the following blocks.

are properly chosen because of its good noise

It also performs impedance match for the balanced

performance. The bipolar transistors are also used

118

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A 2.5dB NF Direct Conversion Receiver for 3G WCDMA

as commutating switches since the required LO

low pass filter prototype with 0.1dB ripple, which

voltage swing is smaller and the critical flicker

meets the blocking and channel-select requirements.

noise can be minimized. Degeneration resistors are

The active-RC implementation is favored over

added to improve the linearity of the mixer. The

gm-C structures for its superior linearity and gain

output of the mixer has resistive loads in parallel

accuracy. The filter is realized in a leap-frog

with capacitors generating a low pass pole, which

architecture to take advantage of its low sensitivity

relaxes the linearity requirements of the baseband

of component values spread. The cutoff frequency

blocks. The external LO is divided by two and in

is placed at 2.25MHz, which is 17% higher than the

quadrature

wanted

on-chip

by

current-steering

toggle

signal

bandwidth

of

1.92MHz,

for

flip-flop [5]. The quadrature outputs are buffered

maintaining group delay variation at the passband

and ac-coupled to the mixer LO inputs.

edge less than 200ns, which can be equalized

digitally [6].

Fig. 5

Fig. 4

Baseband filter

This

Simplified schematic of down-conversion

mixer

baseband

filter

incorporates

77dB

programmable gain control that is accurately

variable in 1dB steps. The variable gain is

3.4 Analog Baseband Circuit Design

distributed in a variable gain preamp stage,

comprising

transconductance

stage

and

current-to-voltage resistors, with 24dB control

The analog baseband circuit consists of two
similar

signal

Chebyshev low pass filter with 42dB control range

with

and 6dB resolution and a final programmable

programmable gain, and dc offsets cancellation

amplifier has a control range of 11dB with 1dB

feedback loop (servo loop). The merged filtering

resolution.

and controlled gain stages minimize the number of

switched-resistor matrices, and filter frequency

amplifiers in the baseband circuit (Fig. 5) and

response maintains the same shape at all settings.

channel-select

channels,
filter,

each

including

range and 6dB resolution followed by the 5th-order

amplification

The

control

is

implemented

with

therefore minimize the current consumption. The

The servo loop, which nulls out the dc

transfer function is based on a 5th-order Chebyshev

component in the input and compensates the

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A 2.5dB NF Direct Conversion Receiver for 3G WCDMA

internal offsets of the baseband, is connected over

algorithm used to realize cutoff frequency auto

the whole baseband circuit excluding the last

calibration [7]. The capacitor matrix is charged

programmable amplifier. The servo amplifier is an

through a resistor by the supply voltage. Capacitor

active RC integrator with two 5nF off-chip

value is selected with the 3-bit capacitor matrix by

capacitors. The high pass pole is located at 7kHz

shifting the binary control code. As the capacitor

and the corner can be kept constant at all gain

value changes from high to low, the voltage

settings according to the adjustment of feedback

integrated by the capacitor during a fixed clock

amplifier.

cycle changes from low to high. When this voltage

Fig. 6 is the operational amplifier used in this

exceeds a reference voltage, which is generated by

baseband filter. It consists of two cascaded

a resistors divider, it means that the capacitor value

differential amplifiers and an emitter follower as

is equal to the setting value, and then calibration is

output stage. The first stage is a differential pair

done. The binary control code at this time is used to

with active loads, and a common mode feedback

set the filter cutoff frequency. The condition that

circuit determines its bias condition. The second

satisfies the calibration scheme can be expressed as

stage is a differential pair with resistor loads. Miller

TC

VCC VCC e R SCSel = VCC

compensation is utilized to ensure stability. The DC

gain is designed with 69dB and unity gain
bandwidth is 1GHz. The phase margin is 80o.

Fig. 6

Two-stage operational amplifier

R2
R1 + R 2

Even if the supply voltage (VCC) varies, the

calibration result would not be affected.

Fig. 7

Cutoff frequency auto calibration algorithm

The primary drawback of integrated active-RC

filters is the cutoff frequency variation due to the

4. Measured Performance

spread of RC product. The filter capacitors are built

of unit capacitors that are programmable with 3-bit

The receiver was fabricated in TSMC 0.35m

range, resulting in a tunable cutoff frequency that

SiGe process and packaged in plastic QFN package.

can

temperature

Fig. 8 is the die photograph. The chip area is

variations. The tuning is done automatically by

10.5mm2. A summary of measured results is given

digital calibration upon start-up. Fig. 7 is the

in Table 1. The maximum receiver voltage gain is

120

overcome

the

process

002

and

A 2.5dB NF Direct Conversion Receiver for 3G WCDMA

102dB and the total AGC range is 100dB. Fig. 9

shows the programmable gain performance, where
the accuracy is better than 0.3dB. The measured
NF without duplexer is 2.5dB, including the
interstage filter loss. The S11 of LNA1 is better
than 10dB at all gain settings, as shown in Fig. 10,
and with an iIP2 of +25dBm, iIP3 of 19dBm, and
iCP of 11.7dBm, this receiver meets the stringent
linearity requirements. After auto calibration of the
filter cutoff frequency, the adjacent channel is
rejected by 45dB. Fig. 11 shows the tuning of filter

Fig. 10

S11 of LNA1

Fig. 11

Tuning of baseband filter cutoff frequency

cutoff frequency.

Fig. 8

Die photograph

5. Conclusion
A low NF direct conversion receiver for the 3G
WCDMA cellular system has been described. This
receiver utilizes a combination of two LNAs and an
interstage

filter

to

alleviate

the

linearity

requirements of the mixers and baseband circuit

and also relaxes the system NF budge. The
Fig. 9

Programmable gain performance of the

receiver

complete receiver fulfills all the needed WCDMA

RF system performance requirements.

SoC Technical Journal

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A 2.5dB NF Direct Conversion Receiver for 3G WCDMA

Table 1 Summary of Measurement

newly proposed linearizing bias circuit, IEEE

Complete Receiver with interstage filter

LNA1

J. Solid-State Circuits, vol. 37, no. 9, pp. 1096-

20.5dB

1099, September 2002.

Gain

2dB ~ 102dB

S11

< -10dB

Noise Figure

2.5dB

1.65dB

iCP

-11.7dBm

-12.3dBm
-0.5dBm

iIP3(in)

-19dBm

iIP3(out)

-4dBm

iIP2(in)

+25dBm

Adj. Chan. Rejection

47dB

[5] Behzad Razavi, RF Microelectronics, chapter 8,

Prentice Hall PTR, 1998.
[6] A. Parssinen, J. Jussila, J. Ryynanen, L.
Sumanen, K.A.I. Halonen, A 2-GHz wideband direct conversion receiver for WCDMA

IQ Imbalance

< 0.5dB / < 2

Supply Voltage

2.7V

Current

46.5mA / 37.5mA

6.4mA

LNA

LNA2 & IQ Mixer

Baseband Filter

Gain

20dB / -3dB

-12.55dB ~ 64.45dB

Noise Figure

< 10dB

iCP

-10.3dBm / 9.3dBm

9.6dBm

iIP3

0dBm / 20.2dBm

4.1dBVrms

Circuits, vol. 38, issue 5, pp. 774-781, May

42.1dBVrms

2003.

applications, IEEE J. Solid-State Circuits, vol.

iIP2
Current

27.6mA / 18.6mA

34, issue 12, pp. 1893-1903, Dec. 1999.

[7] W. Khalil, T. Y. Chang, X. Jiang, S. R. Naqvi,
B. Nikjou, J. Tseng, A highly integrated
analog front-end for 3G, IEEE J. Solid-State

12.5mA

Author
6. References

Yen-Horng Chen was born in

[1] UE

Radio

Transmission

and

Reception

Taipei, Taiwan, 1977. He received

(FDD), Third-Generation Partnership Project

the B.S. in electrical engineering and

(3GPP), Tech. Spec. 25.101, v. 3.0.1, Apr.

the

2000.
Springer, RF Transceiver Architectures for
W-CDMA Systems like UMTS: State of the
and

Future

Trends,

International

Symposium on Acoustic Wave Devices, March

2001.

communication

direct-conversion receivers, IEEE Trans. on

Circuits and Systems II: Analog and Digital
Signal Processing, vol. 44, issue 6, pp. 428435, June 1997.
[4] Y. S. Noh and C. S. Park, PCS/W-CDMA
dual-band MMIC power amplifier with a

University, Taipei, in 1999 and 2001

respectively.
He worked on the design of microwave circuit and
MMIC from 1999 to 2001. In 2001, he joined SoC
Technology

Center

(STC),

Industrial

Technology

Research Institute (ITRI), HsinChu, Taiwan. His research

[3] Behzad Razavi, Design considerations for

122

in

engineering from National Taiwan

[2] R. Weigel, L. Maurer, D. Pimingsdorfer, A.

Art

M.S.

002

interests are in the area of wireless communication

integrated circuits. He is currently working on SiGe
BiCMOS WCDMA transceiver, DAB receiver and
CMOS radio frequency circuits.
E-mail: yenhorng@itri.org.tw
002