VEHICLE TRACKING AND ACCIDENT WARNING SYSTEM USING GPS AND ITS IMPLEMENTATION IN FPGA

A PROJECT REPORT Submitted by Reg. No. 30607106033 30607106044 30607106068 Students Name HUBERT VIJAY A KARTHIKEYAN N PRABHU K

in partial fulfillment for the award of the degree of BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION ENGINEERING JEPPIAAR ENGINEERING COLLEGE, CHENNAI
ANNA UNIVERSITY: CHENNAI-600 025. APRIL 2011

ANNA UNIVERSITY
CHENNAI-600 025

JEPPIAAR ENGINEERING COLLEGE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
JEPPIAAR NAGAR, RAJIV GANDHI SALAI, CHENNAI-600 119

BONAFIDE CERIFICATE
Certified that this project report VEHICLE TRACKING AND ACCIDENT WARNING IN SYSTEM FPGA is USING the GPS bonafide AND work ITS of

IMPLEMENTATION

__________________________________________________________________ who carried out the project work under my supervision.

PROJECT GUIDE

HEAD OF THE DEPARTMENT

Submitted for the examination held on ____________________

INTERNAL EXAMINER

EXTERNAL EXAMINER

CERTIFICATE OF EVALUATION

S. No.

Name of the student/s who have done the project

Title of the project VEHICLE

Name of the Supervisor with Designation

1 2 3

HUBERT VIJAY A KARTHIKEYAN N PRABHU K

TRACKING AND ACCIDENT WARNING SYSTEM MR.B.ARUN VIJAYA KUMAR,

USING GPS AND ITS ASST.PROFESSOR IMPLEMENTATION IN FPGA

The Reports of the project work submitted by the above students in partial fulfillment for the award of Bachelor of Engineering / Technology Degree in Electronics & Communication Engineering of Anna University, Chennai were evaluated and confirmed to be reports of the work by the above students and then evaluated.

INTERNAL EXAMINER

EXTERNAL EXAMINER

ACKNOWLEDGEMENT
We are very much indebted to the Chairman, Honble. Dr. JEPPIAAR, M.A., B.L., Ph.D., the Secretary Dr. P. Chinnadurai, M.Phil, B.Ed., Ph.D, the Director Dr. Regeena, B.Tech, M.B.A., Ph. D., the Principal Dr. Sushil Lal Das, M.Sc (Engg)., Ph.D.

We would also like to express our deep sense of gratitude to the Head of the Department and also to our guide Mr.B.Arun VijayaKumar, Asst.Professor for giving valuable suggestions for making this project a grand success.

We take this opportunity to express our sincere gratitude to our external guide Mr.Vivek, Project Guide, Vi Microsystems Pvt. Ltd, Chennai for giving us the opportunity to do this project under their esteemed guidance.

I also thank the teaching and non teaching staff members of the department of Electronics and Communication Engineering for their constant support.

ABSTRACT

In highly populated Countries like India, during accidents, people lose their lives due to unavailability of proper medical facilities at the right time. This project senses any accident in the vehicle and intimates pre-programmed numbers like the owner of the vehicle, ambulance, police etc. The GSM technology is used to send the position of the vehicle as a SMS to those numbers. And also the position of the vehicle can be obtained by the owner of the vehicle or anyone with proper permission by sending an SMS to a number. Most of the companies wants to keep track of their vehicles, with this equipment we can keep track of the vehicle by periodically sending SMS and the position of the vehicle is sent by the GSM modem as a SMS to the user. To know the position of the vehicle, the owner sends a request through a SMS. This is received by a GSM modem in the device and processed by the Spartan processor and the processor sends command to a GPS module in the device. The GPS module responds with coordinates position of the vehicle. This position is sent to the user as a SMS to the user with date, time, latitude and longitude positions. When there is an accident, the accelerometer sensor detects the change in position and sends a signal to the processor. The processor analyses the signal and finds there is an accident. It immediately sends the position of the vehicle and also the information that there is an accident, to pre-programmed numbers such as the owner of the vehicle, police, ambulance etc. So the ambulance arrives in time and the police can arrive in time to clear the traffic. This reduces the time taken by ambulance to arrive and also traffic can be cleared easily.

VI

TABLE OF CONTENTS
CHAPTER NO. ABSTRACT LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS 1 2 INTRODUCTION LITERATURE REVIEW
2.1 INTRODUCTION 2.2 PERSPECTIVE OF HAPSARI , SYAMSUDIN, PRAMANA 2.3 PERSPECTIVE OF ADNAN I. YAQZAN, ISSAM W. DAMAJ, AND RACHED N. ZANTOUT 2.4 CONCLUSION

TITLE

PAGE NO.
V

x xi xii
1 2 2 2 3 4

SYSTEM SUPPLY

ARCHITECTURE

AND

POWER
5

3.1 SYSTEM OVERVIEW 3.2 BLOCK DIAGRAM OF THE SYSTEM 3.3 POWER SUPPLY CIRCUIT 3.3.1 Linear Power Supply 3.3.2 Multi output Power Supply

5 5 6 7 8

VII

3.3.3 Regulator

GLOBAL SYSTEM FOR MOBILE(GSM)

4.1GSM OVERVIEW 4.2 GSM SPECIFICATIONS 4.3 GSM MODEM 4.4 AT COMMANDS

10 10 10 11 12 14 14 14 15 16 16 17 18 19 22 23

GPS (GLOBAL POSITIONING SYSTEM)

5.1 GPS BASICS 5.2 GPS PRINCIPLE 5.3 GPS RECEIVER 5.4 MAJOR COMPONENTS OF A GPS RECEIVER 5.5 FUNCTION OF GPS 5.6 RECEIVER OUTPUT 5.7 GPS DEVICE 5.8 RECEIVER FEATURES 5.9 HARDWARE CONNECTION 5.10 TYPES OF ERRORS

SPARTAN 3E BOARD
6.1 CONCEPT OF FIELD-PROGRAMMABLE GATE

24 24

VIII

ARRAY (FPGA) 6.2 FEATURES OF SPARTAN 3E BOARD 6.3 ARCHITECTURE OF SPARTAN 3E BOARD 27 28

ACCELEROMETER SENSOR
7.1 ACCELEROMETER BASICS 7.2 ADXL3XX 7.3 FEATURES OF ADXL3XX 7.4 FUNCTIONAL BLOCK DIAGRAM 7.5 THEORY OF OPERATION 7.6 APPLICATIONS OF ACCELEROMETER SENSOR 7.7 I2C BUS 7.7.1 Features of I2C bus 7.7.2 General Description of PCF 8591 7.7.3 Addressing 7.7.4 Control Byte

33 33 33 33 34 35 36 37 38 39 39 39 40 40 40 40 41

DESIGN OF SYSTEM SOFTWARE

8.1 XILINX SOFTWARE 8.2 XILINX WEB EDITION 8.3 VHDL 8.4 DESIGN FLOW IN VHDL

IX

8.5 CREATING A NEW PROJECT 8.6 PROGRAM

42 43 83 84

CONCLUSION REFERENCES

LIST OF TABLES TABLE NO.

5.1 6.1 6.2 6.3 7.1

TITLE
GPS Receiver Characteristics DIP switch connections with FPGA LED pin connections with FPGA LCD pin connections with FPGA Pin Function Descriptions of ADXL335

PAGE NO.
20 28 30 31 35

XI

LIST OF FIGURES FIGURE NO.

3.1 3.2 3.3 3.4 3.5 3.6 4.1 5.1 5.2 6.1 6.2 6.3 6.4 6.5 6.6 7.1 7.2 7.3 7.4 8.1 General Block Diagram Pin connections Block Diagram of Linear Power Supply Circuit Diagram of 5V Power Supply Multi Output Power Supply Regulator General Block Diagram of GSM MODEM GPS Principle GPS Device Example of a Logic Cell Logic Block Pin Locations Architecture of SPARTAN 3E Board SPARTAN 3E Board Pin Configuration of PCF 8951 Port Configuration of Spartan Processor Functional Block Diagram of ADXL335 Pin Configuration of ADXL335 Pin Configuration of IC 8951 Address Byte in I2C Design Flow in VHDL

TITLE

PAGE NO.
5 6 7 8 8 9 13 15 18 25 26 29 30 31 32 34 34 38 39 41

XII

LIST OF ABBREVIATIONS
GPS GSM SMS FPGA HDL VHDL AC DC IC TDMA FDMA GMSK LPC USB NMEA LUT CPLD VHSIC Global positioning system Global system for mobile Communications Short message service Field programmable gate array Hardware description language VHSIC Hardware description language Alternating current Direct current Integrated circuit Time Division multiple access Frequency division multiple access Gaussian Minimum Shift Keying Linear predictive coding Universal serial bus National Marine Electronics Association Lookup table Complex programmable logic device Very High Speed Integrated Circuit

CHAPTER 1

INTRODUCTION
There is a drastic increase in the number of vehicles in these days which also cause a steep rise in the number of accidents with a lot of people losing their lives. According to the World Health Organization, an estimated 1.2 million people lose their lives every year due to car accidents. India's road accident records 16 % of the world's road accident deaths, whereas India has only 1 % of the world's road vehicles. It is due to the increase in the number of vehicles without a subsequent increase in the road facilities required for it. In most of the accident cases, the victims lose their lives because of the unavailability of medical facilities at the right time. In large companies with a large number of vehicles, the drivers use t he companys vehicles even for their own purposes and impact a loss to the company. To solve problems like these, this project came into existence. This project is mainly used to track the position of the Vehicle by the owner or can also be used in the public transportation system by the people to know the location of the buses or trains. In case of any accident, the system sends automated messages to the pre-programmed numbers. We can send messages to any number of mobiles. The owner of the vehicle, Police to clear the traffic, Ambulance to save the people can be informed by this device. This uses a GPS (Global Positioning System) to know the exact position of the vehicle with an accuracy of a few feet. GSM is used to receive SMS from the user and reply the position of the vehicle through a SMS. A FPGA is used to control and co-ordinate all the parts used in this system. When there is any accident, an accelerometer sensor is triggered and it sends signal to the FPGA. The FPGA circuit processes the input and sends the appropriate output according to the programming done. This can also be used for other purposes such as asset tracking, Stolen Vehicle recovery, Fleet management, Field Service Management, Field Sales etc. Industries not traditionally known to use vehicle tracking systems have started to use it in creative ways to improve their processes or businesses. The hospitality industry has caught on to this technology to improve customer service. For example, a luxury hotel in Singapore has been known to install vehicle tracking system in their limousines to ensure they can welcome their VIPs when they reach the hotel. Vehicle tracking systems have also been used in food delivery and car rental companies.

CHAPTER 2

LITERATURE REVIEW
2.1 Overview:
The papers published in IEEE journals regarding vehicle position tracking system and its implementation on Fpga has helped to develop this project by analyzing the defects and using the effective ways from all resources available. The concept of the reference papers and how it helped in designing this system is described in the following subsections.

2.2 Perspective of Hapsari , Syamsudin, Pramana:

This project is referenced to the paper Design of vehicle position tracking system using short message services and its implementation on fpga done by Arias Tanti Hapsari , Eniman Y Syamsudin and, Imron Pramana. In this reference paper author used GPS module to receive the vehicular position and, short messaging service via mobile phone to receive user request and to send the vehicles position. These components are controlled by a system which is designed using VHDL on Altera MAX plus I1 software, and it is implemented on FPGA chip Altera UPlX demoboard (Altera FLEX 10KEPF). In this way the author gets the position of the vehicle and send it to any user who gives the request for tracking.

The objective of this project is to achieve a design of such system that can give information of the vehicle position every time there's a request for it. Safety and security is a major concern for all vehicle owners . This vehicle tracking system ensures safety and security of vehicle by tracking its position and sending it to owner or any people whenever it is requested by them.

And also GPS system ensures maximum accuracy in finding the vehicular position ranging within few feets. Using the mobile phone attached in the system ,the position of the vehicle is sent as short message service(SMS) to the requested people. The designed system is implemented on Altera UPlX demohoard. There are two testing and verification procedures of this system.

2.3 Perspective of Adnan I. Yaqzan, Issam W. Damaj, and Rached N. Zantout :

Another paper referenced is GPS-based Vehicle Tracking System-on-Chip. Modern powerful reconfigurable systems are suited in the implementation of various data-stream, dataparallel, and other applications . An application that needs real-time, fast, and reliable data processing is the global positioning system (GPS)-based vehicle tracking system (VTS). This system is designed using a system-on-chip (SOC) replacement of the current microcontroller-based implementation.

The proposed SOC is built on a field programmable gate array (FPGA) promising a cheaper design, a more cohesive architecture, a faster processing time and an enhanced system interaction. Reconfigurable systems enable extensive exploitation of computing resources. The reconfiguration of resources in different parallel topologies allows for a good matching with the inherent intrinsic parallelism of an algorithm or a specific operation.

The introduction of a new paradigm in hardware design called Reconfigurable Computing (RC) offers to solve any problem by changing the hardware configurations to offer the performance of dedicated circuits. Reconfigurable computing enables mapping software into hardware with the ability to reconfigure its connections to reflect thesoftware being run. The ability to completely reprogram the computers hardware implies that this new architecture provides immense scope for emulating different computer architectures.

As the complexity of FPGA-based designs grow, a need for a more efficient and flexible design methodology is required. One of the modern tools is Quartus II. It is a compiler, simulator, analyzer and synthesizer with a great capability of verification and is chosen to be used for this implementation.

It consists of two main parts, the Base Station (BS) and the Mobile Unit (MU). The BS consists of a PIC Microcontroller based hardware connected to the serial port of a computer. The MU is a self-contained PIC Microcontroller based hardware and a GPS module.

The latter would keep track of all the positions traversed by the vehicle and records them in its memory. The system has a great storage capacity, and could perform a significant recording with a considerable sampling rate. The mobile unit (MU) of the addressed Aram Locator consists of two communicating microcontrollers interfaced with memory. There is also a GPS unit and RF transceiver.

2.4 Conclusion:
With the help of advancement in technology using an FPGA controlled system we can easily track any object or vehicle which ensures safety for vehicle owners and also lots of uses for public transport system.

CHAPTER 3
DESIGN OF SYSTEM STRUCTURE AND POWER SUPPLY
3.1 System overview:
This project is custom made for the heavily populated countries like India. Accident warning System is used to save the persons life by making the medical facilities arriving in time. The Vehicular tracking System can be used by the owner of the Vehicle to track the position of the vehicle and also can be used by the people in public transportation Systems. In public transportation System, People can know the location of the buses or trains which will ease them. The location of the vehicle can be known by using a GPS receiver. Once the SMS is received from user, the response is sent to user via a GSM modem. An accelerometer sensor is used to detect any accident which will trigger a signal in case of any accidents. A FPGA Spartan processor is used to coordinate all the parts in this system according to the program done.

3.2 Block Diagram of the System:

GPS RECIEVER

Request from user

SIGNAL CONDITIONING CIRCUIT

FPGA SPARTAN 3E

GSM MODULE

ACCLEROMETER SENSOR

POWER SUPPLY CIRCUIT

Response from the system

Figure 3.1 General Block Diagram

Figure 3.2 : Pin connections

3.3 Power Supply Circuit:

In this block, we use transformers to convert domestic ac voltage to 9V ac. Then using diode rectifiers it is converted into suitable dc supply and given as input to the microprocessor and all other circuits in the equipment. Power Supply is the device that transfers electric power from a source to a load using electronic circuits. Power supplies are used in many industrial and aerospace applications and also in consumer products. Some of the requirements of power supplies are small size, lightweight, low cost, and high power conversion efficiency. In addition to these, some power supplies require the following: electrical isolation between the source and load, low harmonic distortion for the input and output waveforms, and high power factor (PF) if the source is ac voltage. Some special power supplies require controlled direction of power flow. Typical application of power supplies is to

7 convert utility's AC input power to a regulated voltage(s) required for electronic equipment. Depending on the mode of operation of power semiconductors power supply can be linear or switching.

3.3.1 Linear Power Supply:

A linear power supply is the oldest and simplest type of power supply. In these power supplies, electrical isolation can only be provided by bulky line frequency transformers. The ac source can be rectified with a bridge rectifier to get an uncontrolled dc, and then a dc-to-dc converter can be used to get a controlled dc output. The output voltage is regulated by dropping the extra input voltage across a series transistor (therefore, also referred to as a series regulator). They have very small output ripple, theoretically zero noise, large hold-up time (typically 12 ms), and fast response. The action of a transformer is such that a time-varying (AC) voltage or current is transformed to a higher or lower value, as set by the transformer turns ratio.

Figure3.3 Block Diagram of Linear Power Supply The transformer does not add power, so it follows that the power (V I) on either side must be constant. That is the reason that the winding with more turns has higher voltage but lower current, while the winding with less turns has lower voltage but higher current. The step down transformer converts the AC input with the higher level to some lower level. A bridge rectifier converts the AC voltage into DC voltage. A four-transistor converter (Bridge Rectifier) that can generate the highest output power than other types of rectifiers. The filter circuit resists the unwanted AC signals. The regulator down-convert a DC voltage to a lower DC voltage of the same polarity.

Figure 3.4 Circuit Diagram for 5V power Supply

3.3.2Multi output Power Supply:

It is also possible to generate multiple voltages using linear power supplies. In multi output power supply a single voltage must be converted into the required system voltages (for example, +5V, +12V and -12V) with very high power conversion efficiency.

Figure 3.5 Multi Output power Supply

3.3.3 Regulator:
Voltage regulators ICs are available with fixed (typically 5, 12 and 15V) or variable output voltages. They are also rated by the maximum current they can pass. Negative voltage regulators are available, mainly for use in dual supplies. Most regulators include some automatic protection from excessive current ('overload protection') and overheating ('thermal protection').

Figure 3.6 :Regulator

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CHAPTER 4

GLOBAL SYSTEM FOR MOBILE(GSM)

4.1 GSM overview:
Global System for Mobile Communications (GSM) is the worlds most popular standard for mobile telephony systems. The GSM Association estimates that 80% of the global mobile market uses the standard. GSM is used by over 1.5 billion people across more than 212 countries and territories. This ubiquity means that subscribers can use their phones throughout the world, enabled by international roaming arrangements between mobile network operators. GSM differs from its predecessor technologies in that both signalling and speech channels are digital, and thus GSM is considered a second generation (2G) mobile phone system. This also facilitates the wide-spread implementation of data communication applications into the system. The GSM standard has been an advantage to both consumers, who may benefit from the ability to roam and switch carriers without replacing phones, and also to network operators, who can choose equipment from many GSM equipment vendors. GSM also pioneered low-cost implementation of the short message service (SMS), also called text messaging, which has since been supported on other mobile phone standards as well.

4.2 GSM specifications:

Frequency: 900 MHz or 1800 MHz (Some countries in the Americas including Canada and the United States use the 850 MHz and 1900 MHz bands, 400 and 450 MHz frequency bands are assigned in some countries, notably Scandinavia) Modulation: Modulation is a form of change process where we change the input information into a suitable format for the transmission medium. We also changed the information by demodulating the signal at the receiving end.The GSM uses Gaussian Minimum Shift Keying (GMSK) modulation method. Access Methods: Because radio spectrum is a limited resource shared by all users, a method must be devised to divide up the bandwidth among as many users as possible.GSM chose a

11 combination of TDMA/FDMA as its method. The FDMA part involves the division by frequency of the total 25 MHz bandwidth into 124 carrier frequencies of 200 kHz bandwidth. One or more carrier frequencies are then assigned to each BS. Each of these carrier frequencies is then divided in time, using a TDMA scheme, into eight time slots. One time slot is used for transmission by the mobile and one for reception. They are separated in time so that the mobile unit does not receive and transmit at the same time.

Transmission Rate: The total symbol rate for GSM at 1 bit per symbol in GMSK produces 270.833 K symbols/second. The gross transmission rate of the time slot is 22.8 Kbps.

Frequency Band: The uplink frequency range specified for GSM is 933 - 960 MHz (basic 900 MHz band only). The downlink frequency band 890 - 915 MHz (basic 900 MHz band only).

Channel Spacing: This indicates separation between adjacent carrier frequencies. In GSM, this is 200 kHz.

Speech Coding: GSM uses linear predictive coding (LPC). The purpose of LPC is to reduce the bit rate. The LPC provides parameters for a filter that mimics the vocal tract. The signal passes through this filter, leaving behind a residual signal. Speech is encoded at 13 kbps. Duplex Distance: The duplex distance is 80 MHz Duplex distance is the distance between the uplink and downlink frequencies. A channel has two frequencies, 80 MHz apart.

4.3 GSM Modem:

A GSM modem is a specialized type of modem which accepts a SIM card, and operates over a subscription to a mobile operator, just like a mobile phone. From the mobile operator perspective, a GSM modem looks just like a mobile phone. A wireless modem behaves like a dial-up modem. The main difference between them is that a dial-up modem sends and receives data through a fixed telephone line while a wireless modem sends and receives data through radio waves. A GSM modem can be an external device or a PC Card / PCMCIA Card. Typically, an external GSM modem is connected to a computer through a serial cable or a USB cable. A GSM

12 modem in the form of a PC Card / PCMCIA Card is designed for use with a laptop computer. It should be inserted into one of the PC Card / PCMCIA Card slots of a laptop computer. Like a GSM mobile phone, a GSM modem requires a SIM card from a wireless carrier in order to operate. Both GSM modems and dial-up modems support a common set of standard AT commands. You can use a GSM modem just like a dial-up modem. In addition to the standard AT commands, GSM modems support an extended set of AT commands. These extended AT commands are defined in the GSM standards. With the extended AT commands, you can do things like: Reading, writing and deleting SMS messages. Sending SMS messages. Monitoring the signal strength. Monitoring the charging status and charge level of the battery. Reading, writing and searching phone book entries. SIM Phonebook management Fixed Dialling Number (FDN) Real time clock

The number of SMS messages that can be processed by a GSM modem per minute is very low -- only about six to ten SMS messages per minute.

4.3.1AT commands:
AT commands are also known as Hayes AT commands. There are different views to understand the meanings of "AT". Some call it "Attention Telephone", whereas others interpret it as "Attention Terminal" commands. AT commands allow giving instructions to both mobile devices and ordinary landline telephones. The commands are sent to the phone's modem, which can be a GSM modem or PC modem.. Different manufacturers may have different sets of AT commands. Fortunately, many AT commands are the same. Mobile device manufacturers may also give attention to operators to allow or not to allow some commands on phones.

13

Figure 4.1 General Block Diagram of GSM MODEM

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CHAPTER 5

GPS (GLOBAL POSITIONING SYSTEM)

5.1 GPS Basics:
The Global Positioning System (GPS) is a space-based global navigation satellite system (GNSS) that provides reliable location and time information in all weather and at all times and anywhere on or near the Earth when and where there is an unobstructed line of sight to four or more GPS satellites. It is maintained by the United States government and is freely accessible by anyone with a GPS receiver. When people talk about "a GPS," they usually mean a GPS receiver. The Global Positioning System (GPS) is actually a constellation of 27 Earth-orbiting satellites (24 in operation and three extras in case one fails). The U.S. military developed and implemented this satellite network as a military navigation system, but soon opened it up to everybody else. Each of these 3,000- to 4,000-pound solar-powered satellites circles the globe at about 12,000 miles (19,300 km), making two complete rotations every day. The orbits are arranged so that at anytime, anywhere on Earth, there are at least four satellites "visible" in the sky. A GPS receiver calculates its position by precisely timing the signals sent by GPS satellites high above the Earth. Each satellite continually transmits messages that include the time the message was transmitted precise orbital information (the ephemeris) the general system health and rough orbits of all GPS satellites (the almanac). The receiver uses the messages it receives to determine the transit time of each message and computes the distance to each satellite. These distances along with the satellites' locations are used with the possible aid of trilateration, depending on which algorithm is used, to compute the position of the receiver. This position is then displayed, perhaps with a moving map display or latitude and longitude; elevation information may be included. Many GPS units show derived information such as direction and speed, calculated from position changes.

5.2 GPS Principle:

The GPS satellites act as reference points from which receivers on the ground detect their position. The fundamental navigation principle is based on the measurement of pseudo ranges between the user and four satellites. Ground stations precisely monitor the orbit of every satellite and by measuring the travel time of the signals transmitted from the satellite four distances between receiver and satellites will yield accurate position, direction and speed. Though three - range

15 measurements are sufficient, the fourth observation is essential for solving clock synchronization error between receiver and satellite. Thus, the term pseudo ranges is derived. The secret of GPS measurement is due to the ability of measuring carrier phases to about 1/100 of a cycle equalling to 2 to 3 mm in linear distance. Moreover the high frequency L1 and L2 carrier signal can easily penetrate the ionosphere to reduce its effect. Dual frequency observations are important for large station separation and for eliminating most of the error parameters.

Figure 5.1 GPS Principle

5.3 GPS Receiver:

A GPS navigation device is any device that receives Global Positioning System (GPS) signals for the purpose of determining the device's current location on Earth. GPS devices provide latitude and longitude information, and some may also calculate altitude, although this is not considered sufficiently accurate or continuously available enough (due to the possibility of signal blockage and other factors) to rely on exclusively to pilot aircraft. GPS devices are used in military, aviation, marine and consumer product applications. The user segment is composed of hundreds of thousands of U.S. and allied military users of the secure GPS Precise Positioning Service, and tens of millions of civil, commercial and scientific users of the Standard Positioning Service.

16 GPS receivers are composed of an antenna, tuned to the frequencies transmitted by the satellites, receiver-processors, and a highly stable clock (often a crystal oscillator). They may also include a display for providing location and speed information to the user. A receiver is often described by its number of channels: this signifies how many satellites it can monitor simultaneously. Originally limited to four or five, this has progressively increased over the years so that, as of 2007, receivers typically have between 12 and 20 channels. GPS receivers may include an input for differential corrections, using the RTCM SC-104 format. This is typically in the form of an RS232 port at 4,800 bit/s speed. Data is actually sent at a much lower rate, which limits the accuracy of the signal sent using RTCM. Receivers with internal DGPS receivers can outperform those using external RTCM data. As of 2006, even low-cost units commonly include Wide Area Augmentation System (WAAS) receivers. Many GPS receivers can relay position data to a PC or other device using the NMEA 0183 protocol.

5.4 Major Components of a GPS Receiver:

The main components of a GPS receiver are Antenna with pre-amplifier RF section with signal identification and signal processing Micro-processor for receiver control, data sampling and data processing oscillator Power supply User interface, command and display panel Memory, data storage

5.5 Function Of GPS:

It is a "constellation" of twenty-four 20,000km high GPS satellites. The satellites are distributed on 6 orbits, 4 per orbit. Every satellite makes a complete rotation of the Earth every 12 hours. Every satellite possesses an atomic clock, allowing a very precise measure of time. They emit on two different frequencies: L1: 1575 MHz and L2: 1227 MHz. L2 being reserved for the American Army. Every satellite thus sends ceaselessly a code of 1500 bits, containing numerous data such as the time at which the code is to be sent, the position of the satellite, its state, the position of the other satellites... This data allows the receiver to calculate its position. Each GPS satellite transmits radio signals that enable the GPS receivers to calculate where its (or your vehicles) location on the Earth and convert the calculations into geodetic latitude, longitude and

17 velocity. A receiver needs signals from at least three GPS satellites to pinpoint your vehicles position.

GPS Receivers commonly used in most Vehicle tracking systems can only receive data from GPS Satellites. They cannot communicate back with GPS or any other satellite.

A system based on GPS can only calculate its location but cannot send it to central control room. In order to do this they normally use GSM-GPRS Cellular networks connectivity using additional GSM modem/module.Two levels of navigation and positioning are offered by the Global Positioning System: The Standard Positioning Service (SPS). and the Precise Positioning Service (PPS). The Precise Positioning Service is a highly accurate positioning, velocity and timing service that is designed primarily for the military and other authorized users, although under certain conditions can be used by civilians who have specialized equipment. The Standard Positioning Service offers a base-line accuracy that is much lower than the PPS, but is available to all users with even the most inexpensive receivers. As we will see, there are various techniques available that substantially increase the SPS accuracy, even well beyond that which is offered by the PPS. Published specifications for the Precise Positioning Service are: 17.8 meter horizontal accuracy 27.7 meter vertical accuracy 100 nanosecond time accuracy

Published specifications for the Standard Positioning Service are: 100 meter horizontal accuracy 156 meter vertical accuracy 167 nanoseconds time accuracy.

5.6 RECEIVER OUTPUT:

Typically receivers provide two different formats.

1. NMEA (Nation Marine Electronics Association) ASCII Format Defines a set of standard messages. 2.Proprietary Format

18 Typically Binary No limit on information transmitted Receiver output is related to position, velocity and time. The output in the following

Position: Latitude: degrees: minutes: seconds Longitude: degrees: minutes: seconds Altitude m Velocity: Speed knots Heading degrees Time (UTC): Date dd/mm/yy Time hh/mm/ss.sss GPS receiver gives the latitude, longitude, date, time, speed of the satellite, no of satellites on view etc The National Marine Electronics Association (NMEA) has developed a specification that defines the interface between various pieces of marine electronic equipment. The standard permits marine electronics to send information to computers and to other marine equipment. A full copy of this standard is available for purchase at their web site. None of the information on this site comes from this standard and I do not have a copy. Anyone attempting to design anything to this standard should obtain an official copy.

5.7 GPS DEVICE:

Figure 5.2 GPS Device

19

5.8 RECEIVER FEATURES:

12 parallel channel L1 Band SPS GPS. Very good acquisition and good tracking sensitivity. Antenna open short detection/protection Tracking sensitivity:-154dB-m Acquisition sensitivity 148dB-m 5v and 3.3volt option available.

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Table 5.1 GPS Receiver Characteristics

21

Most computer programs that provide real time position information understand and expect data to be in NMEA format. This data includes the complete PVT (position, velocity, time) solution computed by the GPS receiver. The idea of NMEA is to send a line of data called a sentence that is totally self-contained and independent from other sentences. There are standard sentences for each device category and there is also the ability to define proprietary sentences for use by the individual company. All of the standard sentences have a two-letter prefix that defines the device that uses that sentence type. (For GPS receivers the prefix is GP.) This is followed by a three-letter sequence that defines the sentence contents. In addition NMEA permits hardware manufactures to define their own proprietary sentences for whatever purpose they see fit. All proprietary sentences begin with the letter P and are followed with 3 letters that identifies the manufacturer controlling that sentence. For example a Garmin sentence would start with PGRM and Magellan would begin with PMGN. Each sentence begins with a '$' and ends with a carriage return/line feed sequence and can be no longer than 80 characters of visible text (plus the line terminators). The data is contained within this single line with data items separated by commas. The data itself is just ASCII text and may extend over multiple sentences in certain specialized instances but is normally fully contained in one variable length sentence. The data may vary in the amount of precision contained in the message. For example time might be indicated to decimal parts of a second or location may be show with 3 or even 4 digits after the decimal point. Programs that read the data should only use the commas to determine the field boundaries and not depend on column positions. There is a provision for a checksum at the end of each sentence, which may or may not be checked by the unit that reads the data. The checksum field consists of a '*' and two hex digits representing an 8 bit exclusive OR of all characters between, but not including, the '$' and '*'. A checksum is required on some sentences. There have been several changes to the standard but for GPS use the only ones that are likely to be encountered are 1.5 and 2.0 through 2.3. These just specify some different sentence configurations which may be peculiar to the needs of a particular device thus the GPS may need to be changed to match the devices being interfaced to. Some GPS's provide the ability configure a custom set the sentences while other may offer a set of fixed choices. Many GPS receivers simply output a fixed set of sentences that cannot be changed by the user. The current version of the standard is 3.01. I have no specific information on this version, but I am not aware of any GPS products that require conformance to this version.

22

5.8 Hardware Connection:

The hardware interface for GPS units is designed to meet the NMEA requirements. They are also compatible with most computer serial ports using RS232 protocols, however strictly speaking the NMEA standard is not RS232. They recommend conformance to EIA-422. The interface speed can be adjusted on some models but the NMEA standard is 4800 b/s (bit per second rate) with 8 bits of data, no parity, and one stop bit. All units that support NMEA should support this speed. Note that, at a b/s rate of 4800, you can easily send enough data to more than fill a full second of time. For this reason some units only send updates every two seconds or may send some data every second while reserving other data to be sent less often. In addition some units may send data a couple of seconds old while other units may send data that is collected within the second it is sent. Generally time is sent in some field within each second so it is pretty easy to figure out what a particular GPS is doing. Some sentences may be sent only during a particular action of the receiver such as while following a route while other receivers may always send the sentence and just null out the values. Other difference will be noted in the specific data descriptions defined later in the text. At 4800 b/s you can only send 480 characters in one second. Since an NMEA sentence can be as long as 82 characters you can be limited to less than 6 different sentences. The actual limit is determined by the specific sentences used, but this shows that it is easy to overrun the capabilities if you want rapid sentence response. NMEA is designed to run as a process in the background spitting out sentences which are then captured as needed by the using program. Some programs cannot do this and these programs will sample the data stream, then use the data for screen display, and then sample the data again. Depending on the time needed to use the data there can easily be a lag of 4 seconds in the responsiveness to changed data. This may be fine in some applications but totally unacceptable in others. For example a car traveling at 60 mph will travel 88 feet in one second. Several second delays could make the entire system seem unresponsive and could cause you to miss your turn.

The NMEA standard has been around for many years (1983) and has undergone several revisions. The protocol has changed and the number and types of sentences may be different depending on the revision. Most GPS receivers understand the standard, which is called: 0183 version 2. This standard dictates a transfer rate of 4800 b/s. Some receivers also understand older standards. The oldest standard was 0180 followed by 0182, which transferred data at 1200 b/s. Some receivers also understand an earlier version of 0183 called version 1.5. Some Garmin units and other

23 brands can be set to 9600 for NMEA output or even higher but this is only recommended if you have determined that 4800 works ok and then you can try to set it faster. Setting it to run as fast as you can may improve the responsiveness of the program.

5.9 Types of Errors:

There are two types of positioning errors: correctable and non-correctable. Correctable errors are the errors that are essentially the same for two GPS receivers in the same area. Noncorrectable errors cannot be correlated between two GPS receivers in the same area.

Correctable Errors Sources of correctable errors include satellite clock, ephemeris data and ionosphere and tropospheric delay. If implemented, SA may also cause a correctable positioning error. Clock errors and ephemeris errors originate with the GPS satellite. A clock error is a slowly changing error that appears as a bias on the pseudorange measurement made by a receiver. An ephemeris error is a residual error in the data used by a receiver to locate a satellite in space. Ionosphere delay errors and tropospheric delay errors are caused by atmospheric conditions. Ionospheric delay is caused by the density of electrons in the ionosphere along the signal path. A tropspheric delay is related to humidity, temperature, and altitude along the signal path. Usually, a tropospheric error is smaller than an ionospheric error. Another correctable error is caused by SA which is used by U.S Department of Defence to introduce errors into Standard Positioning Service (SPS) GPS signals to degrade fix accuracy. The amount of error and direction of the error at any given time does not change rapidly. Therefore, two GPS receivers that are sufficiently close together will observe the same fix error, and the size of the fix error can be determined.

Non-Correctable Errors Non-correctable errors cannot be correlated between two GPS receivers that are located in the same general area. Sources of non-correctable errors include receiver noise, which is unavoidably inherent in any receiver, and multipath errors, which are environmental. Multi-path errors are caused by the receiver seeing reflections of signals that have bounced off of surrounding objects. The submeter antenna is multipath-resistant; its use is required when logging carrier phase data. Neither error can be eliminated with differential, but they can be reduced substantially with position fix averaging.

24

CHAPTER 6

SPARTAN 3E BOARD
6.1 Concept of Field-programmable Gate Array (FPGA): A Field-programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of the portion of the design and the low nonrecurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications. FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together" somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. In addition to digital functions, some FPGAs have analog features. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow. Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signalling channels. A few "mixed signal FPGAs" have integrated peripheral Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip. Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric. Architecture of FPGA:

25 The most common FPGA architecture consists of an array of logic blocks (called Configurable Logic Block, CLB, or Logic Array Block, LAB, depending on vendor), I/O pads, and routing channels. Generally, all the routing channels have the same width (number of wires). Multiple I/O pads may fit into the height of one row or the width of one column in the array. An application circuit must be mapped into an FPGA with adequate resources. While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. For example, a crossbar switch requires much more routing than a systolic array with the same gate count. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of LUTs and IOs can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs. In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE, Slice etc). A typical cell consists of a 4-input Lookup table (LUT), a Full adder (FA) and a D-type flip-flop, as shown below. The LUTs are in this figure split into two 3-input LUTs. In normal mode those are combined into a 4-input LUT through the left mux. In arithmetic mode, their outputs are fed to the FA. The selection of mode is programmed into the middle mux. The output can be either synchronous or asynchronous, depending on the programming of the mux to the right, in the figure example. In practice, entire or parts of the FA are put as functions into the LUTs in order to save space.

Figure 6.1 Example of a logic cell

ALMs and Slices usually contain 2 or 4 structures similar to the example figure, with some shared signals.CLBs/LABs typically contain a few ALMs/LEs/Slices.In recent years, manufacturers have started moving to 6-input LUTs in their high performance parts, claiming increased performance.

26

Since clock signals (and often other high-fanout signals) are normally routed via specialpurpose dedicated routing networks in commercial FPGAs, they and other signals are separately managed.

For this example architecture, the locations of the FPGA logic block pins are shown below.

Figure 6.2 Logic Block Pin Locations Each input is accessible from one side of the logic block, while the output pin can connect to routing wires in both the channel to the right and the channel below the logic block.Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it. Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the W wires (where W is the channel width) in the horizontal channel immediately below it. FPGA designing and Programming: To define the behavior of the FPGA, the user provides a hardware description language (HDL) or a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. However, schematic entry can allow for easier visualisation of a design. Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-and-route software. The user will validate the map, place and route results via timing analysis, simulation, and

other verification methodologies. Once the design and validation process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA. Going from schematic/HDL source files to actual configuration: The source files are fed to a software suite from the FPGA/CPLD vendor that through different steps will produce a file. This file is then

27 transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM. The most common HDLs are VHDL and Verilog, although in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level through the introduction of alternative languages. National Instrument's Lab VIEW graphical programming language ( sometimes referred to as "G" ) has an FPGA add-in module available to target and program FPGA hardware. The LabVIEW approach drastically simplifies the FPGA programming process. To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP suppliers (rarely free and typically released under proprietary licenses). Other predefined circuits are available from developer communities such as Open Cores (typically released under free and open source licenses such as the GPL, BSD or similar license), and other sources. In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values backannotated onto the netlist.

6.2 Features of SPARTAN 3E Board:

* 100,000-gate Xilinx Spartan-3E XC3S100E FPGA in a 144-Thin Quad Flat Pack package (XC3S100E-TQ144) 2,160 logic cell equivalents Four 18K-bit block RAMs (72K bits) Four 18x18 pipelined hardware multipliers Two Digital Clock Managers (DCMs)

* 32 Mbit Intel Strata Flash * 3 numbers of 20 pin header to interface VLSI based experiment modules * 8 input Dip Switches

28 * 8 output Light Emitting Diodes(LEDs) * On Board programmable oscillator (3 to 200 MHz) * 16x2 Alphanumeric LCD * RS232 UART * 4 Channel 8 Bit I2C based ADC & single Channel DAC * PS/2 Keyboard/Mouse * Prototyping area for user applications * On Board configuration Flash PROM XCF01S

6.3 Architecture of Spartan 3E Board:

Power Switch: The Spartan-3E Low Cost Kit has a slide power switch. Moving the power switch Up for Power On and down for power off. Configuration Switch: The Spartan-3E Low Cost Kit has a push button Switch to Configure the FPGA from Xilinx Serial Flash PROM. Input Switches: The Spartan-3E Low Cost Kit has 8 way Dip switches for giving inputs to the FPGA i/o lines.

Dip Switch connections with FPGA:

Table 6.1 DIP switch connections with FPGA

29

Figure 6.3 Architecture of SPARTAN 3E Board

30

Figure 6.4 SPARTAN 3E Board

Output LEDs: The Spartan-3E Low Cost Kit has 8 individual surface-mount LEDs. The LEDs are labelled L3 to L10.The cathode of each LED connects to ground. To light an individual LED, drive the associated FPGA control signal High. LED connections with FPGA:

Table 6.2 LED pin connections with FPGA

31 Character LCD Screen: The Spartan-3E Low Cost Kit prominently features a 2-line by 16-character liquid crystal display (LCD). The FPGA controls the LCD via the 8-bit data interface.

LCD Connections with FPGA:

Table 6.3 LCD pin connections with FPGA Analog to digital converter & digital to Analog converter:

Figure 6.5 Pin Configuration of PCF 8591 The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device with four analog inputs, one analog output and a serial I2C-bus interface. Three address pins A0, A1 and A2 are used for programming the hardware address, allowing the use of up to eight devices connected to the I2C-bus without additional hardware. Address, control and data to and from the device are transferred serially via the two-line bidirectional I2C-bus. The functions of the device include analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The maximum conversion rate is given by the maximum speed of the I2C-bus.

32

Figure 6.6 : Port Configuration of Spartan Processor

33

CHAPTER 7

ACCELEROMETER SENSOR
7.1 Accelerometer Basics:
Accelerometers are sensors or transducers that measure acceleration. Accelerometers generally measure acceleration forces applied to a body by being mounted directly onto a surface of the accelerated body. Accelerometers are useful in detecting motion in objects. An accelerometer measures force exerted by a body as a result of a change in the velocity of the body. A moving body possesses an inertia which tends to resist change in velocity. It is this resistance to change in velocity that is the source of the force exerted by the moving body. This force is directly proportional to the acceleration component in the direction of movement when the moving body is accelerated. The motion is detected in a sensitive portion of the accelerometer. This motion is indicative of motion in the larger object or application in which the accelerometer is mounted. Thus, a sensitive accelerometer can quickly detect motion in the application.

7.2 ADXL3XX:
3 Axis Acceleration Sensor Board based on ADXL3XX from Analog devices. It is a first generation 3 axis acceleration sensor. User could get acceleration value of X, Y, and Z axis. And it is widely used in shock, slope, and moving detection. Output sensitivity could be select by simply set voltage level on few pins. The output of MMA7260Q is analog mode, so you need a A/D converter to read the acceleration value.

7.3 FEATURES OF ADXL3XX :

3-axis sensing Small, low profile package 4 mm 4 mm 1.45 mm LFCSP Low power : 350 mA (typical) Single-Supply operation: 1.8 V to 3.6 V 10,000 g shock survival Excellent temperature stability BW adjustment with a single capacitor per axis RoHS/WEEE lead-free compliant

34

7.4 Functional Block Diagram:

Figure 7.1 Functional Block Diagram of ADXL335

Pin Configuration:

Figure 7.2 Pin Configuration of ADXL335

35

Table 7.1 Pin Function Descriptions of ADXL335

7.5 THEORY OF OPERATION :

The ADXL335 is a complete 3-axis acceleration measurement system. The ADXL335 has a measurement range of 3 g mini-mum. It contains a polysilicon surface-micromachined sensor and signal conditioning circuitry to implement an open-loop acceleration measurement architecture. The output signals are analog voltages that are proportional to acceleration. The accelerometer can measure the static acceleration of gravity in tilt-sensing applications as well as dynamic acceleration resulting from motion, shock, or vibration. The sensor is a polysilicon surface-micromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. Deflection of the structure is meas-ured using a differential capacitor that consists of independent fixed plates and plates attached to the moving mass. The fixed plates are driven by 180 out-of-phase square waves. Acceleration deflects the moving mass and unbalances the differential capacitor resulting in a sensor output whose amplitude is proportional to acceleration. Phase-sensitive demodulation techniques are then used to determine the magnitude and direction of the acceleration. The demodulator output is amplified and brought off-chip through a 32 k resistor. The user then sets the signal bandwidth of the device by adding a capacitor. This filtering improves measurement resolution and helps prevent aliasing.

36 Performance : Rather than using additional temperature compensation circuit, innovative design techniques ensure that high performance is built in to the ADXL335. As a result, there is no quantization error or nonmonotonic behavior, and temperature hysteresis is very low (typically less than 3 m g over the 25C to +70C temperature range). Setting The Bandwidth Using Cx, Cy, And Cz : The ADXL335 has provisions for band limiting the XOUT, YOUT, and ZOUT pins. Capacitors must be added at these pins to imple-ment low-pass filtering for antialiasing and noise reduction. The equation for the 3 dB bandwidth is F3 dB = 1/(2(32 k) C(X, Y, Z)) or more simply F3 dB = 5 F/C(X, Y, Z) The tolerance of the internal resistor (RFILT) typically varies as much as 15% of its nominal value (32 k), and the bandwidth varies accordingly. A minimum capacitance of 0.0047 F for CX, CY, and CZ is recommended in all cases.

7.6 Applications of Accelerometer Sensor:

Tilt-sensing applications Mobile devices Gaming systems Disk drive protection Image stabilization Sports and health devices Accelerometers have uses in many commercial, military, and scientific applications including inertial navigation, vehicular safety systems such as airbags, ride comfort control, platform stabilization, tilt sensing, and vibration monitoring. Accelerometers find use in automobile suspension systems, vehicle air bag systems, anti-lock brake systems (ABS), vibrometers, and computer hard disc drivers, smart detonation systems for bombs and missiles and machine vibration monitors. A disk drive employs an accelerometer to detect disturbances affecting an actuator arm while attempting to maintain a head over a centreline of a track. The output of the accelerometer is used as a feed-forward compensation signal in a

servo control system to effectively reject the disturbance.

37 Accelerometers have been employed to help determine the acceleration or deceleration of a ship or plane, to monitor the forces being applied to an apparatus or device, such as a car, train, bus, and the like. Accelerometers are used as a GPS-aid to obtain position information when the GPS receivers lose their line-of-sight with the satellites. Accelerometers are widely used to monitor the vibration of electrical motors, pumps and the like in industrial applications, especially in continuous production operations. Changes in vibration levels, particularly in rotating machinery, provide an advance warning of problems such as excessive wear or an

approaching bearing failure. Electromechanical accelerometers have been used in washing machines to detect an unbalanced load by sensing the sharp accelerations and decelerations of the spinning tub as it rocks back and forth. An accelerometer can measure changes in a patient's physical activity. The physical changes are detected by the accelerometer and algorithmically interpreted by circuitry within the pulse generator to produce a modified therapy that is correct for the current activity level. The accelerometer is placed within the implantable medical device. Accelerometers are also used to detect and record environmental data. In particular, accelerometers are often used in seismic applications to gather seismic data. In the area of oilfield investigation and earth formation characterization, accelerometers may be deployed in wire line applications, logging while drilling applications or using coiled tubing.

7.7 I2C BUS:

The I2C bus was designed by Philips in the early '80s to allow easy communication between components which reside on the same circuit board. Philips Semiconductors migrated to NXP in 2006. The name I2C translates into "Inter IC". Sometimes the bus is called IIC or IC bus. The original communication speed was defined with a maximum of 100 kbit per second and many applications don't require faster transmissions. For those that do there is a 400 kbit fastmode and since 1998 - a high speed 3.4 Mbits option available. Recently, fast mode plus a transfer rate between this has been specified.

38 I2C is not only used on single boards, but also to connect components which are linked via cable. Simplicity and flexibility are key characteristics that make this bus attractive to many applications. Most significant features include:

Only two bus lines are required No strict baud rate requirements like for instance with RS232, the master generates a bus clock

Simple

master/slave

relationships

exist

between

all

components

Each device connected to the bus is software-addressable by a unique address

I2C is a true multi-master bus providing arbitration and collision detection

7.7.1 FEATURES OF I2C BUS:

Single power supply Operating supply voltage 2.5 V to 6 V Low standby current Serial input/output via I2C-bus Address by 3 hardware address pins Sampling rate given by I2C-bus speed 4 analog inputs programmable as single-ended or Differential inputs Auto-incremented channel selection Analog voltage range from VSS to VDD On-chip track and hold circuit 8-bit successive approximation A/D conversion Multiplying DAC with one analog output.

Figure 7.3 : Pin Configuration of IC 8591

39

7.7.2 GENERAL DESCRIPTION OF PCF8591:

The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device with four analog inputs, one analog output and a serial I2C-bus interface. Three address pins A0, A1 and A2 are used for programming the hardware address, allowing the use of up to eight devices connected to the I2C-bus without additional hardware. Address, control and data to and from the device are transferred serially via the two-line bidirectional I2C-busThe maximum conversion rate is given by the maximum speed of the I2C-bus.

7.7.3 Addressing:
Each PCF8591 device in an I2C-bus system is activated by sending a valid address to the device. The address consists of a fixed part and a programmable part. The programmable part must be set according to the address pins A0, A1 and A2. The address always has to be sent as the first byte after the start condition in the I2C-bus protocol. The last bit of the address byte is the read/writebit which sets the direction of the following data transfer.

Fig 7.4 : Address Byte in I2C 7.7.4 Control byte: The second byte sent to a PCF8591 device will be stored in its control register and is required to control the device function. The upper nibble of the control register is used for enabling the analog output, and for programming the analog inputs as single-ended or differential inputs. The lower nibble selects one of the analog input channels defined by the upper nibble. If the autoincrement flag is set the channel number is incremented automatically after each A/D conversion. If the auto-increment mode is desired in applications where the internal oscillator is used, the analog output enable flag in the control byte (bit 6) should be set. This allows the internal oscillator to run continuously, thereby preventing conversion errors resulting from oscillator start-up delay. The analog output enable flag may be reset at other times to reduce quiescent power consumption. The selection of a non-existing input channel results in the highest available channel number being allocated. Therefore, if the auto-increment flag is set, the next selected channel will be always channel 0. The most significant bits of both nibbles are reserved for future functions and have to be set to 0. After a Power-on reset condition all bits of the control register are reset to 0. The D/A converter and the oscillator are disabled for power saving. The analog output is switched to a highimpedance state.

40

CHAPTER 8

DESIGN OF SYSTEM SOFTWARE

8.1 Xilinx SOFTWARE :
Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Xilinx, Inc. (NASDAQ: XLNX) is a supplier of programmable logic devices. It is known for inventing the field programmable gate array (FPGA) and as the first semiconductor company with a fabless manufacturing model. Founded in Silicon Valley in 1984, the company

is headquartered in San Jose, California, U.S.A.; Dublin, Ireland; Singapore; and Tokyo, Japan. The company has corporate offices throughout North America, Asia and Europe.

8.2 XilinX Web Edition:

The Web Edition is a free version of Xilinx ISE that can be downloaded or delivered by mail for free. This edition provides synthesis and programming for a limited number of Xilinx devices. In particular devices with lots of I/O and huge gate matrix are disabled. The low-cost Spartan family of FPGAs is fully supported by this edition, as well as the family of CPLDs, meaning small developers and educational institutions have no overheads from the cost of development software. License registration is required to use the Web Edition of Xilinx ISE, which is free and can be renewed an unlimited number of times. The 12.2 version released in 2010-07-23 has a size of 3.02 GB.

8.3 VHDL:
VHDL (VHSIC hardware description language ) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-

programmable gate arrays and integrated circuits.

41

8.4 Design Flow in VHDL :

Figure 8.1 Design Flow in VHDL VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench. VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada ( tasks). Like Ada, VHDL is strongly typed and is not case sensitive. In order to directly represent operations which are common in hardware, there are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor. VHDL also allows arrays to be indexed in either ascending or descending direction; both conventions are used in hardware, whereas in Ada and most programming languages only ascending indexing is available. VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or

42 verification data. There are some VHDL compilers which build executable binaries. In this case, it might be possible to use VHDL to write a testbench to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected. However, most designers leave this job to the simulator. It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production of transparent latches rather than D-type flip-flops as storage elements. One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, Synopsys Synplify or Mentor Graphics HDL Designer) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required. A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, and then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip.

8.5 Creating a New project:

Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board. To create a new project: 1. Select File > New Project... The New Project Wizard appears. 2. Type tutorial in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. 6. Fill in the properties in the table as shown below: Product Category: All

43 Family: Spartan3 Device: XC3S200 Package: FT256 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: Verilog (or VHDL) Verify that Enable Enhanced Design Summary is selected.

8.6 Program:
--Project describes that SMS based device control

--System Clock is 20 Mhz library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gsm_msg is Port (clk : in std_logic; txd : out std_logic; rxd :in std_logic; rxd1:in std_logic; sda:inout std_logic; sclk : out std_logic; rs : out std_logic; diow : out std_logic; - ---LCD cs : out std_logic; d : inout std_logic_vector(7 downto 0); led :out std_logic_vector(7 downto 0)); end gsm_msg; architecture Behavioral of gsm_msg is type main1 is array(1 to 5) of std_logic_vector(7 downto 0); signal state1:main1:=(x"38",x"06",x"01",x"0c",x"80"); commands

--

LCD

44

type main3 is array(1 to 13) of std_logic_vector(7 downto 0); signal state3:main3:=(x"61",x"5f",x"78",x"3a",x"20",x"20",x"20",x"61",x"5f",x"79",x"3a",x"20",x"20"); --a_x: a_y: (for lcd) type data1 is array(1 to 16) of std_logic_vector(7 downto 0); signal data_disp1:data1:=(x"56",x"65",x"68",x"69",x"63",x"6c",x"65",x"20",x"54",x"72",x"61",x"63",x"6b ",x"69",x"6e",x"67"); ---- vehicle tracking type data2 is array(1 to 11) of std_logic_vector(7 downto 0); signal data_disp2:data2:=( x"20",x"20",x"20",x"53", x"79",x"73",x"74",x"65",x"6d",x"20",x"20"); ---- system type rec_data is array (1 to 3) of std_logic_vector(7 downto 0); signal rx_buff : rec_data; -- store Rx data type main_lcd is (s1,s2,s3,s4,s5); signal state_lcd:main_lcd; type main_adc is (s1,s2,s3,s4); signal state_adc:main_adc; signal sign,sign4 : std_logic_vector(25 downto 0) := "00000000000000000000000000"; signal sign1 : std_logic_vector(25 downto 0) := "00000000000000000000000000"; signal lcd1, lcd2,lcd3,lcd4,lcd5,lcd6,lcd7,lcd8 : std_logic_vector(7 downto 0):=x"20"; type pcf is(set1,write1,read1,division_255); signal adc:pcf; signal sig:std_logic_vector(4 downto 0); signal i:integer:=7; signal k1,k2,k3,k4,k5,j1,j,del,del1,p,p1,g,m:integer:=1; type main_div is (s1, s2); signal div_state : main_div; signal adc_out_int, div1,mul, i1,adc_fb,adc_fb1,adc_fb2,adc_fb3: integer := 0; constant a_byte_w:std_logic_vector(7 downto 0):="10010000"; --(1 0 0 1 A2 A1 A0 W) ADDRESS BYTE(for write W=0) constant a_byte_r:std_logic_vector(7 downto 0):="10010001"; --(1 0 0 1 A2 A1 A0 R) ADDRESS BYTE (for read R=1) constant c0_byte:std_logic_vector(7 downto 0) :="01000100"; --CONTROL BYTE0

45 constant c1_byte:std_logic_vector(7 downto 0) :="01000101"; constant c2_byte:std_logic_vector(7 downto 0) :="01000110"; constant c3_byte:std_logic_vector(7 downto 0) :="01000111"; signal clkdiv:std_logic; signal div:std_logic_vector(15 downto 0); signal sig_f,sig_f1,sig_f2,sig_f3 : std_logic_vector(1 downto 0); signal sig_f5:std_logic_vector(5 downto 0):=(others =>'0'); signal flag_s :std_logic_vector(5 downto 0):="000000"; ------------------------------gsm module---------------------------------------------type gsm_command_in is array (1 to 4) of std_logic_vector(7 downto 0); constant gsm_cmd_in : gsm_command_in := ( x"41",x"54",x"0d",x"0a"); --AT(Enter) type gsm_command is array (1 to 11) of std_logic_vector(7 downto 0); constant gsm_cmd : gsm_command := x"41",x"54",x"2B",x"43",x"4D",x"47",x"46",x"3d",x"31",x"0d",x"0a"); --AT+CMGF=1(Enter) type gsm_command_id is array (1 to 11) of std_logic_vector(7 downto 0); constant gsm_cmd_id : gsm_command_id := ( x"41",x"54",x"2B",x"43",x"4D",x"47",x"52",x"3d",x"31",x"0d",x"0a"); --AT+CMGR=1(Enter) type gsm_delete is array (1 to 13) of std_logic_vector(7 downto 0); constant gsm_del : gsm_delete := ( x"41",x"54",x"2B",x"43",x"4D",x"47",x"44",x"3d",x"31",x"2c",x"34",x"0d",x"0a"); --AT+CMGD=1,4(Enter) type gsm_msg_no is array (1 to 22) of std_logic_vector(7 downto 0); constant gsm_msg : gsm_msg_no := ( x"41", x"54", x"2B",x"43",x"4d",x"47",x"53",x"3d", x"22",x"39", x"35",x"36", x"36", x"35", x"35", x"39",x"36", x"30", x"30",x"22",x"0D", x"0A"); --AT+CMGS="9566559600"Enter [To send Msg] type gsm_reply is array (1 to 29) of std_logic_vector(7 downto 0); constant gsm_ack : gsm_reply :=(x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"0d",x"0a",x"44",x"65",x"76",x"69",x"63",x" 65",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"1a",x"0d",x"0a"); -- Device is controlled type disp is array (53 to 79) of std_logic_vector(7 downto 0); signal disp_data_rx : disp; --Receive msg(device) --CONTROL BYTE1 --CONTROL BYTE2 --CONTROL BYTE3

46 type ready is array (1 to 7) of std_logic_vector(7 downto 0); signal ready_data_rx : ready; --Receive +CMT (for check) type main_g is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13); signal state_g:main_g; signal flag_enable,ack,flag1 : std_logic; signal delay : std_logic_vector(11 downto 0) := (others => '0'); signal baud_clk: std_logic ; signal buff_tx : std_logic_vector(7 downto 0) := (others => '0'); signal bitcnt_tx : std_logic_vector(3 downto 0) := (others => '0'); signal bitcnt_txx : std_logic_vector(3 downto 0) := (others => '0'); constant cntone : std_logic_vector(3 downto 0) := "0001"; signal shift,shift1 : std_logic_vector(7 downto 0); signal bitcnt_rx : std_logic_vector(3 downto 0) := (others => '0'); signal bitcnt_rx1 : std_logic_vector(4 downto 0) := (others => '0'); ---------------------------------gps module---------------------------------------------------------------------type main3_g is array(1 to 107) of std_logic_vector(7 downto 0); signal state3_g : main3_g := ( x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"0d",x"0a", x"54",x"49",x"4d",x"45",x"20",x"3a",x"20",x"20",x"3a",x"20",x"20",x"3a",x"20",x"20",x"20",x"20" ,x"0d",x"0a",x"44",x"41",x"54",x"45",x"20",x"3a",x"20",x"20",x"3a",x"20",x"20",x"3a",x"20",x"20 ",x"20",x"20",x"0d",x"0a",x"4c",x"41",x"54",x"54",x"49",x"20",x"3a",x"20",x"20",x"20",x"20", x"20",x"20",x"20",x"20",x"20" ,x"20",x"20",x"0d",x"0a",x"4c",x"51",x"47",x"49",x"54",x"20",x"3a",x"20",x"20",x"20",x"20",x"20 ",x"20",x"20",x"20",x"20",x"20",x"20",x"0d",x"0a",x"56",x"65",x"68",x"69",x"63",x"6c",x"65",x"2 0",x"41",x"63",x"63",x"69",x"64",x"65",x"6e",x"74",x"65",x"64",x"1a",x"0d",x"0a"); ---TIME : - -

type main3_g1 is array(1 to 107) of std_logic_vector(7 downto 0); signal state3_g1 : main3_g1:= (x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"0d",x"0a", x"54",x"49",x"4d",x"45",x"20",x"3a",x"20",x"20",x"3a",x"20",x"20",x"3a",x"20",x"20",x"20",x"20" ,x"0d",x"0a",x"44",x"41",x"54",x"45",x"20",x"3a",x"20",x"20",x"3a",x"20",x"20",x"3a",x"20", x"20",x"20",x"20",x"0d",x"0a",x"4c",x"41",x"54",x"54",x"49",x"20",x"3a",x"20",x"20",x"20",x"20" ,x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"0d",x"0a",x"4c",x"51",x"47",x"49",x"54",x"20", x"3a",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"0d",x"0a",x"20",x"20" ,x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", x"20",x"1a",x"0d",x"0a"); signal t,lt,lg,d1, data_t,time_delay,lcd_delay :integer := 1; signal t1 : integer := 5; signal lt1 : integer := 18; signal lg1 : integer := 30; signal d11 : integer := 55;

47 signal l1,l2,l3,l4,l5,l6,t_1,t_2,t_3,t_4,t_5,t_6:std_logic_vector(7 downto 0):= x"20"; type ready1 is array (1 to 73) of std_logic_vector(7 downto 0); signal gps_rx,data_rx : ready1; type main_tx is array (1 to 74) of std_logic_vector(7 downto 0); signal buff1_tx : main_tx; type main_time is array (1 to 12) of std_logic_vector(7 downto 0); signal data_time : main_time; type main_lt is array (1 to 14) of std_logic_vector(7 downto 0); signal data_lt: main_lt; type main_lg is array (1 to 15) of std_logic_vector(7 downto 0); signal data_lg:main_lg; type main_d is array (1 to 12) of std_logic_vector(7 downto 0); signal data_d : main_d; begin --------------------------------clock divider-----------------------------------------process(clk) begin if clk'event and clk='1' then div <= div + 1; case div(15 downto 14) is when "00" => clkdiv <= '1'; when "10" => clkdiv <= '0'; when others => end case; end if; end process; --------------------------------- Temp value read process ------------------------------------------------------process(clkdiv) variable j,l,m,n:std_logic_vector(7 downto 0):="00000000"; begin if clkdiv'event and clkdiv='1' then case state_adc is

48 when s1 => case adc is when set1 => sig<=sig+1; case sig(3 downto 0) is --START CONDITION FOR WRITE CONVERSION when "0000"=> sclk <='1'; when "0010" => sda <= '1'; when "0011"=> sda <='0'; when "0100"=> sclk<='0'; i <= 7; --ADDRESS BYTE FOR WRITE OPERATION when "0101" => sda <=a_byte_w(i); sclk<='1'; when "0110" => sclk<='0'; if i > 0 then i <= i - 1; sig(3 downto 0)<="0101"; else sig(3 downto 0)<="0111"; i <= 7; end if; when "0111"=> --ACKNOWLEDGEMENT sclk<='1'; when "1000" => sclk <='0'; --CONTROL BYTE OPERATION when "1001"=> sda <=c0_byte(i); sclk <='1'; when "1010"=> if i > 0 then i <= i - 1;

49 sig(3 downto 0)<="1001"; else sig(3 downto 0)<="1011"; i <= 7; end if; sclk <='0'; when "1011"=> --ACKNOWLEDGEMENT sclk<='1'; when "1100" => sclk <='0'; when "1101" => adc<=write1; sig <= (others => '0'); when others => end case; ----------------------------------------------------START CONDITION FOR A/D CONVERSION when write1 => sig<=sig+1; case sig(3 downto 0) is when "0000"=> sclk <='1'; when "0010" => sda <= '1'; when "0011"=> sda <='0'; when "0100"=> sclk<='0'; i <= 7; --ADDRESS BYTE FOR READ OPERATION when "0101" => sda <=a_byte_r(i); sclk<='1'; when "0110"=> if i > 0 then i <= i - 1; sig(3 downto 0)<="0101"; else sig(3 downto 0)<="0111"; i <= 7; end if;

50 sclk<='0';

when "0111"=> --ACKNOWLEDGEMENT sda <='Z'; sclk<='1'; when "1000" => sclk <='0'; when "1001" => adc<=read1; sig <= (others => '0'); when others => end case; --A/D READ OPERATION when read1 => sig<=sig+1; --FOR EXAMPLE case sig(3 downto 0) is --sda=11110101 when "0000" => sclk<='1'; l:=l(6 downto 0) & sda; when "0001" => if i > 0 then i <= i - 1; sig(3 downto 0)<="0000"; else sig(3 downto 0)<="0010"; i <= 7; end if; sclk <='0'; when "0010" => sda <='0'; when "0011" => sclk <='1'; when "0100" => sda <='1'; when "0101" => sclk <='0'; sda <='Z'; when "0110" =>

51 adc_out_int <= conv_integer(l); -Integer Value of

Corresponding Digital data when "0111" => data(0 to FF) into (0 to 99) by ((data*99)/255) mul <= adc_out_int * 99; i1 <= 0; adc <= division_255; div_state <= s1; when others => end case;

-- converting the Digital

when division_255 => -- DIVISION UNIT (divisin by 255) case div_state is when s1 => if (mul >= 255) then mul <= mul - 255; i1 <= i1 + 1; div_state<=s1; else if (mul < 127) then div1 <= i1; div_state <= s2; else div1 <= i1 + 1; div_state <= s2; end if; end if; when s2 => adc_fb <= div1; --0 to 99 conversion data(adc data) state_adc <= s2; adc <= set1; sig <= (others => '0'); when others => end case; when others => end case;

------------------------adc ch1-------------------------when s2 =>

52

case adc is when set1 =>

sig<=sig+1; case sig(3 downto 0) is --START CONDITION FOR WRITE CONVERSION when "0000"=> sclk <='1'; when "0010" => sda <= '1'; when "0011"=> sda <='0'; when "0100"=> sclk<='0'; i <= 7; --ADDRESS BYTE FOR WRITE OPERATION when "0101" => sda <=a_byte_w(i); sclk<='1'; when "0110" => sclk<='0'; if i > 0 then i <= i - 1; sig(3 downto 0)<="0101"; else sig(3 downto 0)<="0111"; i <= 7; end if; when "0111"=> --ACKNOWLEDGEMENT sclk<='1'; when "1000" => sclk <='0'; --COTNTROL BYTE OPERATION when "1001"=> sda <=c1_byte(i); sclk <='1'; when "1010"=> if i > 0 then i <= i - 1;

53 sig(3 downto 0)<="1001"; else sig(3 downto 0)<="1011"; i <= 7; end if; sclk <='0'; when "1011"=> --ACKNOWLEDGEMENT sclk<='1'; when "1100" => sclk <='0'; when "1101" => adc<=write1; sig <= (others => '0'); when others => end case; ----------------------------------------------------START CONDITION FOR A/D CONVERSION when write1 => sig<=sig+1; case sig(3 downto 0) is when "0000"=> sclk <='1'; when "0010" => sda <= '1'; when "0011"=> sda <='0'; when "0100"=> sclk<='0'; i <= 7; --ADDRESS BYTE FOR READ OPERATION when "0101" => sda <=a_byte_r(i); sclk<='1'; when "0110"=> if i > 0 then i <= i - 1; sig(3 downto 0)<="0101"; else sig(3 downto 0)<="0111"; i <= 7; end if;

54 sclk<='0';

when "0111"=> --ACKNOWLEDGEMENT sda <='Z'; sclk<='1'; when "1000" => sclk <='0'; when "1001" => adc<=read1; sig <= (others => '0'); when others => end case; --A/D READ OPERATION when read1 => sig<=sig+1; --FOR EXAMPLE case sig(3 downto 0) is --sda=11110101 when "0000" => sclk<='1'; j:=j(6 downto 0) & sda; when "0001" => if i > 0 then i <= i - 1; sig(3 downto 0)<="0000"; else sig(3 downto 0)<="0010"; i <= 7; end if; sclk <='0'; when "0010" => sda <='0'; when "0011" => sclk <='1'; when "0100" => sda <='1'; when "0101" => sclk <='0'; sda <='Z'; when "0110" =>

55 adc_out_int <= conv_integer(j); -Integer Value of

Corresponding Digital data when "0111" => data(0 to FF) into (0 to 99) by ((data*99)/255) mul <= adc_out_int * 99; i1 <= 0; adc <= division_255; div_state <= s1; when others => end case;

-- converting the Digital

when division_255 => -- DIVISION UNIT (division by 255) case div_state is when s1 => if (mul >= 255) then mul <= mul - 255; i1 <= i1 + 1; div_state<=s1; else if (mul < 127) then div1 <= i1; div_state <= s2; else div1 <= i1 + 1; div_state <= s2; end if; end if; when s2 => adc_fb1 data(adc data) state_adc<= s1; adc <= set1; sig <= (others => '0'); when others => end case; when others => end case; end if; end process;

<= div1;

--0 to 99 conversion

process(clk)

56 variable t2 : integer := 0; variable h3, h4 : integer:=0; begin if (clk'event and clk = '1') then sig_f <= sig_f + 1; case sig_f is when "00" => t2 := adc_fb; h3 := 0; h4 := 0; when "01" => if (t2 >= 10) then h3 := h3 + 1; t2 := t2 - 10; sig_f <= "01"; else h4 := t2; sig_f <= "10"; end if;

--Display Control for ADC FeedBack

when "10" => if h3>=0 and h3<=9 and h4>=0 and h4<=9 then lcd1 <= conv_std_logic_vector (h3, 8) + x"30"; --(For display the value in LCD (value + 30)) lcd2 <= conv_std_logic_vector (h4, 8) + x"30"; end if; when others => sig_f <= "00"; end case; end if; end process;

process(clk) variable t21 : integer := 0; variable h31, h41 : integer:=0; begin if (clk'event and clk = '1') then sig_f1 <= sig_f1 + 1; case sig_f1 is when "00" => t21 := adc_fb1; h31 := 0;

--Display Control for ADC FeedBack

57 h41 := 0; when "01" => if (t21 >= 10) then h31 := h31 + 1; t21 := t21 - 10; sig_f1 <= "01"; else h41 := t21; sig_f1 <= "10"; end if; when "10" => if h31>=0 and h31<=9 and h41>=0 and h41<=9 then lcd3 <= conv_std_logic_vector (h31, 8) + x"30"; --(For display the value in LCD (value + 30)) lcd4 <= conv_std_logic_vector (h41, 8) + x"30"; end if; when others => sig_f1 <= "00"; end case; end if; end process; ---------------------------------------- LCD Display -------------------------------------------------process begin if clk'event and clk='1' then case state_lcd is when s1 => sign <= sign + 1; case sign(25 downto 20) is when "000000" => when "000001" => when "000010" => when "000011" => k1<=k1+1; if k1<=5 then sign(25 downto 20)<="000001"; d <= state1(k1); cs <= '1'; cs <= '0'; --(lcd command) rs <= '0'; diow <= '0';

58 else sign(25 downto 20)<="001000"; k2 <= 1; end if;

when "001000" => when "001001" =>

rs <= '0'; diow <= '0'; d <= x"80"; ---lcd secondline display

when "001010" => when "001011" => when "001100" => when "001101" => when "001110" => when "001111" => k2<=k2+1; if k2<16 then else

cs <= '1'; cs <= '0'; rs <= '1'; d <= data_disp1(k2); cs <= '1'; cs <= '0';

------(temperature)

--------lcd display of title

sign(25 downto 20)<="001101"; sign(25 downto 20)<="010000"; k3 <= 1; end if;

when "010000" => rs <= '0'; diow <= '0'; when "010001" => d when "010010" => when "010011" => when "010100" => when "010101" => cs <= '1'; cs <= '0'; rs <= '1'; <= x"c0"; ---lcd secondline display

----lcd display of title

<= data_disp2(k3);

when "010110" => cs <= '1'; when "010111" => cs <= '0'; k3<=k3+1; if k3<11 then sign(25 downto 20)<="010101"; else sign(25 downto 20)<="011000";

59 k1<=1; state_lcd<= s2; end if; when others => end case; ---------------------------------------------------------------------------------when s2 => sign <= sign + 1; case sign(25 downto 20) is when "000000" => when "000001" => when "000010" => when "000011" => k1<=k1+1; if k1<=5 then sign(25 downto 20)<="000001"; else sign(25 downto 20)<="001000"; k2 <= 1; end if; d <= state1(k1); cs <= '1'; cs <= '0'; --(lcd command) rs <= '0'; diow <= '0';

when "001000" => when "001001" =>

rs <= '0'; diow <= '0'; d <= x"80";

when "001010" => when "001011" => when "001100" => when "001101" =>

cs <= '1'; cs <= '0'; rs <= '1'; d <= state3(k2);

when "001110" => cs <= '1'; when "001111" => cs <= '0'; k2<=k2+1; if k2<13 then sign(25 downto 20)<="001101"; else sign(25 downto 20)<="010000"; k1<=1;

60 state_lcd<= s3; end if; when others => end case; ----------------------------------------------------------when s3 => sign1<=sign1+1; case sign1(25 downto 20) is when "000000" => rs <= '0'; diow <= '0'; when "000001" => d <= x"84"; when "000010" => cs <= '1'; when "000011" => cs <= '0'; when "000100" => rs <= '1'; when "000101" => d <= lcd1; when "000110" => cs <= '1'; when "000 111" => cs <= '0'; when "001000" => d <= lcd2; when "001001" => cs <= '1'; when "001010" => cs <= '0'; when "001011"=> state_lcd <= s4; when others => sign1(25 downto 20)<="000000"; end case;

--Temperature Value

when s4 => sign1<=sign1+1; case sign1(25 downto 20) is when "000000" => rs <= '0'; diow <= '0'; when "000001" => d <= x"8b"; when "000010" => cs <= '1'; when "000011" => cs <= '0'; when "000100" => rs <= '1'; when "000101" => d <= lcd3; when "000110" => cs <= '1'; when "000111" => cs <= '0'; when "001000" => d <= lcd4; when "001001" => cs <= '1'; when "001010" => cs <= '0'; when "001011"=> sign1(25 downto 20)<="000000"; state_lcd <= s3; when others =>

--Temperature Value

61 end case; when others => end case; end if; end process;

---------------------------flag_enable-----------------------------------process(clk) begin if (clk = '1' and clk'event) then flag_s <= flag_s + 1; case flag_s(2 downto 0) is

when "000" => if ( adc_fb>=32 and adc_fb<=34 and adc_fb1>=39 and adc_fb1<=40) then and adc_fb2>=33 and adc_fb2<=34 ) then flag_enable <= '0'; else flag_enable <= '1'; flag_s(2 downto 0) <= "000"; end if; when others => end case; end if; end process; ----------------------------------------------------------------------------------process(clk) begin if rising_edge(clk) then delay <= delay + 1; case delay is when "000000000000" => -- 0 baud_clk <= '1'; when "010000010010" => -- 1042 baud_clk <= '0'; when "100000100100" => -- 2083 baud_clk <= '1'; delay <= (others => '0');

--

62 when others => end case; end if; end process;

process(baud_clk) begin if rising_edge(baud_clk) then ---------------------------------Receive GPS Data----------------------------------------case bitcnt_rx1 is when "00000" => if (RxD1 = '1') then -- Start Bit bitcnt_rx1 <= "00000"; else bitcnt_rx1 <= bitcnt_rx1 + cntone; end if; when "00001" | "00010" | "00011" | "00100" | "00101" | "00110" | "00111" | "01000" => bitcnt_rx1 <= bitcnt_rx1 + cntone; shift1 <= RxD1 & shift1(7 downto 1); when "01001" => data_rx(p) <= shift1; if (p <73) then p <= p + 1; bitcnt_rx1<= "00000"; else p <= 1; bitcnt_rx1 <= "01010"; end if; when "01010"=> if (p<73) then bitcnt_rx1 <= "01100"; else p bitcnt_rx1 <= "00000"; end if; when "01100"=> <= 1;

63 if (data_rx(p)= x"24") then p<=p+1; bitcnt_rx1 <= "01101"; ---$

else if (p<73)then p<=p+1; bitcnt_rx1 <="01100"; else p<= 1; bitcnt_rx1 <= "00000"; end if; end if; when "01101"=> if (data_rx(p)=x"47") then ---G p<=p+1; led2<='1'; bitcnt_rx1 <= "01110"; else p<= 1; bitcnt_rx1 <= "00000"; end if; when "01110" => if (data_rx(p)=x"50") then

---P p<=p+1; bitcnt_rx1<= "01111"; else p<= 1; bitcnt_rx1 <= "00000";

end if; when "01111"=> if (data_rx(p)=x"52") then ---R gps_rx(m)<=data_rx(p); p<=p+1; m<=m+1; led4<='1';

--

64 bitcnt_rx1 <= "10000"; else p<= 1; bitcnt_rx1 <= "00000"; end if; when "10000"=> if (data_rx(p)=x"4D") then

----M gps_rx(m)<=data_rx(p); p<=p+1; m<=m+1; bitcnt_rx1 <= "10001"; else p<= 1; bitcnt_rx1 <= "00000";

end if; when "10001"=> if (data_rx(p)=x"43") then

---c gps_rx(m)<=data_rx(p); p<=p+1;

m<=m+1; bitcnt_rx1 <= "10010"; else p<= 1; bitcnt_rx1 <= "00000"; end if; when "10010"=> gps_rx(m)<=data_rx(p); if (p<73)then -------full data tx p<=p+1; m<=m+1; bitcnt_rx1 <= "10010"; else m<=1; p<= 1; t<=1; bitcnt_rx1<="10011"; end if ; when "10011" => data_time(t)<=gps_rx(t1);

65 -----time if (t1<=10)then t1<=t1+1; t<=t+1; bitcnt_rx1 <= "10011"; else t1<=5; p<= 1; t<=1; bitcnt_rx1<="10100"; end if ; when "10100" => data_lt(lt)<=gps_rx(lt1); ------latitude if (lt1<=27)then lt1<=lt1+1; lt<=lt+1; bitcnt_rx1 <= "10100"; else lt1<=18; p<= 1; lt<=1; bitcnt_rx1<="10101"; end if ; when "10101" => data_lg(lg)<=gps_rx(lg1); if (lg1<=40)then ----longitude lg1<=lg1+1; lg<=lg+1; bitcnt_rx1 <= "10101"; else lg1<=30; p<= 1; lg<=1; bitcnt_rx1<="10110"; end if ; when "10110" => data_d(d1)<=gps_rx(d11); -----date

66 if (d11<=60)then d11<=d11+1; d1<=d1+1; bitcnt_rx1 <= "10110"; else d11<=55 ; p<= 1; d1<=1; bitcnt_rx1<="10111"; end if ;

when "10111"=> if (del1 <=3000) then del1 <= del1 + 1 ; bitcnt_rx1<="10111"; else m<=1; p<= 1; t1<=5;lt1<=17;lg1<=30;d11<=55; t<=1;lt<=1;lg<=1;d1<=1; bitcnt_rx1<="00000"; shift1 <= (others => '0'); end if; when others => end case; end if; end process;

----------------------------------------------process(baud_clk) begin if rising_edge(baud_clk) then case state_g is when s0 => case bitcnt_tx is when "0000" => led <= x"00"; g <= 1; j <= 1;

67 del <= 1; bitcnt_tx <= bitcnt_tx + cntone; when "0001" => buff_tx <= gsm_cmd_in(g); txd <= '0'; bitcnt_tx <= bitcnt_tx + cntone; when "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone; txd <= buff_tx(0); buff_tx <= '1' & buff_tx(7 downto 1); when "1010" => txd <= '1'; if (g < 4) then g <= g + 1; bitcnt_tx <= "0001"; else bitcnt_tx <= "1011"; g <= 1; end if; when "1011" => if (j < 1) then if (del <= 10000) then bitcnt_tx <= "1011"; del <= del + 1; else del <= 1; j <= j + 1; bitcnt_tx <= "0001"; end if; else j <= 1; bitcnt_tx <= "1100"; end if; when "1100" => bitcnt_tx <= "1100"; state_g <= s1; when others => end case; when s1 => if (del <= 30000) then

---AT setting

68 del else bitcnt_tx <= "0000"; buff_tx <= (others => '0'); g j del <= 1; state_g <= s2; end if; when s2 => case bitcnt_tx is when "0000" => led <= x"01"; g <= 1; j <= 1; del <= 1; bitcnt_tx <= bitcnt_tx + cntone; when "0001" => buff_tx <= gsm_cmd(g); --text mode set txd <= '0'; bitcnt_tx <= bitcnt_tx + cntone; when "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone; txd <= buff_tx(0); buff_tx <= '1' & buff_tx(7 downto 1); when "1010" => txd <= '1'; if (g < 11) then g <= g + 1; bitcnt_tx <= "0001"; else bitcnt_tx <= "1011"; g <= 1; end if; when "1011" => if (j < 1) then if (del <= 0000) then bitcnt_tx <= "1011"; del <= del + 1; else del <= 1; <= 1; <= 1; <= del + 1;

69 j <= j + 1; bitcnt_tx <= "0001"; end if; else j <= 1; bitcnt_tx <= "1100"; end if; when "1100" => bitcnt_tx <= "1100"; state_g <= s3; when others => end case; when s3 =>

if (del <= 30000) then del <= del + 1; else bitcnt_rx <= "0000"; bitcnt_tx <= "0000"; disp_data_rx <= (others => (others => '0')); ready_data_rx <= (others => (others => '0')); buff_tx <= (others => '0'); shift <= (others => '0'); p1 <= 1; g <= 1; j <= 1; del <= 1; state_g <= s4; end if; when s4 => case bitcnt_tx is when "0000" => led <= x"0d" ; g <= 1; j <= 1; del <= 1; bitcnt_tx <= bitcnt_tx + cntone; when "0001" => buff_tx <= gsm_del(g); ----AT+CMGD=1,4.... all msg deleting

70 txd <= '0'; bitcnt_tx <= bitcnt_tx + cntone; when "0010" | "0011" | "0100" |"0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone; txd <= buff_tx(0); buff_tx <= '1' & buff_tx(7 downto 1); when "1010" => txd <= '1'; if (g < 13) then g <= g + 1; bitcnt_tx <= "0001"; else g <= 1; bitcnt_tx <= "1011"; end if; when "1011" => if (j < 1) then if (del <= 10000) then bitcnt_tx <= "1011"; del <= del + 1; else del <= 1; j <= j + 1; bitcnt_tx <= "0001"; end if; else j <= 1; bitcnt_tx <= "1100"; end if; when "1100" => bitcnt_tx <= "1100"; state_g <= s5; when others => end case;

when s5 =>

if (del <= 30000) then del <= del + 1; else bitcnt_rx <= "0000"; bitcnt_tx <= "0000";

71 disp_data_rx <= (others => (others => '0')); ready_data_rx <= (others => (others => '0')); buff_tx <= (others => '0'); shift <= (others => '0'); p1 <= 1; g <= 1; j <= 1; del <= 1; state_g <= s6; end if;

------------send msg at this time------------+CMTI : "SM",1 receiving when s6 => case bitcnt_rx is when "0000" => led <= x"02" ; if (RxD = '1') then -- Stop Bit flag1<='1'; state_g<=s9; bitcnt_tx<="0000"; else flag1<='0'; bitcnt_rx <= bitcnt_rx + cntone; end if; when "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" => bitcnt_rx <= bitcnt_rx + cntone; shift <= RxD & shift(7 downto 1); when "1001" => if (RxD = '1') then bitcnt_rx <= "1001"; else if (p1 < 7) then bitcnt_rx <= "0001"; p1 <= p1 + 1; else bitcnt_rx <= "1010"; p1 <= 1 ;

72 end if; end if; if (p1 < 7) then ready_data_rx(p1) <= shift; end if; when "1010" => if ((ready_data_rx(3) = x"2b") and (ready_data_rx(4) = x"43") and (ready_data_rx(5) = x"4d") and (ready_data_rx(6) = x"54")) then led <= x"03" ; if (del <= 70000) then del <= del + 1; bitcnt_rx <= "1010"; else state_g <= s7; bitcnt_tx <= "0000"; bitcnt_rx <= "0000"; shift<= (others => '0'); ready_data_rx <= (others => (others => '0')); p1 <= 1; end if; else led <= x"0f" ; state_g <= s7; p1 <= 1; bitcnt_tx <= "0000"; ready_data_rx <= (others => (others => '0')); end if; when others => end case; when s7 => ----- AT+CMGR=1 sending case bitcnt_tx is when "0000" => led <= x"04" ; g <= 1; j <= 1; del <= 1; bitcnt_tx <= bitcnt_tx + cntone; when "0001" => buff_tx <= gsm_cmd_id(g); txd <= '0';

73 bitcnt_tx <= bitcnt_tx + cntone; when "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone; txd <= buff_tx(0); buff_tx <= '1' & buff_tx(7 downto 1); when "1010" => txd <= '1'; if (g < 11) then g <= g + 1; bitcnt_tx <= "0001"; else g <= 1; bitcnt_tx <= "1011"; end if; when "1011" => if (j < 1) then if (del <= 10000) then bitcnt_tx <= "1011"; del <= del + 1; else del <= 1; j <= j + 1; bitcnt_tx <= "0001"; end if; else j<= 1; bitcnt_tx <= "1100"; end if; when "1100" => bitcnt_tx <= "1100"; led<=x"08"; bitcnt_rx<="0000"; when others => end case; ----- AT+CMGR=1 RECEIVING case bitcnt_rx is when "0000" => led<=x"07"; if (RxD = '1') then bitcnt_rx <= "0000"; else bitcnt_rx <= bitcnt_rx + cntone; end if;

--

-- Stop Bit

74 when "0001" | "0010" | "0011" |"0100" | "0101" | "0110" | "0111" | "1000" => bitcnt_rx <= bitcnt_rx + cntone; shift <= RxD & shift(7 downto 1); when "1001" => if (p1 >=75) then disp_data_rx(p1) <= shift; end if; if (p1 <78 ) then p1 <= p1 + 1; bitcnt_rx <= "0000"; else p1 <= 1; bitcnt_rx <= "1011"; end if; when "1011" => if ((disp_data_rx(75) = x"4c") and (disp_data_rx(76) = x"6f") and (disp_data_rx(77) = x"63") and (disp_data_rx(78) = x"74")) then led <= x"05" ; -- motor on ack <= '1'; else ack <= '0'; led <= x"CC"; end if; if (j < 1) then if (del <= 50000) then bitcnt_rx <= "1011"; del <= del + 1; else del <= 1; j <= j + 1; bitcnt_rx <= "0001"; end if; else j <= 1; bitcnt_rx <= "1100"; end if; when "1100" => bitcnt_rx <= "1100"; state_g <= s8; when others => end case;

75

when s8 =>

if (del <= 30000) then del <= del + 1; else bitcnt_rx <= "0000"; bitcnt_tx <= "0000"; disp_data_rx <= (others => (others => '0')); ready_data_rx <= (others => (others => '0')); buff_tx <= (others => '0'); shift <= (others => '0'); p1 <= 1; g <= 1; j <= 1; del <= 1; state_g <= s9; end if; when s9 => led <= x"06"; case bitcnt_tx is when "0000" => if( ack= '1') then flag1 <='0'; bitcnt_tx <="0001"; elsif (flag_enable ='1') then flag1 <='0'; bitcnt_tx <="0001"; else if( flag1 ='0') then state_g <= s11; del<=1; else state_g<=s6; bitcnt_rx <= "0000"; end if; end if; when "0001" => buff_tx <= gsm_msg(g);

76 txd <= '0'; bitcnt_tx <= bitcnt_tx + cntone; when "0010" | "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" => bitcnt_tx <= bitcnt_tx + cntone; txd <= buff_tx(0); buff_tx <= '1' & buff_tx(7 downto 1); when "1010" => txd <= '1'; if (g < 22) then g <= g + 1; bitcnt_tx <= "0001"; else bitcnt_tx <= "1011"; g <= 1; end if; when "1011" => if (j < 1) then if (del <= 50000) then bitcnt_tx <= "1011"; del <= del + 1; else del <= 1; j <= j + 1; bitcnt_tx <= "0001"; end if; else j <= 1; bitcnt_tx <= "1100"; end if; when "1100" => bitcnt_tx <= "1100"; state_g <= s10; when others => end case;

when s10=> case bitcnt_txx is when "0000" => g <= 1; j <= 1; del <= 1; bitcnt_txx <= bitcnt_txx + cntone; when "0001"=>

77 if (ack='1') then if (g = 17) then buff_tx <= l1; elsif (g = 18) then buff_tx <= l2; elsif (g = 20 ) then buff_tx <= l3; elsif (g = 21) then buff_tx <= l4; elsif (g = 23) then buff_tx <= l5; elsif (g = 24) then buff_tx <= l6; elsif (g = 35) then buff_tx elsif (g = 36) then buff_tx elsif (g = 38 ) then buff_tx elsif (g = 39) then buff_tx elsif (g = 41) then buff_tx elsif (g = 42) then buff_tx <= data_d(1); <= data_d(2); <= data_d(3); <= data_d(4); <= data_d(5); <= data_d(6);

elsif (g = 54) then buff_tx elsif (g = 55) then buff_tx elsif (g = 56 ) then buff_tx elsif (g = 57) then buff_tx elsif (g = 58) then buff_tx elsif (g = 59) then buff_tx elsif (g = 60) then buff_tx elsif (g = 61) then buff_tx elsif (g = 62) then buff_tx elsif (g = 63) then buff_tx elsif (g = 74) then buff_tx elsif (g = 75) then buff_tx elsif (g = 76) then buff_tx elsif (g = 77) then buff_tx elsif (g = 78) then buff_tx elsif (g = 79) then buff_tx elsif (g = 80) then buff_tx elsif (g = 81) then buff_tx elsif (g = 82) then buff_tx elsif (g = 83) then buff_tx else

<= data_lt(1); <= data_lt(2); <= data_lt(3); <= data_lt(4); <= data_lt(5); <= data_lt(6); <= data_lt(7); <= data_lt(8); <= data_lt(9); <= data_lt(10); <= data_lg(1); <= data_lg(2); <= data_lg(3); <= data_lg(4); <= data_lg(5); <= data_lg(6); <= data_lg(7); <= data_lg(8); <= data_lg(9); <= data_lg(10);

buff_tx <= state3_g1(g); end if; elsif( flag_enable ='1') then if (g = 17) then buff_tx <= l1;

78 elsif (g = 18) then buff_tx <= l2; elsif (g = 20 ) then buff_tx <= l3; elsif (g = 21) then buff_tx <= l4; elsif (g = 23) then buff_tx <= l5; elsif (g = 24) then buff_tx <= l6; elsif (g = 35) then buff_tx elsif (g = 36) then buff_tx elsif (g = 38 ) then buff_tx elsif (g = 39) then buff_tx elsif (g = 41) then buff_tx elsif (g = 42) then buff_tx <= data_d(1); <= data_d(2); <= data_d(3); <= data_d(4); <= data_d(5); <= data_d(6);

elsif (g = 54) then buff_tx elsif (g = 55) then buff_tx elsif (g = 56 ) then buff_tx elsif (g = 57) then buff_tx elsif (g = 58) then buff_tx elsif (g = 59) then buff_tx elsif (g = 60) then buff_tx elsif (g = 61) then buff_tx elsif (g = 62) then buff_tx elsif (g = 63) then buff_tx elsif (g = 74) then elsif (g = 75) then elsif (g = 76) then elsif (g = 77) then elsif (g = 78) then elsif (g = 79) then elsif (g = 80) then elsif (g = 81) then elsif (g = 82) then elsif (g = 83) then else buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx buff_tx

<= data_lt(1); <= data_lt(2); <= data_lt(3); <= data_lt(4); <= data_lt(5); <= data_lt(6); <= data_lt(7); <= data_lt(8); <= data_lt(9); <= data_lt(10); <= data_lg(1); <= data_lg(2); <= data_lg(3); <= data_lg(4); <= data_lg(5); <= data_lg(6); <= data_lg(7); <= data_lg(8); <= data_lg(9); <= data_lg(10);

buff_tx <= state3_g(g); end if; end if; bitcnt_txx <= bitcnt_txx + cntone; when "0010" => TxD <= '0'; bitcnt_txx <= bitcnt_txx + cntone;

79 when "0011" | "0100" | "0101" | "0110" | "0111" | "1000" | "1001" | "1010" => bitcnt_txx <= bitcnt_txx + cntone; TxD <= buff_tx(0); buff_tx <= buff_tx(0) & buff_tx(7 downto 1); when "1011" => TxD <= '1'; bitcnt_txx <= bitcnt_txx + cntone; when "1100" => if g <107 then g <= g + 1; bitcnt_txx <= "0001"; else g<= 1; bitcnt_txx <= "1101"; end if; when "1101" => if (j < 1) then if (del <= 50000) then bitcnt_txx<= "1101"; del <= del + 1; else del <= 1; j <= j + 1; bitcnt_txx <= "0001"; end if; else j <= 1; ack<='0'; bitcnt_txx <= "1110"; end if; when "1110" => bitcnt_txx <= "1110"; state_g <= s11; when others => end case; when s11 => led <= x"f0"; if (del <= 80000) then del <= del + 1;

80 else bitcnt_tx <= "0000"; bitcnt_txx<="0000"; buff_tx <= (others => '0'); g <= 1; j <= 1; del <= 1; state_g <= s0; end if;

when others => end case; end if; end process;

-----------------------------------time convertion process----------------------process(clk) begin if clk'event and clk ='1' then sig_f5<=sig_f5+1; case sig_f5 (5 downto 0) is when"000000" => t_1<= data_time(1)+0; t_2<= data_time(2)+5; t_3<= data_time(3)+3; t_4<= data_time(4)+0; t_5<= data_time(5)+0; t_6<= data_time(6)+0; sig_f5<="000001"; when "000001" => ----------seconds--------if(t_6 >=x"30" and t_6<=x"39" and t_5>=x"30" and t_5<=x"35") then l6<=t_6; l5<= t_5; else l6<=t_6; l5<= t_5 -6; t_4<= t_4+1; end if;

81 sig_f5<="000010"; when "000010" => if(t_4>=x"30" and t_4<=x"39" and t_3>=x"30" and t_3<=x"35") then l4<=t_4; l3<= t_3; else l4<= t_4; l3<= t_3 -6; t_2<= t_2+1; end if; sig_f5<="000011"; when "000011" => -if(t_2>=x"30" and t_2<=x"39" and t_1>=x"30" and t_1<=x"31") then l2<=t_2; l1<= t_1; elsif( t_2>=x"30" and t_2<=x"39" and t_1>=x"32") then if( t_2>=x"30" and t_2<=x"33" and t_1>=x"32") then l2<=t_2; l1<=t_1; else l2<=t_2-4; l1<=t_1-2; end if; else l2<=t_2-10; l1<= t_1+1; end if; sig_f5<="000100"; when "000100" => if(time_delay <= 5000) then time_delay <= time_delay+1; sig_f5 <="000100";

82 else time_delay <= 1; sig_f5<="000000"; end if; when others => end case; end if; end process; end Behavioral;

83

CHAPTER 9

CONCLUSION
This version of our project will send a reply when we send a SMS and also sends the position of the vehicle in terms of latitude and longitude when there is any accident. It doesnt tell the exact nature of the accident, whether it is severe or just a mild one. With the help of accelerometer sensor, we can tell the exact position of the vehicle. We can predict whether the vehicle is in normal position or upside down. This project can be enhanced in future by modifying in the program to find out the actual position of the vehicle and also in accident prevention. This can also be enhanced by automatically locking all the brakes in case of accident. In many accidents, it becomes severe as the drivers lose control and cant stop the vehicle. During the accident, the accelerometer sensor will triggered due to vibrations which is received and processed by the Spartan processor. The processor should be connected to devices which can lock the brakes when triggered. By this enhancement, we can stop the vehicle and can reduce the impact of the accident. This can be used to prevent vehicle theft. In case of any theft, the owner can track the location of the vehicle. In public transport system, the implementation of this equipment will ease the people. When public transport systems like bus, trains these are installed with this equipment, People can know the location of the vehicle and arrive in the stop in time. Modifying the code, we can make it to send the position of the vehicle periodically to a subscribed mobile number so that companies can keep an eye on their vehicles. Thus we can make use of the available technology to the benefit of the people by saving the lives of the people and helping the owners of the vehicle to keep track of their vehicles.

84

REFERENCES

1. Adnan I. Yaqzan, Issam W. Damaj, and Rached N. Zantout (July 24, 2008), GPSBased Vehicle Tracking System-On-Chip, Proceedings of the world Congress on Engineering Vol I WCE 2. Arias Tanti Hapsari Eniman Y Syamsudin Imron Pramana (2005) , Design Of Vehicle Position Tracking System Using Short Message Services And Its Implementation On FPGA, Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ISBN:0-7803-8737-6 3. Peter J. Ashenden (1995) ,The designer's guide to VHDL, Morgan Kaufmann Publishers, San Francisco 4. Theodore S. Rappaport (2008),Wireless Communication, Prentice Hall PTR 1. 2. 5. Vijay Kumar Garg, Joseph E. Wilkes (October 1998),Principles and Applications of GSM, Prentice Hall PTR

6. Ziad A. Osman, Mazen Jrab, Souleiman Midani, Rached N. Zantout (May 2003), Implementation of a System for Offline Tracking using GPS ,Mediterranean Microwave Symposium, Ain Shams University, Cairo,Egypt, pp. 203-207.