(ii)MEMORY CONSISTENCY:

a. sequential consistency b. relaxed consistency

(a)SEQUENTIAL CONSISTENCY:
At any given instant in time in a sequential program, memory has a well defined state. This is called sequential consistency. In parallel programs, it all depends upon the viewpoint. Two writes to memory by a hardware thread may be seen in a different order by another thread. The reason is that when a hardware thread writes to memory, the written data goes through a path of buffers and caches before reaching main memory. Along this path, a later write may reach main memory sooner than an earlier write. Similar effects apply to reads. If one read requires a fetch from main memory and a later read hits in cache, the processor may allow the faster read to pass the slower read. i!ewise, reads and writes might pass each other

. ( )RELA!E" CONSISTENCY: The processor does not have to guarantee that other processors see those reads and writes in the original order. Systems that allow this reordering are said to exhibit relaxed consistency. "ecause relaxed consistency relates to how hardware threads observe each other#s actions, it is not an issue for programs running time sliced on a single hardware thread. Inattention to consistency issues can result in concurrent programs that run correctly on single$threaded hardware, or even hardware running with %T Technology, but fail when run on multi$threaded hardware with dis&oint caches. The hardware is not the only cause of relaxed consistency. 'ompilers are often free to reorder instructions. The reordering is critical to most ma&or compiler optimi(ations. )or instance, compilers typically hoist loop$invariant reads out of a loop, so that the read is done once per loop instead of once per loop iteration. anguage rules typically grant the compiler license to presume the code is single$threaded, even if it is not.