Now you are ready to add vhdl fles to your Project. Click Project->Add Files, a window will be opened for selecting files to be added. Browse to the folder home/atak/vhdl_sim, select the two vhdl files bitreverse.vhd and tt_bitreverse.vhd and click open. (you can use the control key for multiple selection).
After adding VHDL files to your Project, the two files will appear in the workspace window. Click the + sign which is on the left of library=>my_vhdl_sim, the two files will be shown then.
For each file you will notice an entity and architecture. Double click on the files to see the vhdl code in the main window. Spend some time to understand the VHDL codes. The bitreverse.vhd files contain a process which performs a bit reversal operation. tt_bitreverse.vhd is the testbench file to test the bitreverse.vhd.
Click compile-> compile all, this will compile all vhdl files in the design. you should see the message finished compilation session in the console window of sonata.
Click simulate-> select TopLevel, select tt_bitreverse(behavioral) from the window opened.
The sonatas main window has a field for simulation run time in the middle of the toolbar. Write 1000ns and click the arrow left to the field(shown below).
a waveform window will be opened.
Double click on tt_bitreverse in hierarchy window(on the left), you will notice the signals in the tt_bitreverse module in the scope window(left-bottom window) as shown below.
add all the signals in the scope window to the waveform window (by dragging or right clicking and then clicking add selected to waveform)
restart the simulation by clicking simulate->restart and then click .