N.

Senthil Kumar,
M. Saravanan &
S. Jeevananthan
Oxford University Press 2013
INTEL 8086 Microprocessor
rchitecture, !eatures, Si"nals
Oxford University Press 2013
Introduction

#$%8 & Intel release' its (irst #6&)it microprocessor &

8086 & e*ecutes the instructions at +., MI-S .i.e +.,
million Instruction per secon'/.

e*ecution time o( one instruction & 000ns

.1#2MI-S1#2.+.,*#06//

8086 can also a''ress one me"a)3tes .#M41++0

)3tes/ o( memor3.

nother (eature in 8086 & presence o( a small 6&)3te

instruction 5ueue & so instructions (etche' (rom
memor3 are place' in it )e(ore the3 are e*ecute'.

hi"her e*ecution spee' & lar"er memor3 si6e

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Architecture of 8086

It is su)'ivi'e' into t7o units & The e*ecution unit

.E8/ an' The )us inter(ace unit .4I8/

The e*ecution unit .E8/ inclu'es 9 L8 & ei"ht #6&

)it "eneral purpose re"isters & a #6 )it (la" re"ister &
a control unit.

The )us inter(ace unit .4I8/ inclu'es 9 a''er (or

a''ress calculations & (our #6&)it se"ment re"isters
.:S, ;S, SS an' ES/ & a #6 )it instruction pointer
.I-/ & a 6 )3te instruction 5ueue an' )us control
lo"ic.
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Execution Unit (EU)

The E8 consists o( ei"ht #6&)it "eneral purpose

re"isters & <, 4<, :<, ;<, S-, 4-, SI an' ;I.

<, 4<, :< an' ;< & can )e 'ivi'e' into t7o 8&)it
re"isters & =, L, 4L, 4=, :=, :L, ;= an' ;L

>eneral purpose re"isters & can )e use' to store 8

)it or #6 )it 'ata 'urin" pro"ram e*ecution.
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Functional Block diagram of 8086
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Special function of regiter
<2L & use' as accumulator & multipl3, 'ivi'e, input2output .I2?/ an'
some o( the 'ecimal an' S:II a'@ustment instructions.
4< & hol's the o((set a''ress o( a location in memor3 & also use' to
re(er the 'ata in memor3 usin" looAup ta)le techni5ue 7ith the help o(
<LT instruction.
:< & use' to hol' the count 7hile e*ecutin" repeate' strin"
instructions .BE-2BE-E2BE-NE/ an' L??- instruction & also use' to
hol' the count 7hile e*ecutin" the shi(t an' rotate instructions & count
value in'icates the num)er o( times the same instructions has to )e
e*ecute'.
;< & use' to hol' a part o( the result 'urin" multiplication an' part o(
the 'ivi'en' )e(ore a 'ivision & also use' to hol' the I2? 'evice
a''ress 7hile e*ecutin" IN an' ?8T instructions
S- & stacA pointer & use' to hol' the o((set a''ress o( the 'ata store'
at the top o( stacA se"ment & use' alon" 7ith SS re"ister to 'eci'e
the a''ress at 7hich 'ata is pushe' or poppe' 'urin" the e*ecution
o( -8S= an' -?- instructions.
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Special function of regiter
4- & 4ase -ointer & use' to hol' the o((set a''ress o( the 'ata
to )e rea' (rom or 7rite into the stacA se"ment
SI & Source In'e* re"ister & use' to hol' the o((set a''ress o(
source 'ata in 'ata se"ment 7hile e*ecutin" strin" instructions
;I & ;estination In'e* re"ister & use' to hol' the o((set a''ress
o( 'estination 'ata in e*tra se"ment 7hile e*ecutin" Strin"
instructions.
N?TE 9 se"ment & a portion o( memor3 7here 'ata (or a
pro"ram is store' & the ma*imum si6e o( a se"ment can )e
60 )3tes & minimum si6e o( a se"ment can )e even one )3te &
se"ment )e"ins in memor3 at a memor3 a''ress 7hich is
'ivisi)le )3 #6.
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Flag regiter of 8086

The (la"s & classi(ie' into status (la"s an' control

(la"s

:!, -!, !, C!, S! an' ?! & status (la"s & the3

in'icate the status o( the result that is o)taine' a(ter
the e*ecution o( arithmetic or lo"ic instruction

;!, I! an' T! & control (la"s & the3 can control the
operation o( :-8
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Function of different flag
:! .:arr3 !la"/ & hol's the carr3 a(ter 8 )it or #6 )it a''ition & hol's
)orro7 a(ter 8 )it or #6 )it su)traction per(orme'
-! .-arit3 !la"/ & I( the lo7er 8 )it o( the result is havin" o'' parit3
.i.e. o'' num)er o( #s/ & -! is set to 0 & -! is set to # i( the lo7er 8 )it
o( result is havin" even parit3.
! .u*iliar3 :arr3 !la"/ & hol's the carr3 a(ter a''ition & the )orro7
a(ter su)traction o( the )its in )it position D & .LS4 is treate' as )it
position 0/ & use' )3 ; an' ;S instructions to a'@ust the value in
L a(ter a 4:; a''ition or su)traction.
C! .Cero !la"/ & in'icates that the result o( an arithmetic or lo"ic
operation is 6ero & I( C1#, the result is 6ero & i( C10, the result is not
6ero.
S! .Si"n (la"/ & hol's the arithmetic si"n o( the result a(ter an
arithmetic or lo"ic instruction is e*ecute' & I( S&0, the si"n )it is 0 an'
the result is ne"ative.
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Function of different flag

T! .Trap !la"/ & use' to 'e)u" a pro"ram usin"

sin"le step techni5ue & I( T (la" is set .i.e. T!1#/ &
8086 "ets interrupte' .Trap or sin"le step interrupt/
a(ter the e*ecution o( each instruction in the
pro"ram & I( T! is cleare' .i.e. T!10/ & the trappin"
or 'e)u""in" (eature is 'isa)le'

;! .;irection !la"/ & selects either the increment or

'ecrement ma'e (or the ;I an'2or SI re"ister 'urin"
the e*ecution o( strin" instructions & I( ;10 &
re"isters are automaticall3 incremental & i( ;1# & the
re"ister are automaticall3 'ecremente' & can set or
cleare' usin" the ST; or :L; instruction
respectivel3.
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Function of different flag
I! .Interrupt !la"/ & controls the operation o( the EINTBF interrupt pin o(
8086 & I( I10 & INTB pin is 'isa)le' & i( I1# & INTB pin is ena)le' & I (la"
can )e set or cleare' usin" the instruction STI or :LI respectivel3.
?! .?ver(lo7 (la"/ & Si"ne' num)ers are represente' in +Fs
complement (orm 7hen the num)er is ne"ative in microprocessor &
Ghen si"ne' num)ers are a''e' or su)tracte' & over(lo7 ma3 occur &
in'icatin" that the result has e*cee'e' the capacit3 o( the machine &
!or e*ample i( the 8&)it si"ne' 'ata %E= .1 H#+6/ is a''e' 7ith the 8&
)it si"ne' 'ata 0+=.1 H+/, the result is 80=.1 &#+8 in +Fs complement
(orm/. This result in'icates an over(lo7 con'ition & over(lo7 (la" is set
'urin" the a)ove si"ne' a''ition & In an 8&)it re"ister, the minimum
an' ma*imum value o( the si"ne' num)er that can )e store' in &#+8
.180=/ an' H#+% .1%!=/ respectivel3 & In a #6 )it re"ister, the
minimum an' ma*imum value o( the si"ne' num)er that can )e
store' is &D+%68 .18000=/ an' HD+%6% .1%!!!=/ respectivel3 & !or
operation an unsi"ne' 'ata, ?! is i"nore'.
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Bu Interface Unit (BIU)

There are (our se"ment re"isters & :S, ;S, SS an' ES.

The (unction o( the :S, ;S, SS an' ES re"ister & in'icate the
startin" a''ress or )ase a''ress o( co'e se"ment, 'ata
se"ment, stacA se"ment an' e*tra se"ment in memor3

The co'e se"ment & contains the instructions o( a pro"ram &

'ata se"ment contains & 'ata (or the pro"ram
The stacA se"ment & hol's the stacA o( a pro"ram & 7hich is
nee'e' 7hile e*ecutin" :LL an' BET instructions & also to
han'le interrupts & e*tra se"ment & a''itional 'ata se"ment &
use' )3 some o( the strin" instructions & minimum si6e o( a
se"ment & one )3te & ma*imum si6e o( a se"ment is 60
K)3tes.
The )ase a''ress & can )e o)taine' )3 a''in" (our )inar3 0s
to the ri"ht most portion o( the content o( correspon'in"
se"ment re"ister 7hich is same as a''in" a he*a'ecimal 'i"it
0 to the ri"ht most portion o( a se"ment re"ister..
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Bu Interface Unit (BIU)
I( the si6e o( t7o 'i((erent se"ments is less than 60K)3tes then
it is possi)le (or t7o se"ments to "et overlappe' .i.e. 7ithin 60
K)3tes allocate' to a se"ment, another se"ment can start/.
Let a particular application in 8086 re5uires co'e se"ment o(
# K)3te si6e an' 'ata se"ment o( + K)3tes si6e. I( the co'e
se"ment is store' in memor3 (rom the a''ress +0000= then it
7ill en' at the memor3 a''ress +0D!!=.
The 'ata se"ment can )e store' (rom the a''ress +0000=
.7hich is the imme'iate ne*t #6&)3te )oun'ar3 in memor3/.
The :S an' ;S re"isters are loa'e' 7ith the value +000= an'
+000= respectivel3 (or runnin" this application in 8086.
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Acceing memor! location

Each a''ress in ph3sical memor3 .B?M2E-B?M chips/ is

Ano7n as ph3sical a''ress. In or'er to access an operan'
.either 'ata or instruction/ (rom memor3 (rom a particular
se"ment, 8086 has to (irst calculate the ph3sical a''ress o(
that operan'.
To (in' the ph3sical a''ress o( that operan', the 8086 a''s
the )ase a''ress o( the correspon'in" se"ment 7ith an o((set
a''ress 7hich ma3 )e either the content o( a re"ister or an 8
)it or #6 )it 'isplacement "iven in the instruction or
com)ination o( )oth, 'epen'in" upon the a''ressin" mo'e
use' )3 the instruction.
The 8086 'esi"ners have assi"ne' certain re"ister.s/ as
'e(ault o((set re"ister.s/ (or certain se"ment re"ister.

4ut this 'e(ault assi"nment can )e chan"e' )3 usin" se"ment

overri'e pre(i* in the instruction 7hich is e*plaine' in the ne*t
chapter .section #0.+/.
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Fetching of an intruction
from memor!

Let us assume that the :S re"ister is havin" the

value D000= an' the I- re"ister is havin" the value
+000=.

To (etch an instruction (rom memor3, the :-8

calculates the memor3 a''ress (rom 7here the ne*t
instruction is to )e (etche', as sho7n )elo79

:S < #0= 1D0000= H 4ase a''ress o( co'e

se"ment

I- 1 +000= ?((set a''ress

D+000= Memor3 a''ress (rom 7here ne*t

instruction is taAen )3 :-8
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"in #etail of 8086

8086 can operate in an3 one o( the t7o mo'es

namel3 minimum mo'e an' ma*imum mo'e.

In minimum mo'e, all the control si"nals (or the

memor3 an' I2? are "enerate' )3 the 8086.

In ma*imum mo'e, some o( the control si"nals

must )e e*ternall3 "enerate'.

This re5uires the a''ition o( an e*ternal )us

controller such as 8+88 7ith 8086.

Some o( the pins in 8086 have same (unction in

)oth mo'es an' some pins have 'i((erent (unction in
the t7o mo'es.
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Function of pin common to
minimum and maximum mode
;#,&;09 These pins act as the multiple*e' a''ress an' 'ata )us
o( the microprocessor & Ghenever LE .''ress Latch Ena)le/ pin is
hi"h .i.e. #/, these pins carr3 a''ress an' 7hen LE pin is lo7 .i.e. 0/,
these pins carr3 'ata & 8sin" t7o e*ternal octal latches such as %0D%D
alon" 7ith the LE si"nal, these pins can )e splitte' into separate
a''ress )us .#,&0/ an' 'ata )us .;#,&;0/.
#$IS6&#8ISD9These pins .a''ress2status )us )its/ are multiple*e'
to provi'e a''ress si"nals #$&#6 an' also status )its S6&SD &
Ghen LE1#, these pins carr3 a''ress an' 7hen LE10, the3 carr3
the status lines & 8sin" one e*ternal octal latch such as %0D%D alon"
7ith the LE si"nal, these pins can )e splitte' into separate a''ress
)us .#$&#6/ an' status lines .S6&SD/.
NMI& Non&MasAa)le Interrupt .NMI/ input is use' to re5uest a
har'7are interrupt. It can not )e 'isa)le' )3 so(t7are. It is a positive
e'"e tri""ere' interrupt an' 7hen it occurs, t3pe+ interrupt occurs in
8086
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Function of pin common to
minimum and maximum mode
INTB9 Interrupt re5uest .INTB/ is a level tri""ere' interrupt use' to
re5uest a har'7are interrupt. 4ut INTB 'epen's on the status o( I!
(la". Ghen I!1#, i( INTB is hel' hi"h .i.e. lo"ic #/, then 8086 "ets
interrupte'. I( I!10, then INTB interrupt is 'isa)le'
:LK& The clocA si"nal must have a 'ut3 c3cle o( DDJ to provi'e
proper internal timin" (or the 8086. Its ma*imum (re5uenc3 can )e ,
or 8 or #0 M=6 (or 'i((erent versions o( 8086 such as 8086, 8086&+
an' 8086&# respectivel3
Kcc& This po7er suppl3 pin provi'es a H,K si"nal to the 8086. The
variation allo7e' in the po7er suppl3 input is L#0J.
MN2 & The minimum2ma*imum mo'e pin is use' to select either
minimum mo'e or ma*imum mo'e operation (or the 8086 )3
connectin" this pin to either H,K 'irectl3 or "roun' respectivel3.
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Function of pin common to
minimum and maximum mode
B;& Ghenever the rea' si"nal . / is a lo"ic 0, the 8086 rea's 'ata
(rom memor3 or I2? 'evice throu"h the 'ata )us.
TEST M The test pin is an input that is teste' )3 the GIT instruction.
I( pin is at lo"ic 0, then GIT instruction (unctions as a N?- .No
operation/ instruction. I( pin is at lo"ic #, then GIT instruction 7aits
(or pin to )ecome a lo"ic 0. This pin is o(ten connecte' to the 48SN
input o( 808% numeric coprocessor to per(orm (loatin" point
operations.
BE;N9 This input is use' to insert 7ait states into the timin" o( the
8086. I( the BE;N pin is at lo"ic # then it has no e((ect on the
operation o( the microprocessor. I( the rea'3 pin is at lo"ic 0, the
8086 enters into 7ait state an' remains i'le. This pin is use' to
inter(ace slo7l3 operatin" peripherals 7ith 8086.
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Function of pin common to
minimum and maximum mode

BESET9 This input causes the 8086 to reset i( it is

hel' at lo"ic # (or a minimum o( (our clocAin"
perio's. Ghenever the 8086 is reset, the :S an' I-
are initiali6e' to !!!!= an' 0000= respectivel3 an'
all other re"isters are initiali6e' 7ith the value
0000=. This causes 8086 to )e"in e*ecutin"
instructions (rom the memor3 a''ress !!!!0=.

>N;9 The >N; connection is the return (or the

po7er suppl3 .Kcc/. 8086 has t7o >N; pins an'
)oth must )e connecte' to "roun' (or proper
operation.
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Function of pin ued in
minimum mode
M2I? 9 The M2 pin selects memor3 or I2?. This pin in'icates 7hether
the 8086 per(orms memor3 rea' or 7rite operation .M2I? 1#/ or I2?
rea' or 7rite operation .M2 10/.
GB9 The 7rite si"nal in'icates that 8086 is sen'in" 'ata to a memor3
or I2? 'evice. Ghen ;B is at lo"ic 0, the 'ata )us contains vali' 'ata
(or memor3 or I2?.
;T2 B9 The 'ata transmit2receive si"nal sho7s that the 8086 'ata )us
is transmittin" .;T2 B1#/ or receivin" .;T2B 10/ 'ata. This si"nal is
use' to control the 'ata (lo7 'irection in e*ternal 'ata )us )u((ers.
;EN9 ;ata )us ena)le si"nal activates e*ternal 'ata )us )u((ers.
Ghen 'ata is trans(erre' throu"h the 'ata )us o( 8086, this si"nal is
at lo"ic 0. Ghen it is hi"h, no 'ata (lo7s in the 'ata )us.
LE9 Ghen ''ress Latch Ena)le .LE/ si"nal is hi"h, it in'icates
that the 8086 multiple*e' a''ress2'ata )us .;#,&;0/ an'
multiple*e' a''ress2status )us .#$2S6&#62SD/ contain a''ress
7hich can )e either memor3 a''ress on I2? port a''ress.
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Function of pin ued in
minimum mode
INT9 The interrupt acAno7le'"e si"nal is a response to the
INTB input pin. The INT si"nal is use' to place the interrupt
t3pe or vector num)er into the 'ata )us in response to INTB
interrupt.
=?L;9 The hol' input re5uests a 'irect memor3 access .;M/
an' is "enerate' )3 ;M controller. I( the =?L; si"nal is
lo"ic #, the 8086 completes the e*ecution the current
instruction an' places its a''ress 'ata an' control )us at the
hi"h impe'ance state. I( the =?L; pin is at lo"ic 0, the 8086
e*ecutes the instructions normall3.

=L;9 =ol' acAno7le'"ement si"nal in'icates that the 8086

has entere' the hol' state an' is connecte' to =L; input o(
;M controller.
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Function of pin ued in
$aximum mode

S+,S#,S0 9 The states )its in'icates the (unction o( the current

)us c3cle. These si"nals are normall3 'eco'e' )3 the 8+88
.)us controller/. !i"ure #D.#0 sho7s the (unction o( these
three status )its in the ma*imum mo'e.
L?:K9 The locA output is use' to locA peripherals o(( the
s3stem. This pin is activate' )3 usin" the L?:K pre(i* on an3
instruction.
BO2>T0 an' BO2>T# 9 The re5uest2"rant pins re5uest ;M
'urin" ma*imum mo'e operation o( 8086. These lines are
)oth )i&'irectional an' are use' to re5uest an' "rant (or a
;M operation.
OS# an' OS09 The 5ueue status )its sho7 the status o( the
internal instruction 5ueue in 8086. These pins are provi'e' (or
access )3 the numeric coprocessor .808%/. !i"ure #D.##
sho7s the (unction o( OS# an' OS0 )its.
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Summar!
The internal architecture o( 8086 mainl3 contains t7o units namel3
)us inter(ace unit .4I8/ an' e*ecution unit .E8/.
The 4I8 taAes care o( (etchin" the instructions an' 'ata (rom memor3
into the processor usin" the content o( a se"ment re"ister an' o((set.
There e*ists a 6&)3te instruction 5ueue in 8086 7hich is use' to store
the recentl3 (etche' instructions into the :-8. This is use' to spee'
up the e*ecution o( a pro"ram.
There are (our memor3 se"ments namel3 co'e, 'ata, stacA, e*tra
se"ments in 8086 an' their )ase a''ress is in'icate' )3 a''in" (our
)inar3 0s to the ri"ht o( the correspon'in" se"ment re"isterFs content.
The ma*imum si6e o( a memor3 se"ment is 60 K)3tes.
!or (etchin" either an instruction )3te or 'ata, 8086 a''s the )ase
a''ress o( the particular se"ment 7ith an o((set a''ress present
either in a re"ister or "iven as 8 or #6 )it 'isplacement in the
instruction or com)ination o( )oth.
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Summar!

The 8086Fs 'esi"ner have alrea'3 (i*e' up 'e(ault o((set

re"ister.s/ (or ever3 se"ment re"ister. 4ut this can )e chan"e'
usin" se"ment overri'e pre(i* in the instruction.
The E8 contains the L8, "eneral purpose re"isters an' (la"
re"ister 7hich are use' 'urin" the e*ecution o( an instruction.
The (la" re"ister contain 'i((erent (la"s 7hich can )e classi(ie'
into status (la"s an' control (la"s. The status (la"s re(lect the
result o( arithmetic or lo"ical operation an' the control (la"s
control the operation 'urin" e*ecution o( instructions.
8086 can )e operate' in minimum mo'e or ma*imum mo'e.
The a''ress )us an' 'ata )us si6e are +0 )its an' #6 )its
respectivel3 in 8086. The 8086 can access ma*imum memor3
si6e o( # M)3tes .1++0/ as it has +0 )it a''ress )us.
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%e! term
E*ecution unit .E8/ inclu'es the L8, ei"ht #6&)it "eneral purpose
re"isters, a #6 )it (la" re"ister an' control unit in 8086. This unit is
responsi)le (or e*ecutin" the instructions in 8086.
4us inter(ace unit .4I8/ inclu'es an a''er (or a''ress calculations,
(our #6&)it se"ment re"isters .:S,;S,SS an' ES/, a #6 )it instruction
pointer .I-/, a 6 )3te instruction 5ueue an' )us control lo"ic. This unit
is responsi)le (or (etchin" the instruction an' 'ata into 8086 (rom
memor3 or I2? 'evice.
:o'e se"ment contains the instructions o( a pro"ram
;ata se"ment contains 'ata (or the pro"ram
StacA se"ment hol's the stacA o( a pro"ram
E*tra se"ment is an a''itional 'ata se"ment an' is also use' )3
some o( the strin" instructions.
Se"ment Be"ister in'icates the startin" or )ase a''ress o( a se"ment
in memor3.
?((set is a #6&)it num)er that is a''e' to the )ase a''ress o( a
se"ment to select a )3te o( instruction or 'ata (rom memor3.
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%e! term

!la"s sho7 in(ormation relate' to the result o( arithmetic or

lo"ic operation hel' in L8. !la"s in the (la" re"isters can )e
classi(ie' into status (la"s an' control (la"s.
Instruction 5ueue is 6&)3tes lon" an' it stores the pre(etche'
instructions (rom the memor3 an' is use' to spee' up the
e*ecution o( a pro"ram.
Minimum mo'e operation M In this mo'e, all the control si"nals
(or the memor3 an' I2? are "enerate' )3 the microprocessor
itsel(
Ma*imum mo'e operation M In this mo'e, some o( the control
si"nals must )e e*ternall3 "enerate' usin" )us controller such
as 8+88.
Belocata)le pro"ram & relocata)le pro"ram is one 7hich can
)e place' an37here in the memor3 map o( 8086 an' e*ecute'
7ithout an3 mo'i(ication in the pro"ram.
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