Source-Degenerated CTLE In Practice

EE290C – Spring 2011 • Several issues to watch out for

• Finite input device ro
• Tail node ro, Cpar
Lecture 7: Equalization: CTLE and FIR I • Self loading/BW limits

Elad Alon
Dept. of EECS

EE290C Lecture 5 4

CTLE Review Source-Degenerated CTLE In Practice

• Generally implemented on RX • Several issues to watch out for
• (Higher Z than TX – less power for same V swing/gain) • Finite input device ro
• Tail node ro, Cpar
• Self loading/BW limits

EE290C Lecture 5 2 EE290C Lecture 5 5

CTLE Review: Circuit Design FIR Equalizer

• Most common design: source-degenerated • Most often implemented at the TX
• Delay is easy – just need flip-flops

• Typical mixed-signal implementation:

50Ω
data_in Vout
iout+ iout-
z-1

sgn1 d- d+
z-1
c[N:0] Ib
sgn2

EE290C Lecture 5 3 EE290C Lecture 5 6

TX FIR Direct Implementation A Middle Ground
No Filter 3-tap FIR
• Partition segments
50 Ω 50 Ω based on knowledge Ω
data_in
Imax Cpar
Vout data_in
0 – Imax 3Cpar
Vout
of possible coefficients*
-1
z

z-1
0 – Imax • Tradeoff between
• Cpar Æ analog BW, power
0 – Imax
• Digital complexity, power
• FIR coefficients generally not fixed
• Depend on channel, temp., process, etc. • “Optimum” point depends on technology,
• Direct approach very flexible data-rate
• But can have high parasitics (self-loading) – especially • Generally don’t want to focus on just the end points
with large number of taps • * J. Zerbe et al., “Equalization and Clock Recovery for a 2.5 – 10Gb/s 2-PAM/4-PAM Backplane
Transceiver Cell,” IEEE JSSC, Dec. 2003
EE290C Lecture 5 7 EE290C Lecture 5 10

Fundamental Problem What About VM Drivers?

EE290C Lecture 5 8 EE290C Lecture 5 11

Alternate Approach with Min. Cpar

EE290C Lecture 5 9