Administrative

EE290C – Spring 2011 • Elad will be out of town this Thurs.

• Make-up lecture will be held on Mon. 1-31 1:30-3:00pm
in 127 Dwinelle
Lecture 3: Basic Transmitters and Receivers • Office hours on Thurs. cancelled – available over
email

Elad Alon
Dept. of EECS

EE290C Lecture 3 2

Plain Old Inverters – Why Not? Outline

• Signaling Basics • RX Circuit Design
• Single-ended vs. differential • Comparator review
• “Current-mode” vs. • Deserialization
“Voltage-mode” signaling options
• Termination

• TX Circuit Design
• Z control
• CML, VM drivers
• Power vs. swing
• Serialization options

EE290C Lecture 3 3 EE290C Lecture 3 4

Single-Ended Signaling So Why Even Mention This?

rcvr
din xmtr
ref dout
Cd Cr

• RX: comparing against a shared reference

• Reference may be implicit (i.e., ground/supply)
• Mismatch between shared and individual lines
• TX: generates large variations on power supply
• SSO – simultaneous switching outputs
• No XTALK immunity
EE290C Lecture 3 5 EE290C Lecture 3 6
Classic Debate “Voltage-Mode” vs. ”Current-Mode”
• “Differential must be twice as fast as single-
ended in order to win”

• Reality more complicated

• E.g., power supply to signaling pin ratio higher in S.E.

• Short “answer” • Transmission line has both voltage and current…

• Differential a lot easier to build and get right the first • Terminology unfortunately heavily overloaded
time
• Whether or not Zo of driver is high
• Can make S.E. work – but often a lot more painful
• How Zo of driver is set
• What sets output swing
EE290C Lecture 3 7 EE290C Lecture 3 8

“Voltage-Mode” vs. ”Current-Mode” Another View

“Low Impedance” “High Impedance”
VS
Ended
Single

- +
d
VS/2 ref -

shared
Differential

+ -

- d
d

• RX opposite of TX
• Signal integrity implications?
EE290C Lecture 3 9 EE290C Lecture 3 10

Why Terminate? External vs. Internal Termination

• Internal: makes package L, pad C part of T-line

• External: chip/package become a stub
• If want on-die term need to control its value…
EE290C Lecture 3 11 EE290C Lecture 3 12
Untrimmed Poly Termination Ri, Ci, and Pad Complexity
1.00

Rs L
• Main issue is variation: +/-20% at one temperature 0.80

Normalized amplitude
LI
• But Gd C 0.60

CI
• It’s relatively linear RI
0.40

"low_CL"

• ESD robust 0.20 "1_drop"

"2_drop"
"4_drop"

• Low parasitics…
"8_drop"
Ci, Ri 0.00
1e+008 1e+009
typically dominate Freq (Hz)

• LPF at pad can dominate overall channel

• Example: 500fF ESD, 500fF driver, 500fF wire

• Bandwidth ~4GHz with double-terminated link

• Even worse in busses (or if add big series R)…

EE290C Lecture 3 13 EE290C Lecture 3 14

Active Terminations AC vs. DC Termination

• With diff. can terminate to
complement
• High Z Æ lower power RAC Rx
• See more shortly

• TX sets common-mode VCM

• Can be inconvenient RCM

• May need wide CM range

RAC Rx
• AC-coupled + AC-term
• Places some requirements on RCM

data though VCM

EE290C Lecture 3 15 EE290C Lecture 3 16

TX Design: Series vs. Parallel Termination Alphabet Soup

• LVDS, CML
• GTL, GTL+, RSL, …

• VM, CM
• HCM, LCM

• All same basic principles

• Look at two representative circuits to understand
some of the more fundamental tradeoffs

EE290C Lecture 3 17 EE290C Lecture 3 18

CML TX + RX Term Side Note: Pre-Driver
VD D VDD

50Ω 50Ω

Zo = 50Ω

Tx Rx
Zo = 50Ω

Io = - 21m A

Dou ble-term inated

on-ch ip

EE290C Lecture 3 19 EE290C Lecture 3 20

CML Power Consumption Differential VM TX + RX

• Main motivation: can reduce power for same
swing/supply

EE290C Lecture 3 21 EE290C Lecture 3 22

Simplified Model And Power Bad News: Extra Complexity

• Driver impedance (termination) now set totally
by devices
• Some sort of impedance control is critical

• “High-swing” driver:

EE290C Lecture 3 23 EE290C Lecture 3 24

 Low-Swing VM Driver Impedance Control
• Old standards often required large swings
(>1V diff. p2p)
• More modern designs use much lower swings
(~200-400mV diff. p2p) to save power

• Low-swing VM driver:

EE290C Lecture 3 25 EE290C Lecture 3 26

Another Approach Serialization: Input vs. Output

• On-chip clocks often slower than off-chip data-
rates
• Need to take a set of parallel on-chip data and serialize it

• Can serialize either at input of TX or at final output

EE290C Lecture 3 27 EE290C Lecture 3 28

Serialization: Input vs. Output Basic TX Final Notes

• Input ser. requires on-chip circuitry to run at full • Usually need many peripheral controls
line rate • Zo, edge-rate, etc.
• May lead to high power consumption
• In older technologies (0.35um) was hard to support high-
freq. clocks • Keep tuning out of the high-speed signal path
D0 D1 D2 • P(High-speed, low res. + low-speed, high-res.) <<
• Output ser. noved burden data(ck0) P(high-speed, high-res.)
clock(ck3)
at pad RTERM
• At the time was highest BW RTERM out_b
ck3 out

• Limit in both designs: edge rate x8

• Either for the clock or for the data

d0 d0

EE290C Lecture 3 29 EE290C Lecture 3 30

Basic TX Final Notes Basic RX
• Lots of research focused on reduced signaling • Simplest: RX is just a comparator @ fbit
power • (Clocking later)
• I.e., power spent by actual final driver

• Key things to watch out for:

• Watch out for “overhead” (pre-drivers) • High sensitivity (low noise, low offset/hysteresis)
• Especially with emerging low-swing designs, • Common-mode input range
overhead can actually dominate • Supply/common-mode rejection
• Psig (400mV diff. p2p): • Max. clock rate
• Pdigital (100 min. sized inverters @ 10GHz): • Power consumption

• More on this later

EE290C Lecture 3 31 EE290C Lecture 3 32

Typical Design StrongArm Review

EE290C Lecture 3 33 EE290C Lecture 3 34

Higher Speeds

EE290C Lecture 3 35