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Elad Alon
Dept. of EECS
*Poulton’99
EE290C Lecture 4 4
tp,data,1
D1 D Q TX RX D Q DRX1
14
13 tp,data,c
12 TX RX tdel0
11
10 clk
9
8
7
6
100 150 200 250 300 350
T (ps)
bit
EE290C Lecture 4 9 EE290C Lecture 4 12
In General: CDR Bang-Bang (Alexander) Phase Detector
• CDR = Clock and Data Recovery
Vin dn
• Recover clock phase and/or frequency based on data
itself
• If phase only, need a frequency reference data Clk
en
• Several advantages vs. fixed timing
edge Clk
• Don’t have to match delays/paths (mesochronous)
• Allows separate crystals (plesiochronous) • Edge clock Tsym/2 away
from data
• But, CDR isn’t free • Derive early/late from data
• And places some requirements on data and edge samples:
• Dn: (dn != en) & (dn-1 != dn)
• Up: (dn == en) & (dn-1 != dn)
EE290C Lecture 4 13 EE290C Lecture 4 16
Elastic
Buffer
• Transmit data @ f1
• Recover clock and data @ f1 on RX
• Elastic buffer (FIFO) transfers data from f1 to f2
Elastic
Buffer
EE290C Lecture 4 20
EE290C Lecture 4 21