RX FIR Equalizers

EE290C – Spring 2011 • Currently not very popular – why?

Lecture 8: Equalization: FIR II and DFE

Elad Alon
Dept. of EECS

EE290C Lecture 8 4

VM TX + Equalization Coefficient Shuffling Architecture

• First implementation (K.-L. J. Wong, JSSC 2004): • Lee, Razavi, CICC 2001

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Constant Current VM TX Design Shuffling Implementation

• D. Dettloff, ISSCC 2010 • Can shuffle digital tap coefficients or analog
inputs

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 Interleaving A Reminder
• Often combined with tap shuffling
• Ex: J. Jaussi, ISSCC 2004

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DFE: Implementation Self-Loading

• Creates bandwidth 0.6

RX_in C = 20fF
limit 0.5 L
C = 40fF
• No matter how 0.4 L
C = 80fF
much power you L

m
0.3

G
spend 0.2
0.1

• DFE has increased 0

• Design driven by feedback latency constraint “self-loading” due 0 0.2 0.4 0.6
GBW/(ω /γ )
0.8 1
T
• New summer output needs to settle (at comparator to taps…
input) within one bit time

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DFE Summer Design DFE Summer Design

• Key constraint:
tdig_fb + tana_settle = Tbit

• Need some Nτ of
settling:
τsum = (Tbit – tdig_fb)/Nτ

• Typically want ~4τ for ~98% settling

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Maximum Cancelled ISI Split Summation
!0Gb/s DFE
0.05 • B. Leibowitz, ISSCC 2007
tdig = 30ps
0.04 tdig = 40ps
tdig = 50ps
0.03
m
G

0.02

0.01

0
0 2 4 6 8 10
M
DFE

• There is a maximum MDFE you can achieve

• Don’t forget that every tap has to handle worst-
case possible ISI
• Implies max. number of taps (in given tech.)
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TX FIR RX DFE Duality All CML Design

• Can use same techniques we talked about in TX • H. Wang, VLSI 2009
for RX DFE • Over 20Gb/s in 65nm CMOS
• But still need to watch out for digital power…

Vin
d0

clk

0 – Imax/2
z-1
d0
d1 d1
0 – Imax/2 d2
z-1
d1
d2
0 – Imax/4 d2

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Closing the First Tap Loop Unrolling

• K. Parhi, ISCAS 1990

+1+α +α d n | d n −1 = 1
+1-α
+α xn d n −1
dClk D Q
-α
-1+α
-α
d n | d n −1 = 0

-1-α dClk

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Extended Loop Unrolling Practical DFE Design Issues

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LE + DFE Practical DFE Design Issues

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Practical DFE Design Issues

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