CHNG 4: GHEP NI

H THNG VI X LY
Pham Th Duy
ptduy@yahoo.com
GHEP NI H THNG VI X LY
Gii thiu v b nh.
Ghep ni vi x ly vi b nh
Cac thut ng v b nh
Dung lng
Kbit, Mbit, Gbit
T chc b nh
Cac ng ia chi - Address lines
Cac ng d liu - Data lines
Tc / inh thi: Speed / Timing
Thi gian truy cp - Access time
Kha nng ghi d liu - Write ability
ROM
RAM

Cac loai b nh ROM
Mask Rom
PROM OTP
EPROM UV_EPROM
EEPROM
Flash memory
Cac loai b nh RAM
SRAM
DRAM
NV-RAM
SRAM CMOS
Internal lithium battery
Control circuitry to monitor Vcc
Cac vi mach nh - Memory Chip
8K SRAM
to be specific:
8Kx8 bits SRAM
6264
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
CS2
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
CS1
OE
WE
S khi 6264
Bang m ta hoat ng cua 6264
Vi mach nh ROM 2764
8K EPROM
Dung lng:
8Kx8 bits EPROM
2764
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
VPP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C
G
P
S khi 2764
Chip enable
Output enable
Cac ch hoat ng
Lp trinh cho 2764
Sau khi xoa bng en tia cc tim UV-EPROM):
Tt ca cac bit trong M2764A co mc 1.
Chi co mt cach duy nht bin bit 0 thanh 1 la bng
en tia cc tim (ultraviolet light erasure)
Ch lp trinh c chon khi:
VPP cp 12.5V
E va P co mc thp TTL
Cp d liu ti cac chn d liu, ia chi ti cac chn
ia chi va cp xung lp trinh.

Cac chn tin hiu cua 8088
8088
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
A16 / S3
A17 / S4
A18 / S5
A19 / S6
SSO
DEN
DT / R
IO / M
RD
WR
ALE
INTA
MN / MX
READY
CLK
RESET
TEST
HLDA
HOLD
NMI
INTR
Cac chn ngun va GND
Vcc chn 40
Gnd chn 1 va 20
Cac chn ia chi - Address Pins
AD0..AD7
A8..A15
A19/S6, A18/S5, A17/S4, A16/S3
Cac chn d liu - Data Pins
AD0..AD7
Cac chn iu khin - Control Pins
MN/MX (input)
Cho phep chon ch 9o65 hoat ng cua CPU
MIN mode: cu hinh ti thiu khng co ng x ly
MAX mode co ng x ly toan hoc
READY (input)
Khi tac ng mc thp CPU se chuyn qua trang
thai ch trong cac chu ky truy cp BUS.
CLK (input)
Cung cp xung inh thi c ban cho CPU
RESET (input)
CPU k thuc trang thai hoat ng hin hanh
Cn gi mc cao trong it nht 4 chu ky clock
Cac chn iu khin - Control Pins
TEST (input)
Khi cung cp mc cao CPU se ngng hoat ng
cho ti khi ht mc cao.
HOLD (input)
Ngo vao yu cu DMA t DAM controller
HLDA (output)
Ngo ra chp nhn yu cu DMA.
Cac chn iu khin ngt - Control Pins
INTR (input)
Ngo vao yu cu ngt - Interrupt request
INTA (output)
Ngo vao chp nhn yu cu ngt - Interrupt
Acknowledge
NMI (input)
Ngo vao yu cu ngt khng che c
Non-maskable interrupt
Cac chn iu khin b nh va vao ra
Memory/IO Control Pins
DEN (output)
Data Enable cho phep d liu
Tac ng mc thp khi CPU truy cp d liu bn ngoai
DT/R (output)
Data Transmit/Receive Truyn nhn d liu
Khi tac ng mc cao, chiu truyn d liu t vi x ly ti
b nh/vao ra.
Khi tac ng mc thp, CPU oc d liu t b nh hoc
vao ra.
IO/M (output)
Input Output/Memory
Khi truy cp I/O CPU tac ng tin hiu nay mc cao
Khi truy cp b nh CPU tac ng tin hiu nay mc thp

Cac tin hiu iu khin b nh va vao ra
RD (output)
Khi oc d liu t ngoai vao CPU tac ng tin hiu
nay mc thp
WR (output)
Khi ghi d liu ra ngoai CPU tac ng tin hiu nay
mc thp
ALE (output)
Address Latch Enable cho phep cai ia chi
CPU cung cp tin hiu nay mc cao cai cac d
liu qua cac b cai.
Khi mc cao cac ng AD0..AD7, A19/S6,
A18/S5, A17/S4, A16/S3 la cac tin hiu ia chi.

Tin hiu xung ng h - Clock Signal
Cung cp CPU inh thi cac hoat ng
va ng b cac tin hiu cua chung.
Cn cp vao xung vung co tn s khng
i va tt nht co 2/3 chu ky nhim vu.
8086 Signals
ASYNC
AEN2
RDY2
AEN1
RDY1
CSYNC
EF1
F/C
X2
X1
RES
READY
CLK
PCLK
OSC
RESET
8088
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
A16 / S3
A17 / S4
A18 / S5
A19 / S6
SSO
DEN
DT / R
IO / M
RD
WR
ALE
INTA
MN / MX
READY
CLK
RESET
TEST
HLDA
HOLD
NMI
INTR
R
C
5V
B cung cp cac tin hiu Clock, Reset va Ready

8284
Minimum Mode
8088
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DEN
DT / R
IO / M
RD
WR
ALE
Minimum Mode
8088
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DEN
DT / R
IO / M
RD
WR
ALE
Minimum Mode
MEMORY
D7 - D0
A7 - A0
A15 - A8
A19 - A16
RD
WR
8088
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DEN
DT / R
IO / M
RD
WR
ALE
inh thi oc b nh va vao ra cua CPU 8088
Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read
ALE
T1
CLOCK
T2 T3 T4
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DT/R
__
IO/M
__
____
RD
DEN
______
A15 - A8
A7 - A0 D7 - D0 (from memory)
A19 - A16 S6 - S3
if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW
Will the circuit be able to perform
memory read?
;assume that initially the values
;of the registers are:
;BX = 1234, DS = 9000

MOV AL, [BX]
Processor Timing Diagram of 8088 (Minimum Mode)
for Memory or I/O Read
ALE
T1
CLOCK
T2 T3 T4
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DT/R
__
IO/M
__
____
RD
DEN
______
A15 - A8
A7 - A0 D7 - D0 (from memory)
A19 - A16 S6 - S3
if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW
Minimum Mode
MEMORY
D7 - D0
A7 - A0
A15 - A8
A19 - A16
RD
WR
8088
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DEN
DT / R
IO / M
RD
WR
ALE
Minimum Mode
MEMORY
D7 - D0 Q7 - Q0
OE
LE
74LS373
D7 - D0 Q7 - Q0
OE
LE
74LS373
D7 - D4 Q7 - Q4
OE
LE
D3 - D0 Q3 - Q0
74LS373
GND
GND
GND
D7 - D0
A7 - A0
A15 - A8
A19 - A16
RD
WR
8088
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DEN
DT / R
IO / M
RD
WR
ALE
Octal Transparent Latch with 3-State Output
74LS373
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
OE
LE
inh thi oc b nh va vao ra cua CPU 8088
Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read
ALE
T1
CLOCK
T2 T3 T4
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DT/R
__
IO/M
__
____
RD
DEN
______
A19 - A0
from 74LS373 to memory
A7 - A0 D7 - D0 (from memory)
S6 - S3 A19 - A16
A19 - A0 from 74LS373
if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW
A15 - A8
H thng se hoat ng nh t nao khi oc bo nh
Will the circuit be able to perform memory read?
;Gia s cac gia tri cua cac thanh ghi la:
;BX = 1234, DS = 9000

MOV AL, [BX]
inh thi oc b nh vi cac b cai 74373
Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read (with 74373)
ALE
T1
CLOCK
T2 T3 T4
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DT/R
__
IO/M
__
____
RD
DEN
______
A19 - A0
from 74LS373 to memory
A7 - A0 D7 - D0 (from memory)
S6 - S3 A19 - A16
A19 - A0 from 74LS373
if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW
A15 - A8
Ch MIN - Minimum Mode
D7 - D0 Q7 - Q0
OE
LE
74LS373
MEMORY
D7 - D0 Q7 - Q0
OE
LE
74LS373
D7 - D4 Q7 - Q4
OE
LE
D3 - D0 Q3 - Q0
74LS373
GND
GND
GND
D7 - D0
A7 - A0
A15 - A8
A19 - A16
RD
WR
8088
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DEN
DT / R
IO / M
RD
WR
ALE
D liu se c oc ghi nh th nao?
Ch MIN - Minimum Mode
MEMORY
D7 - D0 Q7 - Q0
OE
LE
74LS373
D7 - D0 Q7 - Q0
OE
LE
74LS373 8088
AD7 - AD0
A15 - A8
A19/S6 - A16/
S3
DEN
DT / R
IO / M
RD
WR
ALE
D7 - D4 Q7 - Q4
OE
LE
74LS373
D3 - D0 Q3 - Q0
GND
GND
GND
D7 - D0 A7 - A0 B7 - B0
E
DIR
74LS245
A7 - A0
A15 - A8
A19 - A16
RD
WR
inh thi oc b nh cua 8088 trong ch MIN (co 74245)
Processor Timing Diagram of 8088 (Minimum Mode)
for Memory or I/O Read (with 74245)
ALE
T1
CLOCK
T2 T3 T4
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DT/R
__
IO/M
__
____
RD
DEN
______
A19 - A0
from 74LS373 to memory
S6 - S3 A19 - A16
A19 - A0 from 74LS373
if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW
D7 - D0
from memory to 74LS245
D7 - D0 (from memory)
D7 - D0 from
74LS245
garbage A7 - A0
A15 - A8
Minimum Mode
MEMORY
D7 - D0 Q7 - Q0
OE
LE
74LS373
D7 - D0 Q7 - Q0
OE
LE
74LS373 8088
AD7 - AD0
A15 - A8
A19/S6 - A16/
S3
DEN
DT / R
IO / M
RD
WR
ALE
D7 - D4 Q7 - Q4
OE
LE
74LS373
D3 - D0 Q3 - Q0
GND
GND
GND
D7 - D0 A7 - A0 B7 - B0
E
DIR
74LS245
A7 - A0
A15 - A8
A19 - A16
RD
WR
Minimum Mode
MEMORY
D7 - D0 Q7 - Q0
OE
LE
74LS373
D7 - D0 Q7 - Q0
OE
LE
74LS373 8088
AD7 - AD0
A15 - A8
A19/S6 - A16/
S3
DEN
DT / R
IO / M
RD
WR
ALE
D7 - D4 Q7 - Q4
OE
LE
74LS373
D3 - D0 Q3 - Q0
GND
GND
GND
D7 - D0 A7 - A0 B7 - B0
E
DIR
74LS245
A7 - A0
A15 - A8
A19 - A16
RD
WR
Minimum Mode
B nh
MEMORY
D7 - D0 Q7 - Q0
OE
LE
74LS373
D7 - D0 Q7 - Q0
OE
LE
74LS373 8088
AD7 - AD0
A15 - A8
A19/S6 - A16/
S3
DEN
DT / R
IO / M
RD
WR
ALE
D7 - D4 Q7 - Q4
OE
LE
74LS373
D3 - D0 Q3 - Q0
GND
GND
GND
D7 - D0 A7 - A0 B7 - B0
E
DIR
74LS245
A7 - A0
A15 - A8
A19 - A16
RD
WR
ch 8088 m i BUS a d
liu trong ch MIN -Simplified Drawing of
8088 Minimum Mode
D7 - D0
A7 - A0
A15 - A8
A19 - A16
MEMR
MEMW
Minimum Mode
B nh
MEMORY
D7 - D0
A19 - A0
RD
WR
ch 8088 m
i BUS a
d liu
trong ch MIN
Simplified
Drawing of
8088 Minimum
Mode
D7 - D0
A19 - A0
MEMR
MEMW
When Memory is selected?
Minimum Mode
MEMORY
D7 - D0
A19 - A0
RD
WR
Simplified
Drawing of
8088 Minimum
Mode
D7 - D0
A19 - A0
MEMR
MEMW
CS
2
20
bytes or 1MB
inh vi b nh trong khng gian ia chi 1MB
What are the memory locations of a 1MB (2
20
bytes) Memory?
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
00000 0000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
Vi du: 34FD0

0011 0100 1111 1101 0000
Giao tip b nh 1MB vi vi x ly 8088
Interfacing a 1MB Memory to the 8088 Microprocessor
23 00000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
:
:
45
98
27
39
42
88
07
F4
8A
:
:
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
:
:
:
:
:
:
:
:
A19
A0
:
D7
D0
:
RD
WR
A19
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
CS
Thay vi giao tip vi b nh 1MB, iu gi se xay ra
nu s dung b nh 512KB
Instead of Interfacing 1MB, what will happen if
you interface a 512KB Memory?
A18
A0
:
D7
D0
:
MEMR
MEMW XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
23 00000
00001 95
:
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
A19
B nh 512KB se c inh vi nh th nao?
What are the memory locations of a 512KB
(2
19
bytes) Memory?
A18 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
Giao tip mt b nh 512KB vi vi x ly 8088
A18
A0
:
D7
D0
:
MEMR
MEMW XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
23 00000
00001 95
:
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
A19
Chung ta lam gi vi A19?
iu gi xay ra khi oc ia chi vt ly A0023?
A18
A0
:
D7
D0
:
MEMR
MEMW XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
A000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
23 00000
00001 95
:
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
A19
iu gi xay ra khi oc ia chi vt ly A0023?
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
A0023 1010 0000 0000 0010 0011
A19 khng c ni ti b nh vi vy
nu 8088 a ra logic 1 hay khng b
nh u khng nhn c

iu gi xay ra khi oc ia chi vt ly 20023?
A18 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
20023 0010 0000 0000 0010 0011
Vi b nh ia chi 20023H cung khng
khac gi ia chi A0023H

Giao tip hai b nh 512KB vi vi x ly 8088
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
A19
23 00000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
97 00000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
Giao tip hai b nh 512KB vi vi x ly 8088
Xay ra: Tranh chp BUS. Hai b nh
se cung cung cp d liu ra D7-D0
tai cung mt thi im khi vi x ly
thc hin chu ky oc b nh. Nu
hai d liu nay khac mc logic se
gy h hong BUS.
Giai phap: S dung A19 lam b
chon. Nu A19=1 b nh phia trn
se c chon va ngc lai.
Giao tip hai b nh 512KB vi vi x ly 8088
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
A19
23 00000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
97 00000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
Vi tri cua hai b nh trong vung ia chi 1MB
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
A19
23 00000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
97 00000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
Giao tip hai b nh 512KB vi vi x ly 8088
Khi P cp mt
ia chi nm gia
khoang 0000 ti
7FFFF, b nh
nay se c
chon.
Khi P cp mt ia
chi nm gia khoang
80000 ti FFFFF,
b nh nay se c
chon.
Giao tip hai b nh 512KB vi vi x ly 8088
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
A19
23 00000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
97 00000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
Giao tip hai b nh 512KB vi vi x ly 8088
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
A19
23 00000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
97 00000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
A18
A0
:
D7
D0
:
RD
WR
A19
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
A19
23 00000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
97 00000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
iu gi se xay ra khi bo b nh phia di?
iu gi se xay ra khi bo b nh phia di?
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
A19
23 00000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
When the P outputs
an address between
80000 to FFFFF,
this memory is
selected
Khi P cp ia chi
trong khoang t
00000 ti 7FFFF,
khng co b nh nao
c chon.
!
Giai ma u va giai ma thiu
Giai ma u
Khi s dung tt ca cac ng ia chi cua CPU
kt ni chon b nh va vao ra
Giai ma thiu.
Khi mt hoc nhiu ng ia chi cua CPU
khng c s dung.
Khi giai ma thiu mt nh co th co nhiu
ia chi.
Giai ma u
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
A19
23 00000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
Giai ma u
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
A19 cn phai bng 1 b nh c
chon
Giai ma u
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
Do o nu VXL cp cac ia chi t
00000 ti 7FFFF, thi A19 co logic 0,
b nh se khng c chon.
Giai ma thiu
A18
A0
:
D7
D0
:
MEMR
MEMW XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXX IP
XXXX DI
23 00000
00001 95
:
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
A19
Giai ma thiu
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
Gia tri cua A19 khng quan trong vi b nh, no
khng quyt inh b nh co c chon hay khng

Giai ma thiu
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
ia chi truy cp

Giai ma thiu
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
ia chi truy cp

Giao tip vi hai b nh 512KB
8088
Minimum
Mode
A18
A0
:
D7
D0
:
MEMR
MEMW
A19
512KB
#2
A18
A0
:
D7
D0
:
RD
WR
CS
512KB
#1
A18
A0
:
D7
D0
:
RD
WR
CS
Giao tip vi 1 b nh 512KB
8088
Minimum
Mode
A18
A0
:
D7
D0
:
MEMR
MEMW
A19
512KB
A18
A0
:
D7
D0
:
RD
WR
CS
Giao tip vi 1 b nh 512KB (version 2)
8088
Minimum
Mode
A18
A0
:
D7
D0
:
MEMR
MEMW
A19
512KB
A18
A0
:
D7
D0
:
RD
WR
CS
Giao tip vi 1 b nh 512KB (version 3)
8088
Minimum
Mode
A18
A0
:
D7
D0
:
MEMR
MEMW
A19
512KB
A18
A0
:
D7
D0
:
RD
WR
CS
Giao tip vi 04 b nh 256 KB
8088
Minimum
Mode
A17
A0
:
D7
D0
:
MEMR
MEMW
A18
256KB
#3
A17
A0
:
D7
D0
:
RD
WR
CS
A19
256KB
#2
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#1
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#4
A17
A0
:
D7
D0
:
RD
WR
CS
Giao tip vi 04 b nh 256 KB
8088
Minimum
Mode
A17
A0
:
D7
D0
:
MEMR
MEMW
A18
256KB
#3
A17
A0
:
D7
D0
:
RD
WR
CS
A19
256KB
#2
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#1
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#4
A17
A0
:
D7
D0
:
RD
WR
CS
Ban inh vi tri cho cac chip nh
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210
00000H
3FFFFH
0000
0011

0000
1111

0000
1111
0000
1111
0000
1111

-----
0100
0111

0000
1111
0000
1111
0000
1111
0000
1111
Giao tip vi 04 b nh 256 KB
8088
Minimum
Mode
A17
A0
:
D7
D0
:
MEMR
MEMW
A18
256KB
#3
A17
A0
:
D7
D0
:
RD
WR
CS
A19
256KB
#2
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#1
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#4
A17
A0
:
D7
D0
:
RD
WR
CS
Giao tip vi 04 b nh 256 KB
8088
Minimum
Mode
A17
A0
:
D7
D0
:
MEMR
MEMW
A18
256KB
#3
A17
A0
:
D7
D0
:
RD
WR
CS
A19
256KB
#2
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#1
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#4
A17
A0
:
D7
D0
:
RD
WR
CS
Giao tip vi 04 b nh 256 KB
8088
Minimum
Mode
A17
A0
:
D7
D0
:
MEMR
MEMW
A18
256KB
#3
A17
A0
:
D7
D0
:
RD
WR
CS
A19
256KB
#2
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#1
A17
A0
:
D7
D0
:
RD
WR
CS
256KB
#4
A17
A0
:
D7
D0
:
RD
WR
CS
I1
I0
O3
O2
O1
O0
Giao tip vi cac b
nh 8KB
8088
Minimum
Mode
A12
A0
:
D7
D0
:
MEMR
MEMW
A13
A14
8KB
#2
A12
A0
:
D7
D0
:
RD
WR
CS
8KB
#1
A12
A0
:
D7
D0
:
RD
WR
CS
8KB
#?
A12
A0
:
D7
D0
:
RD
WR
CS
A15
A16
A17
A18
A19
:
:
8088
Minimum
Mode
A12
A0
:
D7
D0
:
MEMR
MEMW
A13
A14
8KB
#2
A12
A0
:
D7
D0
:
RD
WR
CS
8KB
#1
A12
A0
:
D7
D0
:
RD
WR
CS
8KB
#128
A12
A0
:
D7
D0
:
RD
WR
CS
A15
A16
A17
A18
A19
:
:
Giao tip vi 128 b
nh 8KB
8088
Minimum
Mode
A12
A0
:
D7
D0
:
MEMR
MEMW
A13
A14
8KB
#2
A12
A0
:
D7
D0
:
RD
WR
CS
8KB
#1
A12
A0
:
D7
D0
:
RD
WR
CS
8KB
#128
A12
A0
:
D7
D0
:
RD
WR
CS
A15
A16
A17
A18
A19
:
:
Giao tip vi 128 b
nh 8KB
Ban b nh
A19
to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654

AAAA
3210

-----

----


----


----


----


----


-----

----


----


----


----


----

74LS138: B giai ma 3- 8
S chn
Logic Diagram
A
B
C
E1
E2
E3
138
0
1
2
3
4
5
6
7

Outputs
Select
Inputs
Enable
Inputs
Bang hoat ng cua 74LS138
Xp tng cac 74LS138 tng s
ng giai ma.
74138 tac ng mt ngo ra vi mt
trang thai nhi phn go vao.
Co th xp tng cac 74138 tng
s ng giai ma cho h thng.
Chu y trn mi tn tin hiu se co thi
gian tr lan truyn. iu nay co th
lam anh hng ti inh thi hoat
ng cua h thng.

Xp tng cac 74138
A
B
C
E1
E2
E3
138
0
1
2
3
4
5
6
7

A
B
C
E1
E2
E3
138
0
1
2
3
4
5
6
7

A
B
C
E1
E2
E3
138
0
1
2
3
4
5
6
7

OUT A000
OUT A001
OUT A002
OUT A003
OUT A004
OUT A006
OUT A007
OUT A005
IN A000
IN A001
IN A002
IN A003
IN A004
IN A006
IN A007
IN A005
Logic
High
Logic
High
A13
A14
A15
SEL0
SEL1
SEL5
SEL7
Logic
High
MEMR
MEMW
A0
A1
A2
A0
A1
A2
Cac b giai ma hin ai
Giai ma trn cac mainboard may
tinh thng s dung cac chip giai
ma thng dung hoc cac PLD.
Cac b giai ma thng dung nh
74138.