ABSTRACT

A multiplier is one of the key hardware blocks in most

digital and high performance systems such as FIR filters,
digital signal processors and microprocessors etc. With
advances in technology, many researchers have tried and are
trying to design multipliers which offer either of the
following- high speed, low power consumption, regularity of
layout and hence less area or even combination of them is
multiplier. Thus making them suitable for various high speed,
low power and compact VLSI implementations. The shift and
add multiplier obtains product by shifting and adding
multiplicand to the product based upon the LSB of multiplier.
The shift-and-add multiplication method for two n-bit
numbers. The 2n-bit product register (A) is initialized to 0.
Since the basic algorithm shifts the multiplicand register (B)
left one position each step to align the multiplicand with the
sum being accumulated in the product register, we use a 2n-
bit multiplicand register with the multiplicand placed in the
right half of the register and with 0 in the left half. The
algorithm starts by loading the multiplicand into the B
register, loading the multiplier into the Q register, and
initializing the A register to 0. The counter N is initialized to
n. The least significant bit of the multiplier register (Q0)
determines whether the multiplicand is added to the product
register. The left shift of the multiplicand has the effect of
shifting the intermediate products to the left and LSB of
product is verified. Depending upon LSB value it is decided
whether to add and shift or just shift. This process is
continued to obtain product of the numbers.