Bioinstrumentation - John D. Enderle

P1: IML/FFX P2: IML/FFX QC: IML/FFX T1: IML
Morgan-FM MOBK036-Enderle.cls November 1, 2006 15:55

Bioinstrumentation
i
Copyright 2006 by Morgan & Claypool
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any meanselectronic, mechanical, photocopy, recording, or any other except for brief quotations
in printed reviews, without the prior permission of the publisher.
Bioinstrumentation
John D. Enderle
www.morganclaypool.com
ISBN-10: 1598291327 paperback
ISBN-13: 9781598291322 paperback
ISBN-10: 1598291335 ebook
ISBN-13: 9781598291339 ebook
DOI 10.2200/S00043ED1V01Y200608BME006
Library of Congress Cataloging-in-Publication Data
SYNTHESIS LECTURES ON BIOMEDICAL ENGINEERING
Lecture #6
Series Editor and Afliation: John D. Enderle, University of Connecticut
1930-0328 Print
1930-0336 Electronic
First Edition
10 9 8 7 6 5 4 3 2 1
Portions of this manuscript were reprinted from the following book with the Permission of Elsevier, INTRODUC-
TION TO BIOMEDICAL ENGINEERING, ISBN 0122386626 2005, Chapter 8, pp403-504, Enderle et al 2
nd
edition. This permission is granted for non-exclusive world English rights only in both print and on the world wide
web.
Additional Information regarding the bestselling book, Introduction to Biomedical Engineering, 2
nd
edition 2005, by
Enderle, Blanchard and Bronzino, from Elsevier can be found on the Elsevier Homepage http://www/elsevier.com.
ii
Bioinstrumentation
John D. Enderle
Program Director & Professor for Biomedical Engineering
University of Connecticut
SYNTHESIS LECTURES ON BIOMEDICAL ENGINEERING #6
M
&C
Morgan
&
Claypool Publishers
iii
ABSTRACT
This short book provides basic information about bioinstrumentation and electric circuit theory.
Many biomedical instruments use a transducer or sensor to convert a signal created by the body
into an electric signal. Our goal here is to develop expertise in electric circuit theory applied
to bioinstrumentation. We begin with a description of variables used in circuit theory, charge,
current, voltage, power and energy. Next, Kirchhoff s current and voltage laws are introduced,
followed by resistance, simplications of resistive circuits and voltage and current calculations.
Circuit analysis techniques are then presented, followed by inductance and capacitance, and
solutions of circuits using the differential equation method. Finally, the operational amplier
and time varying signals are introduced. This lecture is written for a student or researcher or
engineer who has completed the rst two years of an engineering program (i.e., 3 semesters of
calculus and differential equations). A considerable effort has been made to develop the theory
in a logical mannerdeveloping special mathematical skills as needed. At the end of the short
book is a wide selection of problems, ranging from simple to complex.
KEYWORDS
Bioinstrumentation, Circuit Theory, Introductory Biomedical Engineering, Sensors,
Transducers, Circuits, Voltage, Current
iv
v
Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Basic Bioinstrumentation System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Charge, Current, Voltage, Power and Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Kirchhoff s Current Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.1 Kirchhoff s Voltage Law. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Power and Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Equivalent Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Series and Parallel Combinations of Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1 Resistors in Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.2 Resistors in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 Voltage and Current Divider Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.5.1 Voltage Divider Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.5.2 Current Divider Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5. Linear Network Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Node-Voltage Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Mesh-Current Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3 Linearity, Superposition and Source Transformations . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.1 Linearity and Superposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.2 Equivalent Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6. Th evenins and Nortons Theorems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1 Th evenins Theorem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2 Nortons Theorem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
vi CONTENTS
6.3 Dependent Sources and Th evenin and Norton Equivalent Circuits . . . . . . . . . . . 59
7. Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.1 Power and Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8. Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.1 Power and Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9. Inductance and Capacitance Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10. General Approach to Solving Circuits Involving Resistors,
Capacitors and Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.1 Discontinuities and Initial Conditions in a Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.2 Circuits with Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11. Operational Ampliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.1 Voltage Characteristics of the Op Amp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12. Time-Varying Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.1 Phasors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.2 Passive Circuit Elements in the Phasor Domain. . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.3 Kirchhoff s Laws and Other Techniques in the Phasor Domain. . . . . . . . . . . . . 137
13. Active Analog Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
14. Bioinstrumentation Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
14.1 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
14.2 Computers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
13. Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
vii
Preface
This short book on bioinstrumentation is written for a reader who has completed the rst two
years of an engineering program (i.e., three semesters of calculus and differential equations).
A considerable effort has been made to develop the theory in a logical mannerdeveloping
special mathematical skills as needed.
I have found it best to introduce this material using simple examples followed by more
difcult ones.
At the end of the short book is a wide selection of problems, ranging from simple to
difcult, presented in the same general order as covered in the textbook.
I acknowledge and thank William Pruehsner for the technical illustrations. Portions of
this short book are from Chapter 8 of Enderle, J. D., Blanchard, S. M., and Bronzino, J. D.,
Introduction to Biomedical Engineering (Second Edition), Elsevier, Amsterdam, 2005, 1118 pages,
with Sections 1, 2 and 13 contributed by Susan Blanchard, Amanda Marley, and H. Troy Nagle.
viii
P1: KDD
MOBK036-01 MOBK036-Enderle.cls November 1, 2006 16:0
1
C H A P T E R 1
Introduction
This short book provides basic information about bioinstrumentation and electric circuit theory.
Many biomedical instruments use a transducer or sensor to convert a signal created by the body
into an electric signal. Our goal here is to develop expertise in electric circuit theory applied
to bioinstrumentation. We begin with a description of variables used in circuit theory, charge,
current, voltage, power, and energy. Next, Kirchhoff s current and voltage laws are introduced,
followed by resistance, simplications of resistive circuits and voltage and current calculations.
Circuit analysis techniques are then presented, followed by inductance and capacitance, and
solutions of circuits using the differential equation method. Finally, the operational amplier
and time-varying signals are introduced.
Before 1900, medicine had little to offer the typical citizen because its resources were
mainly the education and little black bag of the physician. The origins of the changes that
occurred within medical science are found in several developments that took place in the applied
sciences. During the early 19th century, diagnosis was based on physical examination, and
treatment was designed to heal the structural abnormality. By the late 19th century, diagnosis
was based on laboratory tests, and treatment was designed to remove the cause of the disorder.
The trend towards the use of technology accelerated throughout the 20th century. During
this period, hospitals became institutions of research and technology. Professionals in the areas
of chemistry, physics, mechanical engineering, and electrical engineering began to work in
conjunction with the medical eld, and biomedical engineering became a recognized profession.
As a result, medical technology advanced more in the 20th century than it had in the rest of
history combined (Fig. 1.1).
During this period, the area of electronics had a signicant impact on the development
of new medical technology. Men such as Richard Caton and Augustus Desire proved that
the human brain and heart depended upon bioelectric events. In 1903, William Einthoven
expanded on these ideas after he created the rst string galvanometer. Einthoven placed two
skin sensors on a man and attached them to the ends of a silvered wire that was suspended
through holes drilled in both ends of a large permanent magnet. The suspended silvered wire
moved rhythmically as the subjects heart beat. By projecting a tiny light beamacross the silvered
P1: KDD
2 BIOINSTRUMENTATION
1750
1800
1850
1900
1950
2000
1752 Ben Franklin flew his kite in the storm.
1774 John Walsh proved electricity
passes through humans.
1791 Galvani published his findings
on animal electricity.
1800 Volta built the first battery.
1820 Oersted discovered electromagnetism.
Ampere measured the magnetic effect
of an electric current.
1860 Maxwell worked out the mathematical
equations for the laws of
Electricity and magnetism.
1886 Hertz discovered the electromagnetic wave.
1897 Thomson discovered electrons.
1903 Einthoven discovered the galvanometer.
1909 Millikan measured the charge of the
electron.
1920s Television was invented.
1935 Amplifiers were used to record EEGs.
1948 Transistors become readily available.
1959 First transistor-based computer was made.
1972 First CAT machine was made.
First microprocessor was used.
1785 Coulomb worked out the laws
of attraction and repulsion between
electrically charged bodies.
1826 Ohm formulated law of
electrical resistance.
1831 Faraday and Henry found
that a moving magnet would induce
an electric current in a coil of wire.
1895 Roentgen discovered X-rays.
1904 Fleming invented the vacuum tube.
1929 Hans Berger recorded the first EEG.
1948 The first large scale
computer was built.
1960 Chardock and Greatbatch
created the first implantable pacemaker
1981 IBM introduced the
first personal computer
FIGURE 1.1: Timeline for major inventions and discoveries that led to modern medical instrumenta-
tion.
P1: KDD
INTRODUCTION 3
wire, Einthoven was able to record the movement of the wire as waves on a scroll of moving
photographic paper. Thus, the invention of the string galvanometer led to the creation of the
electrocardiogram (ECG), which is routinely used today to measure and record the electrical
activity of abnormal hearts and to compare those signals to normal ones.
In 1929, Hans Berger created the rst electroencephalogram (EEG), which is used to
measure and record electrical activity of the brain. In 1935, electrical ampliers were used to
prove that the electrical activity of the cortex had a specic rhythm, and, in 1960, electrical
ampliers were used in devices such as the rst implantable pacemaker that was created by
William Chardack and Wilson Greatbatch. These are just a small sample of the many examples
in which the eld of electronics has been used to signicantly advance medical technology.
Many other advancements that were made in medical technology originated from re-
search in basic and applied physics. In 1895, the X-ray machine, one of the most important
technological inventions in the medical eld, was created when W. K. Roentgen found that
X-rays could be used to give pictures of the internal structures of the body. Thus, the X-ray
machine was the rst imaging device to be created.
Another important addition to medical technology was provided by the invention of
the computer, which allowed much faster and more complicated analyses and functions to be
performed. One of the rst computer-based instruments in the eld of medicine, the sequential
multiple analyzer plus computer, was used to store a vast amount of data pertaining to clinical
laboratory information. The invention of the computer made it possible for laboratory tests to
be performed and analyzed faster and more accurately.
The rst large-scale computer-based medical instrument was created in 1972 when the
computerized axial tomography (CAT) machine was invented. The CAT machine created an
image that showed all of the internal structures that lie in a single plane of the body. This
new type of image made it possible to have more accurate and easier diagnosis of tumors,
hemorrhages, and other internal damage from information that was obtained noninvasively.
Telemedicine, which uses computer technology to transmit information fromone medical
site to another, is being explored to permit access to health care for patients in remote locations.
Telemedicine can be used to let a specialist in a major hospital receive information on a patient
in a rural area and send back a plan of treatment specic for that patient.
Today, there is a wide variety of medical devices and instrumentation systems. Some are
used to monitor patient conditions or acquire information for diagnostic purposes, e.g. ECG
and EEG machines, while others are used to control physiological functions, e.g. pacemakers
and ventilators. Some devices, like pacemakers, are implantable while many others are used
noninvasively. This chapter will focus on those features that are common to devices that are
used to acquire and process physiological data.
P1: KDD
4
P1: KDD
5
C H A P T E R 2
Basic Bioinstrumentation System
The quantity, property, or condition that is measured by an instrumentation system is called the
measurand (Fig. 2.1). This can be a bioelectric signal, such as those generated by muscles or the
brain, or a chemical or mechanical signal that is converted to an electrical signal. Sensors are
used to convert physical measurands into electric outputs. The outputs from these biosensors
are analog signals, i.e. continuous signals, which are sent to the analog processing and digital
conversion block. There, the signals are amplied, ltered, conditioned, and converted to digital
form. Methods for modifying analog signals, such as amplifying and ltering an ECG signal,
are discussed later in this chapter. Once the analog signals have been digitized and converted
to a form that can be stored and processed by digital computers, many more methods of signal
conditioning can be applied.
Basic instrumentation systems also include output display devices that enable human
operators to view the signal in a format that is easy to understand. These displays may be
numerical or graphical, discrete or continuous, and permanent or temporary. Most output
display devices are intended to be observed visually, but some also provide audible output, e.g.
a beeping sound with each heart beat.
Inadditionto displaying data, many instrumentationsystems have the capability of storing
data. In some devices, the signal is stored briey so that further processing can take place or so
that an operator can examine the data. In other cases, the signals are stored permanently so that
different signal processing schemes can be applied at a later time. Holter monitors, for example,
acquire 24 hrs of ECG data that is later processed to determine arrhythmic activity and other
important diagnostic characteristics.
With the invention of the telephone and now with the Internet, signals can be ac-
quired with a device in one location, perhaps in a patients home, and transmitted to an-
other device for processing and/or storage. This has made it possible, for example, to pro-
vide quick diagnostic feedback if a patient has an unusual heart rhythm while at home. It
has also allowed medical facilities in rural areas to transmit diagnostic images to tertiary care
hospitals so that specialized physicians can help general practitioners arrive at more accurate
diagnoses.
P1: KDD
Sensor Calibration
A/D
Analog
Processing
Signal
Processing
Data
Storage
Control &
Feedback
Output
Display
Data
Transmission
FIGURE 2.1: Basic instrumentation systems using sensors to measure a signal with data acquisition,
storage and display capabilities, along with control and feedback.
Two other components play important roles in instrumentation systems. The rst is the
calibration signal. A signal with known amplitude and frequency content is applied to the
instrumentation system at the sensors input. The calibration signal allows the components of
the system to be adjusted so that the output and input have a known, measured relationship.
Without this information, it is impossible to convert the output of an instrument system into
a meaningful representation of the measurand.
Another important component, a feedback element, is not a part of all instrumentation
systems. These devices include pacemakers and ventilators that stimulate the heart or the lungs.
Some feedback devices collect physiological data and stimulate a response, e.g. a heart beat or
breath, when needed or are part of biofeedback systems in which the patient is made aware
of a physiological measurement, e.g. blood pressure, and uses conscious control to change the
physiological response.
P1: KDD
7
C H A P T E R 3
Charge, Current, Voltage,
Power and Energy
3.1 CHARGE
Two kinds of charge, positive and negative, are carried by protons and electrons, respectively.
The negative charge carried by an electron, q
e
, is the smallest amount of charge that exists and
is measured in units called Coulombs (C).
q
e
= 1.602 10
19
C
The symbol q(t) is used to represent charge that changes with time, and Q for constant charge.
The charge carried by a proton is the opposite of the electron.
Example 3.1. What is the charge of 3 10
15
g of electrons?
Solution
Q = 3 10
15
g
1 kg
10
3
g

1 electron
9.1095 10
31
kg

1.60219 10
19
C
electron
= 5.27643 10
7
C
3.2 CURRENT
Electric current, i (t), is dened as the change in the amount of charge that passes through a
given point or area in a specied time period. Current is measured in amperes (A). By denition,
one ampere equals one coulomb/second (C/s).
i (t) =
dq
dt
(3.1)
and
q(t) =
t
t
0
i () d +q(t
0
) (3.2)
P1: KDD
Circuit
element
Circuit
element
i
i
FIGURE3.1: A simple electric circuit illustrating current owing around a closed loop.
Current, dened by Eq. (3.1), also depends on the direction of ow as illustrated in the circuit
in Fig. 3.1.
Example 3.2. Suppose the following current is owing in Fig. 3.1.
i (t) =
0 t < 0
3e
100t
A t 0
Find the total charge.
Solution
Q =
idt =
0
3e
100t
dt =
3
100
e
100t
t=0
= 0.03 C
Consider Fig. 3.1. Current is dened as positive if
(a) A positive charge is moving in the direction of the arrow
(b) A negative charge is moving in the opposite direction of the arrow
Since these two possibilities produce the same outcome, there is no need to be concerned as to
which is responsible for the current. In electric circuits, current is carried by electrons in metallic
conductors.
Current is typically a function of time, as given by Eq. (3.1). Consider Fig. 3.2 with the
current entering terminal 1 in the circuit on the right. In the time interval 01.5 s, current is
positive and enters terminal 1. In the time interval 1.53 s, the current is negative and enters
terminal 2 with a positive value. We typically refer to a constant current as a DC current, and
P1: KDD
CHARGE, CURRENT, VOLTAGE, POWERANDENERGY 9
-1.5
-1
-0.5
0
0.5
1
1.5
-1 -0.5 0 0.5 1 1.5 2 2.5 3
t
(s)
i
(A)
Circuit
element
i
1
2
i
FIGURE 3.2: (Left) A sample current waveform. (Right) A circuit element with current entering
terminal 1 and leaving terminal 2. Passive circuit elements have two terminals with a known voltage
current relationship. Examples of passive circuit elements include resistors, capacitors and inductors.
denote it with a capital letter such as I indicating it does not change with time. We denote a
time-varying current with a lower case letter, such as i (t),or just i .
3.2.1 Kirchhoff s Current Law
Current can ow only in a closed circuit, as shown in Fig. 3.1. No current is lost as it ows
around the circuit because net charge cannot accumulate within a circuit element and charge
must be conserved. Whatever current enters one terminal must leave at the other terminal.
Since charge cannot be created and must be conserved, the sum of the currents at any node,
that is, a point at which two or more circuit elements have a common connection, must equal
zero so no net charge accumulates. This principle is known as Kirchhoff s current law (KCL),
given as
N
n=1
i
n
(t) = 0 (3.3)
where there are N currents leaving the node. Consider the circuit in Fig. 3.3. Using Eq. (3.3)
and applying KCL for the currents leaving the node gives
i
1
i
2
+i
4
+i
3
= 0
The previous equation is equivalently written for the currents entering the node, as
i
1
+i
2
i
4
i
3
= 0
P1: KDD
i
1 i
2
i
3
i
4
FIGURE3.3: A node with 4 currents.
It should be clear that the application of KCL is for all currents, whether they are all leaving or
all entering the node.
In describing a circuit, we dene its characteristics with the terms node, branch, path,
closed path and mesh as follows.
Node: A point at which two or more circuit elements have a common connection.
Branch: A circuit element or connected group of circuit elements. A connected group
of circuit elements usually connect nodes together.
Path: A connected group of circuit elements in which none is repeated.
Closed Path: A path that starts and ends at the same node.
Mesh: A closed path that does not contain any other closed paths within it.
Essential Node: A point at which three or more circuit elements have a common con-
nection.
Essential Branch: A branch that connects two essential nodes.
InFig. 3.4, there are ve nodes, A, B, C, DandE, whichare all essential nodes. Kirchhoff s
current law is applied to each of the nodes as follows.
Node A: i
1
+i
2
i
3
= 0
Node B: i
3
+i
4
+i
5
i
6
= 0
Node C: i
1
i
4
i
8
= 0
Node D: i
7
i
5
+i
8
= 0
Node E: i
2
+i
6
+i
7
= 0
Kirchhoff s current law is also applicable to any closed surface surrounding a part of the circuit.
It is understood that the closed surface does not intersect any of the circuit elements. Consider
the closed surface drawn with dashed lines in Fig. 3.4. Kirchhoff s current law applied to the
closed surface gives
i
1
+i
4
+i
5
+i
7
= 0
P1: KDD
Circuit
element
Circuit
element
i
1
Circuit
element
Circuit
element
Circuit
element
Circuit
element
Circuit
element
A
B
C
D
E
i
2
i
3
i
4
i
5
i
6
i
7
i
8
Closed surface
FIGURE3.4: A circuit with a closed surface.
3.3 VOLTAGE
Voltage represents the work per unit charge associated with moving a charge between two points
(A and B in Fig. 3.5), and given as
v =
dw
dq
(3.4)
The unit of measurement for voltage is the volt (V). A constant (DC) voltage source is denoted
by V while a time-varying voltage is denoted by v(t), or just v. In Fig. 3.5, the voltage, v,
between two points (A and B), is the amount of energy required to move a charge from point
A to point B.
Circuit
element
i
1
2
B
A
+
v
-
FIGURE3.5: Voltage and current convention.
P1: KDD
Circuit
element
Circuit
element
Circuit
element
Circuit
element
Circuit
element
+
v
3
-
-
v
4
+
+
v
5
-
+ v
1
- + v
2
-
CP1 CP2
CP3
FIGURE 3.6: Circuit illustrating Kirchhoff s voltage law. Closed paths are identied as CP1, CP2
and CP3.
3.3.1 Kirchhoff s Voltage Law
Kirchhoff s voltage law (KVL) states the sum of all voltages in a closed path is zero, or
N
n=1
v
n
(t) = 0 (3.5)
where there are N voltage drops assigned around the closed path, with v
n
(t) denoting the
individual voltage drops. The sign for each voltage drop in Eq. (3.5) is the rst sign encountered
while moving around the closed path.
Consider the circuit in Fig. 3.6, with each circuit element assigned a voltage, v
n
, with a
given polarity, and three closed paths, CP1, CP2 and CP3. Kirchhoff s voltage law for each
closed path is given as
CP1: v
3
+v
1
v
4
= 0
CP2: v
4
+v
2
+v
5
= 0
CP3: v
3
+v
1
+v
2
+v
5
= 0
Kirchhoff s laws are applied in electric circuit analysis to determine unknown voltages and
currents. Each unknown variable has its distinct equation. To solve for the unknowns using
MATLAB, we create a matrix representation of the set of equations and solve. This method is
demonstrated in many examples in this book.
P1: KDD
Example 3.3. Find I
1
, I
2
and I
3
for the following circuit.
Circuit
Element
Circuit
Element
I1
Circuit
Element
Circuit
Element
Circuit
Element
Circuit
Element
A
B
C
I
2
I
3
2A
3A 4A
Solution. We apply KCL rst at node C, then B and nally A.
Node C: 2 + I
3
+4 = 0; I
3
= 2 A
Node B: I
2
+3 I
3
= 0; I
2
= I
3
3 = 5 A
Node A: I
1
I
2
+2 = 0; I
1
= 2 I
2
= 7 A
3.4 POWERANDENERGY
Power is the rate of energy expenditure given as
p =
dw
dt
=
dw
dq
dq
dt
= vi (3.6)
where p is power measured in watts (W), and w is energy measured in joules ( J). Power is
usually determined by the product of voltage across a circuit element and the current through it.
By convention, we assume that a positive value for power indicates that power is being delivered
(or absorbed or consumed) by the circuit element. A negative value for power indicates that
power is being extracted or generated by the circuit element, i.e., a battery.
Figure 3.7 illustrates the four possible cases for a circuit elements current and voltage
conguration. According to convention, if both i and v are positive, with the arrow and polarity
shown in Fig. 3.7A, energy is absorbed (either lost by heat or stored). If either the current arrow
or voltage polarity is reversed as in B and C, energy is supplied to the circuit. Note that if both
the current direction and voltage polarity are reversed together, as in D, energy is absorbed.
P1: KDD
Circuit
element
i
1
2
+
v
-
p vi =
Circuit
element
i
1
2
+
v
-
p = vi
Circuit
element
i
1
2
-
v
+
p = vi
Circuit
element
i
1
2
-
v
+
p = vi
A B
C D
FIGURE3.7: Polarity references for four cases of current and voltage. Cases A and D result in positive
power being consumed by the circuit element. Cases B and C result in negative power being extracted
from the circuit element.
A passive circuit element is dened as an element whose power is always positive or zero,
which may be dissipated as heat (resistance), stored in an electric eld (capacitor) or stored in
a magnetic eld (inductor). We dene an active circuit element as one whose power is negative
and capable of generating energy.
Energy is given by
w(t) =
t
pdt (3.7)
3.5 SOURCES
Sources are two terminal devices that provide energy to a circuit. There is no direct voltage
current relationship for a source; when one of the two variables is given, the other cannot be
determined without knowledge of the rest of the circuit. Independent sources are devices for
which the voltage or current is given and the device maintains its value regardless of the rest of
the circuit. A device that generates a prescribed voltage at its terminals, regardless of the current
ow, is called an ideal voltage source. Figure 3.8A and B shows the general symbols for an ideal
voltage source. Figure 3.8C shows an ideal current source that delivers a prescribed current to
P1: KDD
V
S
+
-
V
S
I
S
A B C
FIGURE3.8: Basic symbols used for independent sources. (A) Battery. (B) Ideal voltage source. V
s
can
be a constant DC source (Battery) or a time-varying source. (C) Ideal current source I
s
.
V
S
I
S
+
-
FIGURE3.9: Basic symbols used for dependent or controlled sources. (Left) Controlled voltage source.
The voltage V
s
is a known function of some other voltage or current in the circuit. (Right) Controlled
current source. The current I
s
is a known function of some other voltage or current in the circuit.
the attached circuit. The voltage generated by an ideal current source depends on the elements
in the rest of the circuit.
Shown in Fig. 3.9 are a dependent voltage and current source. A dependent source takes
on a value equaling a known function of some other voltage or current value in the circuit. We
use a diamond-shaped symbol to represent a dependent source. Often, a dependent source is
called a controlled source. The current generated for a dependent voltage source and the voltage
for a dependent current source depend on circuit elements in the rest of the circuit. Dependent
sources are very important in electronics. Later in this chapter, we will see that the operational
amplier uses a controlled voltage source for its operation.
Example 3.4. Find the voltage V
3
for the circuit shown in the following gure.
10V
5A
-
+
I2
+
-
5V
3A
2I
2
-
+
+
V
3
-
P1: KDD
Solution. Current I
2
equals 5 A because it is in the same branch as the 5 A current source. The
voltage across the dependent voltage source on the right side of the circuit equals 2I
2
= 10 V.
Applying KVL around the outer closed path gives
V
3
5 10 = 0
or
V
3
= 15 V
P1: KDD
17
C H A P T E R 4
Resistance
4.1 RESISTORS
A resistor is a circuit element that limits the ow of current through it and is denoted with
the symbol . Resistors are made of different materials and their ability to impede current
is given with a value of resistance, denoted R. Resistance is measured in Ohms (), where
1 = 1 V/A. A theoretical bare wire that connects circuit elements together has a resistance of
zero. A gap between circuit elements has a resistance of innity. An ideal resistor follows Ohms
law, which describes a linear relationship between voltage and current, as shown in Fig. 4.1,
with a slope equal to the resistance.
There are two ways to write Ohms law, depending on the current direction and voltage
polarity. Ohms law is written for Fig. 4.2A as
v = i R (4.1)
and for Fig. 4.2B as
v = i R (4.2)
In this book, we will use the convention shown in Fig. 4.2A to write the voltage drop across a
resistor. As described, the voltage across a resistor is equal to the product of the current owing
through the element and its resistance, R. This linear relationship does not apply at very high
voltages and currents. Some electrically conducting materials have a very small range of currents
and voltages in which they exhibit linear behavior. This is true of many physiological models
as well: linearity is observed only within a range of values. Outside this range, the model is
nonlinear. We dene a short circuit as shown in Fig. 4.3A with R = 0, and having a 0 V voltage
drop. We dene an open circuit as shown in Fig. 4.3B with R = , and having 0 A current
pass through it.
Each material has a property called resistivity () that indicates the resistance of the
material. Conductivity () is the inverse of resistivity, and conductance (G) is the inverse of
P1: KDD
I
(A)
V
(V)
Slope = R
FIGURE4.1: Voltagecurrent relationship for a resistor.
A
i(t)
R
+
v(t)
B
i(t)
R
+
v(t)
FIGURE4.2: An ideal resister with resistance R in Ohms ().

i
+
v = 0 V
0 R=
A. Short Circuit
+
v
R=
B. Open Circuit
i = 0 A
FIGURE4.3: Short and open circuits.
P1: KDD
RESISTANCE 19
resistance. Conductance is measured in units called siemens (S) and has units of A/V. In terms
of conductance, Ohms law is written as
i = Gv (4.3)
Example 4.1. From the following circuit, nd I
2
, I
3
and V
1
.
R2
R1 5
5
5A
50 V
I3
I2
+
V1
8 A
10 A
Solution. First we nd I
2
by applying KCL at the node in the upper left of the circuit.
5 + I
2
+8 = 0
and
I
2
= 3 A
Current I
3
is determined by applying KCL at the node on the right of the circuit.
10 + I
3
8 = 0
and
I
3
= 2 A
Voltage V
1
is determined by applying KVL around the lower right closed path and using
Ohms law.
V
1
50 +5I
3
= 0
V
1
= 50 +5 (2) = 60 V
4.2 POWER
The power consumed by a resistor is given by the combination of Eq. (3.6) and either Eq. (4.1)
or (4.2) as
p = vi =
v
2
R
= i
2
R (4.4)
P1: KDD
and given off as heat. Equation (4.4) demonstrates that regardless of the voltage polarity and
current direction, power is consumed by a resistor. Power is always positive for a resistor, which
is true for any passive element.
Example 4.2. Calculate the power in each element.
18 V 5I
1 3
I
1
Solution. We rst note that the resistor on the right has 18 V across it, and therefore the
current through it, according to Ohms law, is
18
3
= 6 A. To nd the current I
1
we apply KCL
at the upper node, giving
I
1
5I
1
+6 = 0
or
I
1
= 1 A
The power for each of the circuit elements is
p
18V
= I
1
18 = 18 W
p
5i
1
= 18 5I
1
= 90 W
p
3
=
18
2
3
= 108 W
In any circuit, the power supplied by the active elements always equals the power consumed.
Here, the power generated is 108 W and the power consumed is 108 W, as required.
Example 4.3. Electric safety is of paramount importance in a hospital or clinical environment.
If sufcient current is allowed to ow through the body, signicant damage can occur, as
illustrated in the following gure.
P1: KDD
RESISTANCE 21
0.0001 0.001 0.01 0.1 1.0 10.0 100.0
Current (A)
Threshold of
perception
Let-go
current
Respiratory paralysis, Fatigue, Pain
Ventricular fibrillation
Sustained myocardial
contraction
Burns, Injury
For instance, a current of magnitude 50 mA (dashed line) is enough to cause ventricular bril-
lation, as well as other conditions. The gure on the left shows the current distribution from a
macroshock from one arm to another (Redrawn from Enderle et al., Introduction to Biomedical
Engineering, 2000). Acrude electric circuit model of the body consisting of two arms (each with
resistance R
A
), two legs (each with resistance R
L
), body trunk (with resistance R
T
), and head
(with resistance R
H
) is shown in the following gure on the right.
+
-
VS
RT
RH
RA
RA
RL RL
P1: KDD
Since the only elements that form a closed path that current can ow is given by the source in
series with the two arms, we reduce the body electric circuits to
RA
RA VS
I
If R
A
= 400 and V
s
= 120 V, then nd I.
Solution. Using Ohms law, we have
I =
V
s
R
A
+ R
A
=
120
800
= 0.15 A
The current I is the current passing through the heart, and at this level it would cause ventricular
brillation.
4.3 EQUIVALENTRESISTANCE
It is sometimes possible to reduce complex circuits into simpler and, as we will see, equivalent
circuits. We consider two circuits equivalent if they cannot be distinguished from each other by
voltage and current measurements, that is, the two circuits behave identically. Consider the two
circuits A and B in Fig. 4.4, consisting of combinations of resistors, each stimulated by a DC
voltage V
s
. These two circuits are equivalent if I
A
= I
B
. We represent the resistance of either
circuit using Ohms law as
R
EQ
=
V
s
I
A
=
V
s
I
B
(4.5)
Thus, it follows that any circuit consisting of resistances can be replaced by an equivalent circuit
as shown in Fig. 4.5. In another section on a Th evenin equivalent circuit, we will expand this
remark to include any combination of sources and resistances.
P1: KDD
RESISTANCE 23
Circuit
A
VS
I
A
Circuit
B
VS
I
B
FIGURE4.4: Two circuits.
4.4 SERIES ANDPARALLEL COMBINATIONS OF RESISTANCE
4.4.1 Resistors in Series
If the same current ows from one resistor to another, the two are said to be in series. If these
two resistors are connected to a third and the same current ows through all of them, then the
three resistors are in series. In general, if the same current ows through N resistors, then the
N resistors are in series. Consider Fig. 4.6 with three resistors in series. An equivalent circuit
can be derived through KVL as
V
s
+IR
1
+IR
2
+IR
3
= 0
or rewritten in terms of an equivalent resistance R
EQ
as
R
EQ
=
V
s
I
= R
1
+ R
2
+ R
3
Circuit
A
VS
IA
VS
IA
REQ
FIGURE4.5: Equivalent circuits.
P1: KDD
R1
R2
R3
VS
I
FIGURE4.6: A series circuit.
In general, if we have N resistors in series,
R
EQ
=
N
i =1
R
i
(4.6)
4.4.2 Resistors in Parallel
Two or more elements are said to be in parallel if the same voltage is across each of the resistors.
Consider the three parallel resistors as shown in Fig. 4.7. We use a shorthand notation to
represent resistors in parallel using the symbol. Thus in Fig. 4.7, R
EQ
= R
1
R
2
R
3
. An
equivalent circuit for Fig. 4.7 is derived through KCL as
I +
V
s
R
1
+
V
s
R
2
+
V
s
R
3
= 0
V
S
R
3
R
2
R
1
I
FIGURE4.7: A parallel circuit.
P1: KDD
RESISTANCE 25
or rewritten in terms of an equivalent resistance R
EQ
as
R
EQ
=
V
s
I
=
1
1
R
1
+
1
R
2
+
1
R
3
In general, if we have N resistors in parallel,
R
EQ
=
1
1
R
1
+
1
R
2
+ +
1
R
N
(4.7)
For just two resistors in parallel, Eq. (4.7) is written as
R
EQ
= R
1
R
2
=
R
1
R
2
R
1
+ R
2
(4.8)
Example 4.4. Find R
EQ
and the power supplied by the source for the following circuit.
2
5 V 12 12 12
3
2 2
I
Solution. To solve for R
EQ
, apply from right to left the parallel and series combinations. First,
we have two 2 resistors in parallel that are in series with the 3 resistor. Next, this group
is in parallel with the three 12 resistors. Finally, this group is in series with the 2 resistor.
These combinations are shown in the following gure and calculation:
2
5 V 12 12 12
3
2 2
I
22 =1
3+1=4 121212 =4
44=2
2+2 =4
P1: KDD
R
EQ
= 2 +((12 12 12 ) (3 +(2 2 )))
= 2 +
1
1
12
+
1
12
+
1
12
3 +
1
1
2
+
1
2
= 2 +((4) (3 +1)) = 2 +2 = 4
Accordingly,
I =
5
R
EQ
=
5
4
= 1.25 A
and
p = 5 I = 6.25 W
4.5 VOLTAGEANDCURRENTDIVIDERRULES
Let us nowextend the concept of equivalent resistance, R
EQ
=
V
I
, to allowus to quickly calculate
voltages in series resistor circuits and currents in parallel resistor circuits without digressing to
the fundamentals.
4.5.1 Voltage Divider Rule
The voltage divider rule allows us to easily calculate the voltage across a given resistor in a series
circuit. Consider nding V
2
in the series circuit shown in Fig. 4.8, where R
EQ
= R
1
+ R
2
.
Accordingly,
I =
V
s
R
EQ
=
V
s
R
1
+ R
2
R1
R2 VS
I
+
V2
FIGURE4.8: Voltage divider rule circuit.

P1: KDD
RESISTANCE 27
V
S
R
2
R
1
I
I
1
I
2
FIGURE4.9: Current divider rule circuit.
and therefore
V
2
= IR
2
= V
s
R
2
R
1
+ R
2
This same analysis can be used to nd V
1
as
V
1
= V
s
R
1
R
1
+ R
2
In general, if a circuit contains N resistors in series, the voltage divider rule gives the voltage
across any one of the resistors, R
i
, as
V
i
= V
s
R
i
R
1
+ R
2
+ R
N
(4.9)
4.5.2 Current Divider Rule
The current divider rule allows us to easily calculate the current through any resistor in parallel
resistor circuits. Consider nding I
2
inthe parallel circuit showninFig. 4.9, where R
EQ
=
R
1
R
2
R
1
+R
2
.
Accordingly,
I
2
=
V
s
R
2
and
V
s
= I
R
1
R
2
R
1
+ R
2
P1: KDD
yielding after substituting V
s
I
2
= I
1
R
2
1
R
1
+
1
R
2
In general, if a circuit contains N resistors in parallel, the current divider rule gives the current
through any one of the resistors, R
i
, as
I
i
= I
1
R
i
1
R
1
+
1
R
2
+
1
R
N
(4.10)
Example 4.5. For the following circuit, nd I
1
.
5 A 10/3 2
1
12 12 12
I
1
Solution. We solve this circuit problem in two parts, as is evident from the redrawn circuit
that follows, by rst nding I
2
and then I
1
.
5 A 10/3 2
1
12
REQ
12 12
I1
I2
To begin, rst nd R
EQ
, which, when placed into the circuit, reduces to three parallel resistors
from which I
2
is calculated. The equivalent resistance is found as
R
EQ
= 1 +(12 12 12) = 1 +
1
1
12
+
1
12
+
1
12
= 5
P1: KDD
RESISTANCE 29
Applying the current divider rule on the three parallel resistors,
10
3
2 R
EQ
, we have
I
2
= 5
1
5
3
10
+
1
2
+
1
5
= 1 A
I
2
ows through the 1 resistor, and then divides into three equal currents of
1
3
A through each
12 resistor. The current I
1
can also be found by applying the current divider rule as
I
1
= I
2
1
12
1
12
+
1
12
+
1
12
=
1
12
1
12
+
1
12
+
1
12
=
1
3
A
P1: KDD
30
P1: KDD
31
C H A P T E R 5
Linear Network Analysis
Our methods for solving circuit problems up to this point have included applying Ohms law
and Kirchhoff s laws, resistive circuit simplication, and the voltage and current divider rules.
This approach works for all circuit problems, but as the circuit complexity increases, it becomes
more difcult to solve problems. In this section, we introduce the node-voltage method and
the mesh-current method to provide a systematic and easy solution of circuit problems. The
application of the node-voltage method involves expressing the branch currents in terms of
one or more node voltages, and applying KCL at each of the nodes. The application of the
mesh-current method involves expressing the branch voltages in terms of mesh currents, and
applying KVL around each mesh. These two methods are systematic approaches that lead to a
solution that is efcient and robust, resulting in a minimum number of simultaneous equations
that saves time and effort.
In both cases, the resulting linear set of simultaneous equations is solved to determine the
unknown voltages or currents. The number of unknown voltages for the node-voltage method
or currents for the mesh-current method determines the number of equations. The number of
independent equations necessitates:
N-1 equations involving KCLat N-1 nodes for the node-voltage method. This number
may be fewer if there are voltage sources in the circuit.
N-1 equations involving KVL around each of the meshes in the circuit for the
mesh-current method. This number may be fewer if there are current sources in the
circuit.
As we will see, MATLAB is ideal for solving problems that involves solution of simulta-
neous equations, providing a straightforward tool that minimizes the amount of work.
5.1 NODE-VOLTAGEMETHOD
The use of node equations provides a systematic method for solving circuit analysis problems by
the application of KCL at each essential node. The node-voltage method involves the following
two steps:
P1: KDD
R
+
V1
+
V2
+ V
IA
(A)
R
+
V1
+
V2
V +
(B)
IB
FIGURE5.1: Ohms law written in terms of node voltages.
1. Assign each node a voltage with respect to a reference node (ground). The reference
node is usually the one with the most branches connected to it, and is denoted with the
symbol . All voltages are written with respect to the reference node.
2. Except for the reference node, we write KCL at each of the N-1 nodes.
The current through a resistor is written using Ohms law, with the voltage expressed as
the difference between the potential on either end of the resistor with respect to the reference
node as shown in Fig. 5.1. We express node-voltage equations as the currents leaving the node.
Two adjacent nodes give rise to the current moving to the right (like Fig. 5.1A) for one node, and
the current moving to the left (like Fig. 5.1B) for the other node. The current is written for (A)
as I
A
=
V
R
=
V
1
V
2
R
and for (B) as I
B
=
V
R
=
V
2
V
1
R
. It is easy to verify in (A) that V = V
1
V
2
by applying KVL.
If one of the branches located between an essential node and the reference node contains
an independent or dependent voltage source, we do not write a node equation for this node,
because the node voltage is known. This reduces the number of independent node equations
by one and the amount of work in solving for the node voltages. In writing the node equations
for the other nodes, we write the value of the independent voltage source in those equations.
Consider Fig. 5.1 (A) and assume the voltage V
2
results from an independent voltage source
of 5 V. Since the node voltage is known, we do not write a node voltage equation for node 2
in this case. When writing the node-voltage equation for node 1, the current I
A
is written as
I
A
=
V
1
5
R
. Ex. 5.1 further illustrates this case.
Example 5.1. Find V
1
using the node-voltage method.
1/2 1/2
1/3 1/4 5 V 3 A
+
V
1
P1: KDD
LINEARNETWORKANALYSIS 33
Solution. This circuit has two essential nodes, labeled 1 and 2 in the redrawn circuit that follows,
with the reference node and two node voltages, V
1
and V
2
, indicated. The node involving the 5 V
voltage source has a known node voltage and therefore we do not write a node equation for it.
1/2 1/2
1/3 1/4 5 V 3 A
+
V
1
+
V
2
1 2
Summing the currents leaving node 1 gives
2(V
1
5) +3V
1
+2(V
1
V
2
) = 0
which simplies to
7V
1
2V
2
= 10
2(V
2
V
1
) +4V
2
+3 = 0
which simplies to
2V
1
+6V
2
= 3
The two node equations are written in matrix format as
7 2
2 6
V
1
V
2
10
3
and solved with MATLAB as follows:

A = [7 2; 2 6];
F = [10; 3];
V = A\F
V =
1.4211
0.0263
Thus, V
1
= 1.4211 V.
P1: KDD
Generally, the coefcient for the node voltage is the sumof the conductances connected to
the node. The coefcients for the other node voltages are the negative of the sumof conductances
connected between the node voltage and other node voltages. If the input consists of a set of
current sources applied at each node, then the node equations have the following form.
G
1,1
V
1
G
1,2
V
2
G
1,N1
V
N1
= I
1
G
2,1
V
1
+ G
2,2
V
2
G
2,N1
V
N1
= I
2
.
.
.
G
N1,1
V
1
G
N1,2
V
2
G
N1,N1
V
N1
= I
N
(5.1)
Equation (5.1) is put in matrix form for solution by MATLAB as
G
1,1
G
2,1
G
1,N1
G
2,1
G
2,2
G
2,N1
.
.
.
G
N1,1
G
N1,2
G
N1,N1
V
1
V
2
.
.
.
V
N1
I
1
I
2
.
.
.
I
N1
(5.2)
Note the symmetry about the main diagonal where the off-diagonal terms are equal to each
other and negative. This is true of all circuits without dependent sources. A dependent source
destroys this symmetry. In general, if a circuit has dependent sources, the node-voltage approach
is the same as before except for an additional equation describing the relationship between the
dependent source and the node voltage. In cases involving more than one dependent source,
there is one equation for each dependent source in terms of the node voltages.
Example 5.2. For the following circuit, nd V
3
using the node-voltage method.
1/2
5 A 1/3
1/4
3 A 1
1/4
2Id
I
d
+
V3
P1: KDD
Solution. Notice that this circuit has three essential nodes and a dependent current source.
We label the essential nodes 1, 2 and 3 in the redrawn circuit, with the reference node at the
bottom of the circuit and three node voltages V
1
, V
2
and V
3
, as indicated.
1/2
5 A 1/3
1/4
3 A 1
1/4
2I
d
Id
+
V
3
+
V
2
+
V
1
1
2 3
Note that I
d
= V
3
according to Ohms law. Summing the currents leaving node 1 gives
5 +2 (V
1
V
2
) +2I
d
+4 (V
1
V
3
) = 0
which reduces to
6V
1
2V
2
2V
3
= 5
2I
d
+2 (V
2
V
1
) +3V
2
+4 (V
2
V
3
) = 0
which simplies to
2V
1
+9V
2
6V
3
= 0
4 (V
3
V
2
) 3 + V
3
+4 (V
3
V
1
) = 0
reducing to
4V
1
4V
2
+9V
3
= 3
P1: KDD
The three node equations are written in matrix format as
6 2 2
2 9 6
4 4 9
V
1
V
2
V
3
5
0
3
Notice that the systemmatrix is no longer symmetrical because of the dependent current source,
and two of the three nodes have a current source giving rise to a nonzero termon the right-hand
side of the matrix equation.
Solving with MATLAB gives
A = [6 2 2; 2 9 6; 4 4 9];
F = [5; 0; 3];
V = A\F
V =
1.1471
0.5294
0.4118
Thus V
3
= 0.4118 V.
If one of the branches has an independent or controlled voltage source located between
two essential nodes as shown in Fig. 5.2, the current through the source is not easily expressed
in terms of node voltages. In this situation, we form a supernode by combining the two nodes.
The supernode technique requires only one node equation in which the current, I
A
, is passed
through the source and written in terms of currents leaving node 2. Specically, we replace
I
A
with I
B
+ I
C
+ I
D
in terms of node voltages. Because we have two unknowns and one
supernode equation, we write a second equation by applying KVL for the two node voltages 1
+
V1
+
V2
1
2
IA IC
ID
IB
FIGURE5.2: A dependent voltage source is located between nodes 1 and 2.
P1: KDD
and 2 and the source as
V
1
V
+ V
2
= 0
or
V
= V
1
V
2
Example 5.3. For the following circuit, nd V
3
.
2 A 1/2
1/4
1/3 1 A
1 V
1/2
1/5
+
V3
Solution. The circuit has three essential nodes, two of which are connected to an independent
voltage source and form a supernode. We label the essential nodes as 1, 2 and 3 in the redrawn
circuit, with the reference node at the bottom of the circuit and three node voltages, V
1
, V
2
and
V
3
as indicated.
2 A 1/2
1/4
1/3 1 A
1 V
1/2
1/5
+
V3
1 2 3
+
V2
+
V1
P1: KDD
2 +2V
1
+5 (V
1
V
3
) +4 (V
1
V
2
) = 0
Simplifying gives
11V
1
4V
2
5V
3
= 2
Nodes 2 and 3 are connected by an independent voltage source, so we form a supernode 2 +3.
Summing the currents leaving the supernode 2 +3 gives
4 (V
2
V
1
) +3V
2
1 +2V
3
+5 (V
3
V
1
) = 0
Simplifying yields
9V
1
+7V
2
+7V
3
= 1
The second supernode equation is KVL through the node voltages and the independent source,
giving
V
2
+1 + V
3
= 0
or
V
2
+ V
3
= 1
The two node and KVL equations are written in matrix format as
11 4 5
9 7 7
0 1 1
V
1
V
2
V
3
2
1
1
Solving with MATLAB gives

A = [11 4 5; 9 7 7; 0 1 1];
F = [2; 1; 1];
V = A\F
V =
0.4110
0.8356
0.1644
Thus V
3
= 0.1644.
P1: KDD
5.2 MESH-CURRENTMETHOD
Another method for analyzing planar circuits is called the mesh-current method. A mesh is a
closed path without any other closed paths within it and a planar circuit is a circuit without any
overlapping branches. All of our problems in this book involve planar circuits. The mesh-current
method provides a systematic process for solving circuit analysis problems with the application
of KVL around each mesh. The mesh-current method involves the following two steps:
1. Dene the mesh currents in the circuit. By convention, we draw the mesh currents with
a circle, arc or a surface on the inside perimeter of the mesh. Moreover, we dene the
mesh-current direction for all meshes to be clockwise.
2. Write a set of mesh equations using KVL. In general, we write one equation for each
mesh. Under special circumstances, the number of mesh equations may be fewer than
the total number of meshes.
In writing the mesh equation, we move through the mesh in a clockwise direction by
writing the voltage drops in terms of mesh currents. Whenever a circuit element is shared by
two meshes, as in Fig. 5.3, the voltage drop across the resistor is
V = RI = R(I
1
I
2
)
when writing the equation for mesh 1. When writing the mesh equation for mesh 2, the
clockwise direction gives a voltage drop according to convention as R(I
2
I
1
), just the opposite
as in mesh 1. Moreover, according to KCL
I = I
1
I
2
Mesh currents, as in Fig. 5.3, are not measurable with an ammeter in that they do
not equal a branch current. The current through the branch is composed of the difference
between the two mesh currents, here I = I
1
I
2
. Even though the mesh current is not real,
it is a powerful technique that simplies analysis of circuit problems as shown in the next
example.
R
I
+
V
I
1 I2
FIGURE5.3: Mesh currents.
P1: KDD
Example 5.4. Find I in the following circuit.
10 V 5 V
I
2
4
3
Solution. There are two meshes in this circuit. Mesh currents are always dened in a clockwise
direction, one for each mesh, as illustrated in the redrawn circuit that follows.
10 V 5 V
I
2
4
3
I1 I2
Summing the voltage drops around mesh 1 gives
10 +2I
1
+4 (I
1
I
2
) = 0
which simplies to
6I
1
4I
2
= 10
4 (I
2
I
1
) +3I
2
+5 = 0
P1: KDD
which simplies to
4I
1
+7I
2
= 5
The two mesh equations are written in matrix form as
6 4
4 7
I
1
I
2
10
5
Comments made in Section 5.1 on the structure and symmetry of the system matrix with
the node-voltage method also apply for the mesh-current method. We solve this problem with
MATLAB, giving
A = [6 4; 4 7];
F = [10; 5];
I = A\F
I =
1.9231
0.3846
The current I is found from I = I
1
I
2
= 1.9231 0.3846 = 1.5385 A.
When one of the branches has an independent or dependent current source in the circuit, a
modication must be made to the mesh-current method. Depending on whether the current
source is on the outer perimeter or inside the circuit, as shown in Fig. 5.4, we handle both cases
as follows:
1. The current source is located on the perimeter, as in the circuit on the left in Fig. 5.4,
where the mesh current equals the branch current. In this case, we do not write a mesh
equation because the current is known. The mesh current I
1
equals the source current,
5 V
I
2
4
3
3 A
I1 I2
5 V
I
2 3
I1 I2
3 A 10 V
FIGURE5.4: (Left) A current source on the perimeter of a circuit. (Right) A current source in a branch
between two meshes.
P1: KDD
I
1
= 3 A. The equation for mesh 2 is found by applying KVL, giving
4 (I
2
I
1
) +3I
2
+5 = 4 (I
2
3) +3I
2
+5 = 0,
which gives I
2
= 1 A.
2. The current source is locatedwithinthe circuit where the meshcurrent does not equal the
branch current as shown in Fig. 5.4 (right). Since we cannot easily write the voltage drop
across the current source, we form a supermesh. A supermesh is formed by combing two
meshes together, with one equation describing both meshes. In this case, the equation
starts wit the rst mesh and continues on to the second mesh, circumventing the voltage
drop across the current source. Here the supermesh equation is
10 +2I
1
+3I
2
+5 = 0
Because there are two unknown currents, we need two independent equations. The second
equation is written using KCL for the current source and the two mesh currents. Here the KCL
equation is I
2
I
1
= 3.
Example 5.5. Find V
0
as shown in the following circuit.
3 V
2
3
4
I
S
= 2 V
0 5
2 A
+
V
0
Solution. This circuit has four meshes, as shown in the circuit diagram that follows. Mesh
4 has a current source on the perimeter, so we do not write a mesh equation for it, but write
simply I
4
= 2 A.
P1: KDD
3 V
2
3 I1
4
IS = 2 V0
I2 I3
5
2 A
I4
+
V
0
Summing the voltages around mesh 1 gives

3 +2 (I
1
2) +3(I
1
I
2
) = 0
Simplifying gives
5I
1
3I
2
= 7
Since there is a dependent current source inside the circuit, we form a supermesh for meshes 2
and 3. Summing the voltages around supermesh 2 +3 yields
3 (I
2
I
1
) +4I
2
+5I
3
= 0
which reduces to
3I
1
+7I
2
+5I
3
= 0
Applying KCL for the dependent current source gives
2V
0
= 2 3 (I
1
I
2
) = I
3
I
2
yielding
6I
1
5I
2
I
3
= 0
P1: KDD
The three independent equations are written in matrix format as
5 3 0
3 7 5
6 5 1
I
1
I
2
I
3
7
0
0
Solution using MATLAB gives

A = [5 3 0; 3 7 5; 6 5 1];
F = [7; 0; 0];
I = A\F
I =
14.0000
21.0000
21.0000
Thus,
V
0
= 3(I
1
I
2
) = 3(14 21) = 21 V
5.3 LINEARITY, SUPERPOSITIONANDSOURCE
TRANSFORMATIONS
5.3.1 Linearity and Superposition
If a linear system is excited by two or more independent sources, then the total response is
the sum of the separate individual responses to each input. This property is called the prin-
ciple of superposition. Specically for circuits, the response to several independent sources is
the sum of responses to each independent source with the other independent sources dead,
where
A dead voltage source is a short circuit
A dead current source is an open circuit
In linear circuits with multiple independent sources, the total response is the sum of each
independent source taken one at a time. This analysis is carried out by removing all of the sources
except one, and assuming the other sources are dead. After the circuit is analyzed with the rst
source, it is set equal to a dead source and the next source is applied with the remaining sources
dead. When each of the sources have been analyzed, the total response is obtained by summing
the individual responses. Note carefully that this principle holds true solely for independent
sources. Dependent sources must remain in the circuit when applying this technique, and they
P1: KDD
must be analyzed based on the current or voltage for which it is dened. It should be apparent
that voltages and currents in one circuit differ among circuits, and that we cannot mix and
match voltages and currents from one circuit with another.
Generally, superposition provides a simpler solution than is obtained by evaluating the
total response with all of the applied sources. This property is especially valuable when dealing
with an input consisting of a pulse or delays. These are considered in future sections.
Example 5.6. Using superposition, nd V
0
as shown in the following gure.
2 3
2 A 3 A 5 10 V
+
V
0
Solution. We start by analyzing the circuit with just the 10 V source active and the two current
sources dead, as shown in the following gure.
2 3
5 10 V
+
V
0
10
The voltage divider rule easily gives the response, V
0
10
, due to the 10 V source
V
0
10
= 10
8
2 +8
= 8 V
P1: KDD
Next consider the 2 A source active, and the other two sources dead, as shown in the following
circuit.
2 3
2 A 5
+
V
0

2
Combining the resistors in an equivalent resistance, R
EQ
= 2 (3 +5) =
28
2+8
= 1.6 ,
and then applying Ohms law gives V
0
2
= 2 1.6 = 3.2 V.
Finally, consider the response, V
0
3
, to the 3 A source as shown in the following gure.
2 3
3 A 5
+
V
0
3
To nd V
0
3
, note that the 3 A current splits into 1.5 A through each branch (2 +3 and
5 ), and V
0
3
= 1.5 2 = 3 V.
The total response is given by the sum of the individual responses as
V
0
= V
0
10
+ V
0
2
+ V
0
3
= 8 +3.2 3 = 8.2 V
This is the same result we would have found if we analyzed the original circuit directly using
the node-voltage or mesh-current method.
P1: KDD
Example 5.7. Find the voltage across the 5 A current source, V
5
, in the following gure using
superposition.
3
5
2 10 V
+
V
0
5 A
+
V
5
3V
0
Solution. First consider nding the response, V
0
10
, due to the 10 V source only with the 5 A
source dead as shown in the following gure. As required during the analysis, the dependent
current source is kept in the modied circuit and should not be set dead.
3
5
2 10 V
+
V
0
+
V
5
3V
0
I = 0 A
10 10
3 V
0
10
10
A
Notice that no current ows through the open circuit created by the dead current source,
and that the current owing through the 5 resistor is 3V
0
. Therefore, applying KCL
P1: KDD
at node A gives
V
0
10
10
3
+
V
0
10
2
+3V
0
10
3V
0
10
= 0
which gives V
0
10
= 4 V. KVL gives V
0
10
5 3V
0
10
+ V
5
10
= 0, and therefore V
5
10
= 64 V.
Next consider nding the response, V
0
5
, due to the 5 Asource, with the 10 Vsource dead.
3
5
2
+
V
0

5 A
+
V
5

3V
0
B
5
5 5
I
5
First combine the two resistors in parallel (3 2 ), giving 1.2 . V
0
5
is easily calculated
by Ohms law as V
0
5
= 5 1.2 = 6 V. KCL is then applied at node B to nd I
5
, giving
3V
0
5
+ I
5
5 = 0
With V
0
5
= 6 V, I
5
= 3 6 +5 = 23 A. Finally, apply KVL around the closed path
V
0
5
5I
5
+ V
5
5
= 0
or V
5
5
= V
0
5
+5I
5
= 6 +5 23 = 121 V. The total response is given by the sum of the indi-
vidual responses as
V
5
= V
5
10
+ V
5
5
= 64 +121 = 185 V
5.3.2 Equivalent Sources
We call two sources equivalent if they each produce the same voltage and current regardless of
the resistance. Consider the two circuits in Fig. 5.5. If I
s
=
V
s
R
s
as shown in the gure on the
right, then the same current and voltage are seen in resistor R
l
in either circuit as easily shown
P1: KDD
V
S
R
S
R1
Il
+
Vl
R1
Il
+
Vl
R
S
S
S
S
V
I
R
=
FIGURE5.5: Two equivalent circuits.
using voltage and current divider rules. For the circuit on the left, the current and voltage for
R
l
are
V
l
= V
s
R
l
R
l
+ R
s
and I
l
=
V
s
R
l
+ R
s
R1
Rs
Il
+
Vl
VS R1
Rs
Rx VS
Il
+
Vl
Rs
Rx
Il
+
Vl
R1 Rs
Il
+
Vl
R1
s
s
s
V
I
R
=
s
s
s
V
I
R
=
FIGURE5.6: Equivalent circuits. In both circuits on the left, the resistor R
x
has no effect on the circuit
and can be removed.
P1: KDD
For the circuit on the right with I
s
=
V
s
R
s
, the current and voltage for R
l
are
I
l
= I
s
R
s
R
l
+ R
s
=
V
s
R
l
+ R
s
and V
l
= I
l
R
l
= V
s
R
l
R
l
+ R
s
Therefore, we can replace the voltage source and R

s
in the box in Fig. 5.5 (left) with the current
source and R
s
in the box in Fig. 5.5 (right). We shall see that exchanging source plus resistor
according to Fig. 5.5 simplies the analysis of circuits.
Consider Fig. 5.6. In the two circuits on the left, the resistor R
x
has no impact on the
voltage and current on R
l
, and as indicated, these circuits can be replaced by the two circuits
on the right by completely removing R
x
.
Example 5.8. Use source transformations to nd V
0
in the following gure.
4
2
2
4
4 V
4 V
3 A
+
V
0
Solution. Our strategy in this solution involves combining resistors in series and parallel,
current sources in parallel and voltage sources in series. We rst remove the 4 resistor since it
is in series with the 3 A source and has no effect on the circuit, and transform the 2 resistor
and 4 V source into a
4
2
= 2 A source in parallel with a 2 resistor as shown in the following
gure. Notice that the current direction in the transformed source is in agreement with the
polarity of the 4 V source.
2 4
4 V
3 A
+
V
0
2 A 2
P1: KDD
As shown in the next gure, combining the two parallel current sources results in a 1 A source,
and combining the two parallel resistors results in a 1 resistance.
4
4 V
+
V
0
1 1 A
Another source transformation is carried out on the current source and resistor in parallel as
shown in the next gure.
4 V
4
+
V
0
1
1 V
The two voltage sources are combined, resulting in a 5 V source. Using the voltage divider gives
V
0
= 5
4
4 +1
= 4 V
P1: KDD
52
P1: KDD
53
C H A P T E R 6
Th evenins and Nortons Theorems
Any combination of resistances, controlled sources, and independent sources with two external
terminals (A and B, denoted A,B) can be replaced by a single resistance and an independent
source, as shown in Fig. 6.1. A Th evenin equivalent circuit reduces the original circuit into
a voltage source in series with a resistor (upper right of Fig. 6.1). A Norton equivalent cir-
cuit reduces the original circuit into a current source in parallel with a resistor (lower right
of Fig. 6.1). These two theorems help reduce complex circuits into simpler circuits. We re-
fer to the circuit elements connected across the terminals A,B (that are not shown) as the
load. The Th evenin equivalent circuit and Norton equivalent circuits are equivalent to the
original circuit in that the same voltage and current are observed across any load. Usually,
the load is not included in the simplication because it is important for other analysis, such
as maximum power expended by the load. Although we focus here on sources and resistors,
these two theorems can be extended to any circuit composed of linear elements with two
terminals.
6.1 TH

EVENINS THEOREM
Th evenins Theorem states that an equivalent circuit consisting of an ideal voltage source, V
OC
,
in series with an equivalent resistance, R
EQ
, can be used to replace any circuit that consists
of independent and dependent voltage and current sources and resistors. V
OC
is equal to the
open circuit voltage across terminals A,B as shown in Fig. 6.2, and calculated using standard
techniques such as the node-voltage or mesh-current methods.
The resistor R
EQ
is the resistance seen across the terminals A,B when all sources are
dead. Recall that a dead voltage source is a short circuit and a dead current source is an open
circuit.
P1: KDD
V
OC
REQ
B
A
REQ I
SC
B
A
Replaced by
Independent and
dependent
sources, and
resistances
A
B
FIGURE 6.1: A general circuit consisting of independent and dependent sources can be replaced by a
voltage source (V
OC
) in series with a resistor (R
EQ
) or a current source (I
SC
) in parallel with a resistor
(R
EQ
).
Independent and
dependent
sources, and
resistances
A
B
+
V
OC
FIGURE 6.2: The open circuit voltage, V

OC
, is calculated across the terminals A,B using standard
techniques such as node-voltage or mesh-current methods.
P1: KDD
TH

EVENIN S ANDNORTON S THEOREMS 55
Example 6.1. Find the Th evenin equivalent circuit with respect to terminals A,B for the
following circuit.
10 V 4 A
2
2
B
A
Solution. The solution to nding the Th evenin equivalent circuit is done in two parts, rst
nding V
OC
and then solving for R
EQ
. The open circuit voltage, V
OC
, is easily found using the
node-voltage method as shown in the following circuit.
10 V 4 A
2
2
B
A
+
V
OC
The sum of currents leaving the node is

V
OC
10
2
+
V
OC
2
4 = 0
and V
OC
= 9 V.
Next, R
EQ
is found by rst setting all sources dead (the current source is an open circuit
and the voltage source is a short circuit), and then nding the resistance seen from the terminals
A,B as shown in the following gure.
P1: KDD
2
2
B
A
REQ
From the previous circuit, it is clear that R
EQ
is equal to 1 (that is, 2 2 ). Thus, the
Th evenin equivalent circuit is
9 V
1
B
A

It is important to note that the circuit used in nding V
OC
is not to be used in nding R
EQ
as not all voltages and currents are relevant in the other circuit and one cannot simply mix and
match.
6.2 NORTONS THEOREM
Nortons Theorem states that an equivalent circuit consisting of an ideal current source, I
SC
,
in parallel with an equivalent resistance, R
EQ
, can be used to replace any circuit that consists
of independent and dependent voltage and current sources and resistors. I
SC
is equal to the
current owing through a short between terminals A,B as shown in Fig. 6.3, and calculated
using standard techniques such as the node-voltage or mesh-current methods. The Th evenin
P1: KDD
TH

Independent and
dependent
sources, and
resistances
A
B
ISC
FIGURE 6.3: The short circuit current, I
SC
, is calculated by placing a short across the terminals A,B,
and nding the current through the short using standard techniques such as node-voltage or mesh-current
methods.
and Norton equivalent circuits are related to each other according to
R
EQ
=
V
OC
I
SC
(6.1)
This is easily seen by shorting the terminals A,B in Fig. 6.2. The current owing through the
short is
V
OC
I
SC
in agreement with Eq. (6.1). It should be clear that Figs. 6.2 and 6.3 are source
transformations of each other.
Example 6.2. Find the Norton equivalent circuit with respect to terminals A,Bfor the following
circuit.
10 V 4 A
2
2
B
A

P1: KDD
Solution. This circuit is the same as Ex. 6.1, so R
EQ
= 1 . To nd I
SC
we place a short
between the terminals A,B as shown in the following gure.
10 V 4 A
2
2
B
A
I
SC
Note that the 2 resistor is in parallel with the short across terminals A,B, therefore it is
removed since no current ows through it, as shown in the next gure.
10 V 4 A
2
B
A
I
SC
I
2
+ 10 V
Note also that current I
2
equals 5 A since the 10 V source is applied directly across the 2
resistor. Applying KCL at the node denoted A, gives
0 = I
2
4 + I
SC
= 5 4 + I
SC
and I
SC
= 9 A. We could have found the current I
SC
directly from the solution of Ex. 6.1 since
I
SC
=
V
OC
R
EQ
=
9
1
= 9 A
P1: KDD
TH

The Norton equivalent circuit is shown in the following gure.
B
A
9 A 1

6.3 DEPENDENTSOURCES ANDTH

EVENINANDNORTON
EQUIVALENTCIRCUITS
If a circuit connected to terminals A,B contains dependent sources, the process for nding R
EQ
for either the Th evenin or Norton equivalent circuit must be modied, because the dependent
source has resistance, and this resistance cannot be calculated when setting all sources dead.
In this case we nd V
OC
and I
SC
, and then calculate R
EQ
=
V
OC
I
SC
.
Example 6.3 Find the Th evenin equivalent circuit with respect to terminals A,B for the fol-
lowing circuit.
10 V
3
2
5
B
A
5 A
+
V
1
3V
1

P1: KDD
Solution. Since this circuit has a dependent source, R
EQ
is found by R
EQ
=
V
OC
I
SC
. Lets rst
nd V
OC
using the mesh-current method as labeled in the next gure.
10 V
3
2 I
1
5
I
2
B
A
+
V
OC
5 A
I
3
+
V
1
3V1
Note that since there are two current sources on the perimeter of the circuit, I
2
= 5 A
and I
3
= 3V
1
= 3 2 (I
1
I
2
) = 6I
1
+30.
10 +3I
1
+2 (I
1
I
2
) = 0
Simplifying with I
2
= 5 A gives I
1
= 0 A. Applying KVL around mesh 2 to nd V
OC
gives
2 (I
2
I
1
) +5 (I
2
I
3
) + V
OC
= 0
With I
1
= 0 A, I
2
= 5 A and I
3
= 30 A, gives V
OC
= 185 V.
Next, we nd I
SC
using the node-voltage method as labeled in the next gure.
Summing the currents leaving node gives
V
1
10
3
+
V
1
2
+
V
1
5
+3V
1
= 0
and V
1
=
100
121
V.
P1: KDD
TH

Applying KCL at terminal A gives
10 V
3
2
5
B
A
5 A
+
V
1
3V
1
I
SC
3V
1
5
V
1
5
+ I
SC
= 0
With V
1
=
100
121
, gives I
SC
= 7.65 A. Therefore R
EQ
=
V
OC
I
SC
=
185
7.65
= 24.18 . The Th evenin
equivalent circuit is
B
A
24.18
185 V

P1: KDD
62
P1: KDD
63
C H A P T E R 7
Inductors
In the previous sections, we considered circuits involving sources and resistors that are de-
scribed with algebraic equations. Any changes in the source are instantaneously observed in
the response. In this section, we examine the inductor, a passive element that relates the
voltagecurrent relationship with a differential equation. Circuits that contain inductors are
written in terms of derivatives and integrals. Any changes in the source with circuits that
contain inductors, i.e., a step input, have a response that is not instantaneous, but has nat-
ural response that changes exponentially and a forced response that is the same form as the
source.
An inductor is a passive element that is able to store energy in a magnetic eld, and is
made by winding a coil of wire around a core that is an insulator or a ferromagnetic material. A
magnetic eld is established when current ows through the coil. We use the symbol
to represent the inductor in a circuit; the unit of measure for inductance is the henry or henries
(H), where 1 H = 1 Vs/A. The relationship between voltage and current for an inductor is
given by
v = L
di
dt
(7.1)
The convention for writing the voltage drop across an inductor is similar to that of a resistor, as
shown in Fig. 7.1.
Physically, current cannot change instantaneously through an inductor since an innite
voltage is required according to Eq. (7.1) (i.e., the derivative of current at the time of the
instantaneous change is innity). Mathematically, a step change in current through an inductor
is possible by applying a voltage that is a Dirac delta function. For convenience, when a circuit
has just DC currents (or voltages), the inductors can be replaced by short circuits since the
voltage drop across the inductors are zero.
P1: KDD
L
+ v
i
FIGURE7.1: An inductor.
Example 7.1. Find v in the following circuit.
+
v
5 A 2 H
Solution. Accordingly,
v = L
di
dt
= 2
d (5)
dt
= 0
This example shows that an inductor acts like a short circuit to DC current.
Example 7.2. Find I in the following circuit, given that the source has been applied for a very
long time.
6
5 H
3 H 4
4
1 H
2
3 H 5 V
I
P1: KDD
INDUCTORS 65
Solution. Since the source has been applied for a very long time, only DC current ows in the
circuit and the inductors can be replaced by short circuits as shown in the following gure.
2
4 2
4
6
6 V
I
To nd I, we nd the total resistance seen by the source and use Ohms law as follows:
R
EQ
= 6 ((4 4) +(2 2)) = 2
therefore,
I =
6
2
= 3
Example 7.3. Find v in the following circuit.
0 1 2 3
t (s)
1
i (A)
+
v
2 H i
Solution. The solution to this problem is best approached by breaking it up into time intervals
consistent with the changes in input current. Clearly for t < 0 and t > 2, the current is zero
and therefore v = 0. We use Eq. (7.1) to determine the voltage in the other two intervals as
follows.
P1: KDD
For 0 < t < 1
In this interval, the input is i = t, and
v = L
di
dt
= 2
d(t)
dt
= 2 V
For 1 t 2
In this interval, the input is i = (t 2) , and
v = L
di
dt
= 2
d ((t 2))
dt
= 2 V
Equation (7.1) denes the voltage across an inductor for a given current. Suppose one is given a
voltage across an inductor and asked to nd the current. We start from Eq. (7.1) by multiplying
both sides by dt, giving
v (t) dt = Ldi
Integrating both sides yields
t
t
0
v () d = L
i (t)
i (t
0
)
d
or
i (t) =
1
L
t
t
0
v () d +i (t
0
) (7.2)
For t
0
= 0, as is often the case in solving circuit problems, Eq. (7.2) reduces to
i (t) =
1
L
t
0
v () d +i (0) (7.3)
and for t
0
= , the initial current is by denition equal to zero, and therefore Eq. (7.2)
reduces to
i (t) =
1
L
t
v () d (7.4)
The initial current in Eq. (7.2), i (t
0
), is usually dened in the same direction as i , which means
i (t
0
) is a positive quantity. If the direction of i (t
0
) is in the opposite direction of i (as will happen
when we write node equations), then i (t
0
) is negative.
P1: KDD
INDUCTORS 67
Example 7.4. Find i for t 0 if i (0 ) = 2 A and v(t) = 4e
3t
u(t) in the following circuit.
2 H
i
v
Solution. From Eq. (7.2), we have
i (t) =
1
L
t
t
0
vd +i (t
0
) =
1
2
t
0
4e
3
d +i (0) =
1
2
t
0
4e
3
d +2
= 2
e
3
3
t
=0
+2
=
2
3
4 e
3t
u(t)V
7.1 POWERANDENERGY
Since the inductor is a passive element, it absorbs power according to the relationship
p = vi = Li
di
dt
(7.5)
Within the inductor, power is not consumed as heat, as happens in a resistor, but stored
as energy in the magnetic eld around the coil during any period of time [t
0
, t] as
w(t) w(t
0
) =
t
t
0
p dt = L
t
t
0
i
di
dt
dt (7.6)
= L
i (t)
i (t
0
)
i di =
1
2
L
[i (t)]
2
[i (t
0
)]
2
where the unit of energy is joules ( J). At time equal to negative innity, we assume that the
initial current is zero and thus the total energy is given by
w(t) =
1
2
Li
2
(7.7)
P1: KDD
Any energy stored in the magnetic eld is recoverable. If power is negative in Eq. (7.5),
energy is being extracted from the inductor. If power is positive, energy is being stored in the
inductor.
Example 7.5. Find the inductor power in the following circuit for t > 0 when i (0) = 0 A.
2
+2
v (V)
0 1 2
t (s)
v 2 H
i
Solution. We rst solve for current so that Eq. (7.5) can be applied to nd the power. As
before, the solution is best approached by breaking it up into time intervals consistent with the
changes in input voltage.
For 0 < t < 1
In this interval, the input is v = 2t, and
i (t) =
1
L
t
0
v () d +i (0) =
1
2
t
0
2 d =
t
2
2
A
Power for this interval is
p = vi = 2t
t
2
2
= t
3
W
The current at t = 1 needed for the initial condition in the next part is
i (1) =
t
2
2
t=1
=
1
2
A
For 1 t 2
In this interval, the input is v = 2 (t 2), and
i (t) =
1
L
t
1
v ()d +i (1) =
1
2
t
1
2 ( 2)d +
1
2
=
t
2
2
2t +2 A
P1: KDD
INDUCTORS 69
Accordingly, power is
p = vi = 2 (t 2)
t
2
2
2t +2
= t
3
6t
2
+12t 8 W
For t > 2
Power is zero in this interval since the voltage is zero.
P1: KDD
70
P1: KDD
71
C H A P T E R 8
Capacitors
Acapacitor is a device that stores energy in an electric eld by charge separation when appropri-
ately polarized by a voltage. Simple capacitors consist of parallel plates of conducting material
that are separated by a gap lled with a dielectric material. Dielectric materials, that is, air, mica,
or Teon, contain a large number of electric dipoles that become polarized in the presence of an
electric eld. The charge separation caused by the polarization of the dielectric is proportional
to the external voltage and given by
q(t) = C v (t) (8.1)
where C represents the capacitance of the element. The unit of measure for capacitance is
the farad or farads (F), where 1 F = 1 C/V. We use the symbol
C
to denote a capacitor;
most capacitors are measured in terms of microfarads (1 F = 10
6
F) or picofarads (1 pF =
10
12
F). Figure 8.1 illustrates a capacitor in a circuit.
Using the relationship between current and charge, Eq. (8.1) is written in a more useful
form for circuit analysis problems as
i =
dq
dt
= C
dv
dt
(8.2)
The capacitance of a capacitor is determined by the permittivity of the dielectric ( =
8.854 10
12
F/M for air) that lls the gap between the parallel plates, the size of the gap
between the plates, d, and the cross-sectional area of the plates, A, as
C =
A
d
(8.3)
As described, the capacitor physically consists of two conducting surfaces that stores
charge, separated by a thin insulating material that has a very large resistance. In actuality,
current does not owthrough the capacitor plates. Rather, as James Clerk Maxwell hypothesized
when he described the unied electromagnetic theory, a displacement current ows internally
between capacitor plates and this current equals the current owing into the capacitor and out
of the capacitor. Thus KCL is maintained. It should be clear from Eq. (8.2) that dielectric
P1: KDD
v
C
i
FIGURE8.1: Circuit with a capacitor.
materials do not conduct DC currents; capacitors act as open circuits when DC currents are
present.
Example 8.1. Suppose v = 5 V and C = 2 F for the circuit shown in Fig. 8.1 Find i .
Solution.
i = C
dv
dt
= 2
d
dt
(5) = 0
A capacitor is an open circuit to DC voltage.
Example 8.2. Find I in the following circuit given that the current source has been applied
for a very long time.
4 A 2 1 F
3
2 F
2
I
4 H
2 H
2 H
2 F
P1: KDD
CAPACITORS 73
Solution. Since the source has been applied for a very long time, only DC current ows in
the circuit. Furthermore the inductors can be replaced by short circuits and capacitors can be
replaced by open circuits, as shown in the following gure.
4 A 2
I
2
To nd I, we use the current divider law as
I = 4
1
2
1
2
+
1
2
= 2 A
Example 8.3. Find i for the following circuit.
0 1 2
1
v (V)
2 F
v
i
t (s)
Solution. For t < 0 and t > 2, v = 0 V, and therefore i = 0 in this interval. For nonzero val-
ues, the voltage waveform is described with two different functions, v = t V for 0 t 1, and
v = (t 2) V for 1 < t 2. Equation (8.2) is used to determine the current for each interval
as follows.
For 0 < t < 1
i = C
dv
dt
= 2
d
dt
(t) = 2 A
P1: KDD
For 1 t 2
i = C
dv
dt
= 2
d
dt
((t 2)) = 2 A
Voltage cannot change instantaneously across a capacitor. To have a step change in voltage
across a capacitor requires that an innite current ow through the capacitor, which is not
physically possible. Of course, this is mathematically possible using a Dirac delta function.
Equation (8.2) denes the current through a capacitor for a given voltage. Suppose one is
given a current through a capacitor and asked to nd the voltage. To nd the voltage, we start
from Eq. (8.2) by multiplying both sides by dt, giving
i (t) dt = C dv
Integrating both sides yields
t
t
0
i () d = C
v(t)
v(t
0
)
dv
or
v(t) =
1
C
t
t
0
i dt +v(t
0
) (8.4)
For t
0
= 0, Eq. (8.4) reduces to
v(t) =
1
C
t
0
i dt +v(0) (8.5)
and for t
0
= , Eq. (8.4) reduces to
v(t) =
1
C
t
i () d (8.6)
The initial voltage in Eq. (8.4), v(t
0
), is usually dened with the same polarity as v, which
means v(t
0
) is a positive quantity. If the polarity of v(t
0
) is in the opposite direction of v (as will
happen when we write mesh equations), then v(t
0
)is negative.
P1: KDD
CAPACITORS 75
Example 8.4. Find v for the circuit that follows.
2 F
0 2
2
i
s
(A)
t (s)
i
s
+
v
Solution. The current waveform is described with three different functions: for the interval
t 0, for the interval 0 < t 2, and for t >2. To nd the voltage, we apply Eq. (8.6) for each
interval as follows.
For t < 0
v(t) =
1
C
t
i dt =
1
2
0
0 dt = 0 V
For 0 t 2
v(t) =
1
C
t
0
i dt +v(0)
and with v(0) = 0,we have
v(t) =
1
2
t
0
d =
1
2
2
2
t
0
=
t
2
4
V
The voltage at t = 2 needed for the initial condition in the next part is
v(2) =
t
2
4
t=2
= 1 V
For t > 2
v(t) =
1
C
t
2
i dt +v(2) =
1
2
t
2
0 dt +v(2) = 1 V
P1: KDD
8.1 POWERANDENERGY
The capacitor is a passive element that absorbs power according to the relationship
p = vi = C v
dv
dt
(8.7)
Energy is stored in the electric eld during any period of time [t
0
, t] as
w(t) w(t
0
) =
t
t
0
p dt = C
t
t
0
v
dv
dt
dt
= C
v(t)
v(t
0
)
v dv =
1
2
C([v(t)]
2
[v (t
0
)]
2
) (8.8)
where the unit of energy is joules ( J). At time equal to negative innity, we assume that the
initial voltage is zero and thus the total energy is given by
w(t) =
1
2
C v
2
(8.9)
Any energy stored in the electric eld is recoverable. If power is negative in Eq. (8.7), energy is
being extracted from the capacitor. If power is positive, energy is being stored in the capacitor.
Example 8.5. Find the power and energy for the following circuit.
v
s
(t) =
0 V t < 0
t
2
V 0 t 1
e
(t1)
V t > 1
2 F v
s
i
Solution. To nd the power, we rst need to nd the current calculated from Eq. (8.2).
i (t) = C
dv
dt
=
0 A t < 0
4 t A 0 t 1
2e
(t1)
A t > 1
P1: KDD
CAPACITORS 77
Equation (8.7) is used to nd the power as follows.
p(t) = v i =
0 t < 0
t
2
4t = 4t
3
W 0 t 1
e
(t1)
(2e
(t1)
) = 2e
2(t1)
W t > 1
The energy in each interval is calculated using Eq. (8.9) as follows.
w(t) =
1
2
C v
2
=
0 t < 0
1
2
2[t
2
]
2
= t
4
J 0 t 1
1
2
2[e
(t1)
]
2
= e
2(t1)
J t > 1
Note that energy is being stored in the interval 0 t 1 since power is positive, and energy is
being extracted from the electric eld by the source for t > 1 since power is negative.
From Eq. (8.8), we calculate the energy stored in the electric eld during time interval
[0, 1] as
w(1) w(0) =
1
2
2(v(1)
2
v(0)
2
) = 1 J
and the energy delivered from the electric eld in the interval [1, ] as
w() w(1) =
1
2
2(v ()
2
v (1)
2
) = 1 J
P1: KDD
78
P1: KDD
79
C H A P T E R 9
Inductance and Capacitance
Combinations
As with resistors, it is possible to reduce complex inductor and capacitor circuits into simpler,
equivalent circuits by combining series and parallel collections of like elements. Consider the
following circuit consisting of N inductors in series. Since the same current ows through each
inductor, the voltage drop across each inductor is v
i
= L
i
di
dt
. Applying KVLon this circuit gives
v
s
= v
1
+v
2
+ +v
N
= L
1
di
dt
+ L
2
di
dt
+ + L
N
di
dt
= (L
1
+ L
2
+ + L
N
)
di
dt
= L
EQ
di
dt
Thus, inductors connected in a series can be replaced by an equivalent inductance, whereby
L
EQ
= L
1
+ L
2
+ + L
N
(9.1)
Next, consider N inductors connected in parallel as shown in Fig. 9.1. Since the same
voltage is across each inductor, the current through each inductor is i
i
=
1
L
i
t
_
t
0
v
0
dt +i
i
(t
0
).
Applying KCL on the upper node of this circuit gives
i
s
=
N
i =1
_
_
1
L
i
t
_
t
0
v
0
dt +i
i
(t
0
)
_
_
=
_
1
L
1
+
1
L
2
+ +
1
L
N
_
t
_
t
0
v
0
dt +
N
i =1
i
i
(t
0
)
=
1
L
EQ
t
_
t
0
v
0
dt +i
s
(t
0
)
P1: KDD
+ v
1

L
1
L
2
i
+ v
2

v
s
+
vN
L
N
v
s
L
EQ
i
FIGURE9.1: (Left) N inductors in series. (Right) An equivalent circuit for inductors in series.
Thus, inductors connected in parallel can be replaced by an equivalent inductance, where-
by
L
EQ
=
1
1
L
1
+
1
L
2
+ +
1
L
N
(9.2)
For the case of two inductors in parallel, Eq. (9.2) reduces to
L
EQ
=
L
1
L
2
L
1
+ L
2
(9.3)
Equations (9.1) and (9.2) are similar to the results we found for resistors in series and parallel,
and the process used for simplifying resistor circuits is the same used for inductors in series and
parallel.
L1
is
+
v
0
L2 LN
+
v0
is
iN i2 i1
FIGURE9.2: (Left) N inductors in parallel. (Right) An equivalent circuit for inductors in parallel.
P1: KDD
INDUCTANCEANDCAPACITANCECOMBINATIONS 81
Example 9.1. Find L
EQ
1 H 4 H 2 H
2 H 4 H 6 H 6 H
LEQ
Solution. The equivalent inductance is found by forming series and parallel combinations
from right to left until it reduces to a single inductance as shown in the following gure.
1 H 4 H 2 H
2 H 4 H 6 H 6 H
L
EQ
2 +2= 4 H
4 4 = 2 H
4 +2= 6 H
6 6 6 = 2 H
1 + 2 = 3 H
If follows that
L
EQ
= 1 +(6 6 (4 +(4 (2 +2))))
= 1 +
_
6 6
_
4 +
_
1
1
4
+
1
4
___
= 1 +
_
1
1
6
+
1
6
+
1
6
_
= 1 +2 = 3 H
P1: KDD
C1
is
+
v
0
C2 CN CN
+
v0
FIGURE9.3: (Left) N capacitors in parallel. (Right) An equivalent circuit for capacitors in parallel.
Next, consider N capacitors connected in parallel, as shown in Fig. 9.3. Since the same voltage
is across each capacitor, the current through each inductor is i
i
= C
i
dv
0
dt
. Applying KCL on the
upper node of this circuit gives
i
s
= C
1
dv
0
dt
+C
2
dv
0
dt
+ +C
N
dv
0
dt
= C
EQ
dv
0
dt
Thus, capacitors connected in series can be replaced by an equivalent capacitance, whereby
C
EQ
= C
1
+C
2
+ +C
N
(9.4)
Next, consider N capacitors connected in series as shown in Fig. 9.4. Since the same
current ows through each capacitor, the voltage across each inductor is v
i
=
1
C
i
t
_
t
0
i dt +v
i
(t
0
).
Applying KVL around this circuit gives
+ v
1

C
1
C
2
i
+ v
2

vs
+
v
N
vs
i
C
N
+
v
N
C
EQ
FIGURE9.4: (Left) N capacitors in series. (Right) An equivalent circuit for capacitors in series.
P1: KDD
v
s
=
N
i =1
_
_
1
C
i
t
_
t
0
i dt +v
i
(t
0
)
_
_
=
_
1
C
1
+
1
C
2
+ +
1
C
N
_
t
_
t
0
i dt +
N
i =1
v
i
(t
0
)
=
1
C
EQ
t
_
t
0
i dt +v
s
(t
0
)
Thus, capacitors connected in series can be replaced by an equivalent capacitance, whereby
C
EQ
=
1
1
C
1
+
1
C
2
+ +
1
C
N
(9.5)
For the case of two capacitors in series, Eq. (9.5) reduces to
C
EQ
=
C
1
C
2
C
1
+C
2
(9.6)
Equations (9.5) and (9.6) are similar to the results we found for resistors in parallel and
series, respectively. That is, we treat capacitors in parallel using the techniques for resistors in
series, and capacitors in series as resistors in parallel.
Example 9.2. Reduce the following circuit to a single capacitor and inductor.
6 F
6 F
0.5 H
3 F
3 F
3 H
2 H
2 H 2 H
Solution. The equivalent inductance is found by forming series and parallel combinations,
from right to left, of inductors and capacitors until the analysis reduces the circuit to a single
inductance and capacitance. Consider the inductors rst as shown in the following gure on
the right, which results in 1.5 H. Also note that the two parallel capacitors equal 6 F.
P1: KDD
6 F
6 F
0.5 H
3 F
3 F
3 H
2 H
2 H 2 H
2 2 = 1 H
2 + 1 = 3 H
3 3 = 1.5 H 3 + 3 = 6 F
Next we slide the 1.5 H equivalent inductance to the left past the capacitors as shown
in the following gure. The two series inductors equal 2 H, and the three capacitors in series
(treated like resistors in parallel) equal
1
1
6
+
1
6
+
1
6
= 2 F.
6 F 6 F 6 F
1.5 H 0.5 H
6 6 6 = 2 F 0.5 + 1.5 = 2 H
The nal reduced circuit is shown in the following gure.
2 F
2 H
P1: KDD
The next example illustrates how to simplify a circuit and then apply the mesh-current
method to solve for unknown currents.
Example 9.3. (a) Find i (t), i
1
(t), i
2
(t) and v(t) for the following circuit for t 0 given
i
1
(0
) = 5 A and i
2
(0
) = 15 A. (b) Find the initial energy stored in the inductors. (c) Find
the energy dissipated in the resistors between t = 0 and t = . (d) Find the energy trapped in
the inductors at t = .
3 H 6 H 300 600 200
400
i
i
1
i
2
+
v
Solution
(a) For ease in solution, rst simplify the circuit by combining the three resistors as
R
EQ
= 400 +
1
1
200
+
1
300
+
1
600
= 500
and two inductors as L
EQ
=
36
3+6
= 2 H as shown in the following circuit.
2 H
i
+
v
500
i
We use the mesh-current method to nd v(t) as follows. Recall that the voltage drop
across an inductor is v
L
= L
di
dt
, so we have
500i +2
di
dt
= 0
P1: KDD
or
di
dt
+250i = 0
The previous differential equation has the characteristic equation
s +250 = 0
with root s = 250 and solution
i (t) = K
1
e
250t
A
Note that the forced response is zero since there is no input. Because the energy stored in an
inductor cannot change instantaneously,
i
1
(0
) = i
1
(0
+
) = 5 A, i
2
(0
) = i
2
(0
+
) = 15 A and
i (0
) = i (0
+
) = i
1
(0
+
) +i
2
(0
+
) = 20 A
To determine K
1
we use i (0) = 20 = K
1
. Thus, our solution is i (t) = 20e
250t
u(t) A. To nd
i
1
(t) and i
2
(t) we nd v(t) = L
EQ
di
dt
and then use i
i
(t) =
1
L
i
t
_
0
v dt +i
i
(0). For t 0
v (t) = 2
di
dt
= 10000e
250t
u(t) V
and
i
1
(t) =
1
3
t
_
0
(10000e
250
) d +5 =
40
3
e
250
t
=0
+5 =
40
3
e
250t
40
3
+5
=
40
3
e
250t
25
3
A
i
2
(t) =
1
6
t
_
0
(10000e
250
) d +15 =
40
6
e
250
t
=0
+15 =
20
3
e
250t
20
3
+
45
3
=
20
3
e
250t
+
25
3
A
Naturally i (t) = i
1
(t) +i
2
(t) = 20e
250t
u(t) A.
(b) From Eq. 7.7, the total initial energy stored in the inductors equals
w
L
(0) =
1
2
L
1
i
2
1
+
1
2
L
2
i
2
2
=
1
2
3 5
2
+
1
2
6 15
2
= 712.5 J
P1: KDD
(c) The energy dissipated in the resistors equals
w
R
EQ
=
_
0
R
EQ
i
2
(t) dt =
_
0
500 (20e
250t
)
2
dt
=
_
0
500 400e
500t
dt = 400e
500t
0
= 400 J
(d) The energy trapped in the inductors at t = equals
w
1
() =
1
2
L
1
i
2
1
() =
1
2
3
_
25
3
_
2
= 104.1667 J
w
2
() =
1
2
L
2
i
2
2
() =
1
2
6
_
25
3
_
2
= 208.333 J
Notice that energy trapped in the two inductors equals the total initial stored energy minus the
energy dissipated in the resistors. Also note that while energy is trapped in the two inductors at
t = , the energy stored in the equivalent inductor, L
EQ
, is zero. Note that the initial energy
stored in the equivalent inductor is
1
2
2 (20)
2
= 400 J, and that the energy dissipated in the
resistors equals the energy stored in the equivalent inductor at t = 0.
P1: KDD
88
P1: KDD
89
C H A P T E R 1 0
AGeneral Approach to Solving
Circuits Involving Resistors,
Capacitors and Inductors
Sometimes a circuit consisting of resistors, inductors and capacitors cannot be simplied by
bringing together like elements in series and parallel combinations. Consider the circuit shown
in Fig. 10.1. In this case, the absence of parallel or series combinations of resistors, inductors
or capacitors prevents us from simplifying the circuit for ease in solution, as in Ex. 10.1. In
this section, we apply the node-voltage and mesh-current methods to write equations involving
integrals and differentials using element relationships for resistors, inductors and capacitors.
From these equations, we can solve for unknown currents and voltages of interest.
Example 10.1. Write the node equations for the following circuit for t 0 if the initial
conditions are zero.
vs(t)
C1
C2
R2
R1
L1
Solution. With the reference node at the bottom of the circuit, we have two essential nodes,
as shown in the following redrawn circuit. Recall that the node involving the voltage source is a
known voltage and that we do not write a node equation for it. When writing the node-voltage
equations, the current through a capacitor is i
c
= C v, where v is the derivative of the
P1: KDD
1 F
3 F 4 F
5 H
2 H
3
2
FIGURE10.1: A circuit that cannot be simplied.
voltage across the capacitor, and the current through an inductor is i
L
=
1
L
t
_
0
vd +i
L
(0),
where v is the voltage across the inductor. Since the initial conditions are zero, the term
i
L
(0) = 0.
vs(t)
C1
C2
R2
R1
L1
+
v1

+
v2
2
1
C
1
( v
1
v
s
) +
v
1
R
1
+
v
1
v
2
R
2
= 0
which simplies to
C
1
v
1
+
_
1
R
1
+
1
R
2
_
v
1
1
R
2
v
2
= C
1
v
s
v
2
v
1
R
2
+C
2
v
2
+
1
L
1
t
_
0
(v
2
v
s
) d = 0
P1: KDD
GENERAL APPROACHTOSOLVINGCIRCUITS 91
Typically, we eliminate integrals in the node equations by differentiating. When applied to the
previous expression, this gives
1
R
2
v
2
1
R
2
v
1
+C
2
v
2
+
1
L
1
v
2
1
L
1
v
s
= 0
and after rearranging yields
v
2
+
1
C
2
R
2
v
2
+
1
C
2
L
1
v
2
1
C
2
R
2
v
1
=
1
C
2
L
1
v
s
When applying the node-voltage method, we generate one equation for each essential
node. To write a single differential equation involving just one node voltage and the inputs, we
use the other node equations and substitute into the node equation of the desired node voltage.
Sometimes this involves differentiation as well as substitution. The easiest case involves a node
equation containing an undesired node voltage without its derivatives. Another method for
creating a single differential equation is to use the D operator.
Consider the node equations for Ex. 10.1, and assume that we are interested in obtaining
a single differential equation involving node voltage v
1
and its derivatives, and the input. For
ease in analysis, let us assume that the values for the circuit elements are R
1
= R
2
= 1 , C
1
=
C
2
= 1 F, and L
1
= 1 H, giving us
v
1
+2v
1
v
2
= v
s
and
v
2
+ v
2
+ v
2
v
1
= v
s
Using the rst equation, we solve for v
2
, calculate v
2
and v
2
, and then substitute into the second
equation as follows.
v
2
= v
1
+2v
1
v
s
v
2
= v
1
+2 v
1
v
s
v
2
=
...
v
1
+2 v
1
...
v
s
After substituting into the second node equation, we have
...
v
1
+2 v
1
...
v
s
+ v
1
+2 v
1
v
s
+ v
1
+2v
1
v
s
v
1
= v
s
and after simplifying
...
v
1
+3 v
1
+2 v
1
+2v
1
=
...
v
s
+ v
s
+ v
s
v
s
P1: KDD
The Doperator also provides us the means to write the two differential equations as a single dif-
ferential equation involving only v
1
and v
s
. In terms of the D operator, the two node equations
are written as
(D+2)v
1
v
2
= Dv
s
(D
2
+ D+1)v
2
Dv
1
= v
s
Solving the rst equation for v
2
gives v
2
= (D+2) Dv
s
, and after substituting v
2
into the
second equation yields
(D
2
+ D+1)(D+2)v
1
D(D
2
+ D+1)v
s
Dv
1
= v
s
Upon simplication
(D
3
+3D
2
+2D+2)v
1
= (D
3
+ D
2
+ D+1)v
s
Returning to the differential notation, the result is
...
v
1
+3 v
1
+2 v
1
+2v
1
=
...
v
s
+ v
s
+ v
s
v
s
which is the same expression we calculated before.
In general, the order of the differential equation relating a single output variable and
the inputs is equal to the number of energy storing elements in the circuit (capacitors and
inductors). In some circuits, the order of the differential equation is less than the number of
capacitors and inductors in the circuit. This occurs when capacitor voltages and inductor currents
are not independent, that is, there is an algebraic relationship between the capacitor, specically
voltages and the inputs, or the inductor currents and the inputs. This occurs when capacitors
are connected directly to a voltage source or when inductors are connected directly to a current
source as shown in Fig. 10.2A and B. In Fig. 10.2A, two capacitors are connected directly to a
voltage source. KVL applied around the outer loop gives
v(t) +v
1
(t) +v
2
(t) = 0
or
v(t) = v
1
(t) +v
2
(t)
where v
1
(t) and v
2
(t) are the voltages across the two capacitors. It should be clear that in the
previous equation, v
1
(t) and v
2
(t) are not independent, that is, there is an algebraic relationship
P1: KDD
C1
C2
v(t)
+
v1(t)
+
v2(t)
R1
R2
i(t)
R1 R2
L1 L2
i2(t) i1(t)
C1
C2
v(t)
+
v1(t)
+
v2(t)
R1
R2
RS
i(t)
R1 R2
L1 L2
i2(t) i1(t) is(t)
Rs
A
B
C
D
FIGURE 10.2: (A), (B) Circuits described by rst-order differential equations and having algebraic
relationships between the voltages and currents. (C), (D) Circuits described by second-order differential
equations, with no algebraic relationships between voltages and currents.
between the two; if v
1
(t) is known, then v
2
(t) = v(t) v
1
(t). The same situation occurs with
two inductors connected directly to a current source as in Fig. 10.2B. KCL applied at the upper
node gives
i (t) = i
1
(t) +i
2
(t)
As before, currents i
1
(t) and i
2
(t) are not independent: there exists an algebraic relationship
between the currents. Circuits with the characteristics of Fig. 10.2A and B are rare in realistic
situations. For example, the two circuits in Fig. 10.2A and B are better described by those
in Fig. 10.2C and D since the voltage and current sources are more appropriately modeled
with a resistance within the ideal source, R
s
(called an internal resistancea small resistance
for voltage source and a large resistance for a current source). By including an internal resis-
tance R
s
in the circuit, we no longer have any algebraic relationships among the voltages and
currents.
Notice that the circuit given in Ex. 10.1 has three energy storing elements (two capacitors
and one inductor), and the resulting differential equation is of third-order, as expected.
P1: KDD
Example 10.2. Write the mesh-current equations for the circuit in Ex. 10.1 for t 0 if the
initial conditions are zero.
Solution. There are three meshes in this circuit, as shown in the following gure. To write the
mesh-current equations, recall that the voltage across a capacitor is v
C
=
1
C
t
_
0
i d +v
C
(0
+
),
where i is the resultant current (sum of mesh currents) through the capacitor, and the voltage
across a inductor v
L
= L
di
dt
where
di
dt
is the derivative of the resultant current through the
inductor. Since the initial conditions are zero, v
C
(0
+
) = 0.
v
s
(t)
C1
C2
R
2
R
1
L
1
i
1
i
2
i
3
v
s
+
1
C
1
t
_
0
(i
1
i
3
)d + R
1
(i
1
i
2
) = 0
Differentiating and rearranging the previous equation gives
R
1
di
1
dt
+
1
C
1
i
1
R
1
di
2
dt
+
1
C
1
i
3
=
dv
s
dt
R
1
(i
2
i
1
) + R
2
(i
2
i
3
) +
1
C
2
t
_
0
i
2
d = 0
(R
1
+ R
2
)
di
2
dt
+
1
C
2
i
2
R
1
di
1
dt
R
2
di
3
dt
= 0
P1: KDD
Finally, summing the voltage drops around mesh 3 gives
L
1
di
3
dt
+ R
2
(i
3
i
2
) +
1
C
1
t
_
0
(i
3
i
1
)d = 0
L
1
d
2
i
3
dt
2
+ R
2
di
3
dt
+
1
C
1
i
3
R
2
di
2
dt

1
C
1
i
1
= 0
The previous two examples involved a circuit with zero initial conditions. When circuits
involve nonzero initial conditions, our approach remains the same as before except that the
initial inductor currents are included when writing the node-voltage and the initial capacitor
voltages are included when writing the mesh-current equations.
Example10.3. Write the node equations for the following circuit for t 0 assuming the initial
conditions are i
L
1
(0) = 8 A and i
L
2
(0) = 4 A.
vs
10
1 H 2 H
1 F 2 F 3 F
1
L
i
2
L
i
Solution. With the reference node at the bottom of the circuit, we have three essential nodes
as shown in the redrawn circuit that follows.
vs
10
1 H 2 H
1 F 2 F 3 F
1
L
i
2
L
i
+
v1
+
v2
+
v3
1 2
3
P1: KDD
(v
1
v
s
)
10
+ v
1
+
t
_
0
(v
1
v
2
) d +8 = 0
where i
L
1
(0) = 8 A.
t
_
0
(v
2
v
1
)d 8 +2 v
2
+
1
2
t
_
0
(v
2
v
3
)d 4 = 0
where i
L
2
(0) = 4 A. Notice that the sign for the initial inductor current is negative because the
direction is from right to left and the current is dened on the circuit diagram in the opposite
direction for the node 2 equation.
1
2
t
_
0
(v
3
v
2
)d +4 +3 v
3
= 0
In this example, we have not simplied the node equations by differentiating to remove
the integral, which would have eliminated the initial inductor currents fromthe node-equations.
If we were to write a single differential equation involving just one node voltage and the input,
a fth-order differential equation would result because there are ve energy storing elements in
the circuit. To solve the differential equation, we would need ve initial conditions, the initial
node voltage for the variable selected, as well as the rst through fourth derivatives at time
zero.
10.1 DISCONTINUITIES ANDINITIAL
CONDITIONS INACIRCUIT
Discontinuities in voltage and current occur when an input such as a unit step is applied or a
switch is thrown in a circuit. As we have seen, when solving an nth order differential equation
one must know n initial conditions, typically the output variable and its (n 1) derivatives at
the time the input is applied or switch thrown. As we will see, if the inputs to a circuit are known
for all time, we can solve for initial conditions directly based on energy considerations and not
depend on being provided with them in the problem statement. Almost all of our problems
involve the input applied at time zero, so our discussion here is focused on time zero, but may
be easily extended to any time an input is applied.
P1: KDD
Energy cannot change instantaneously for elements that store energy. Thus, there are
no discontinuities allowed in current through an inductor or voltage across a capacitor at
any timespecically, the value of the variable remains the same at t = 0
and t = 0
+
. In
the previous problem when we were given initial conditions for the inductors and capaci-
tors, this implied, i
L
1
(0
) = i
L
1
(0
+
) and i
L
2
(0
) = i
L
2
(0
+
), and v
1
(0
) = v
1
(0
+
), v
2
(0
) =
v
2
(0
+
) and v
3
(0
) = v
3
(0
+
). With the exception of variables associated with current through
an inductor and voltage across a capacitor, other variables can have discontinuities, especially
at a time when a unit step is applied or when a switch is thrown; however, these variables must
obey KVL and KCL.
While it may not seem obvious at rst, a discontinuity is allowed for the derivative of the
current through an inductor and voltage across a capacitor at t = 0
and t = 0
+
since
di
L
(0+)
dt
=
v
L
(0+)
L
and
dv
C
(0+)
dt
=
i
C
(0+)
L
as discontinuities are allowed in v
L
(0+) and i
C
(0+). Keep in mind that the derivatives in the
previous expression are evaluated at zero after differentiation, that is
di
L
(0+)
dt
=
di
L
(t)
dt
t=0
+
and
dv
C
(0+)
dt
=
dv
C
(t)
dt
t=0
+
In calculations to determine the derivatives of variables not associated with current
through an inductor and voltage across a capacitor, the derivative of a unit step input may
be needed. Here, we assume the derivative of a unit step input is zero at t = 0
+
.
The initial conditions for variables not associated with current through an inductor and
voltage across a capacitor at times of a discontinuity are determined only from the initial
conditions from variables associated with current through an inductor and voltage across a
capacitor, and any applicable sources. The analysis is done in two steps involving KCL and
KVL or using the node-voltage or mesh-current methods.
1. First, we analyze the circuit at t = 0
. Recall that when a circuit is at steady state, an

inductor acts as a short circuit and a capacitor acts as an open circuit. Thus at steady
state at t = 0
, we replace all inductors by short circuits and capacitors by open circuits

in the circuit. We then solve for the appropriate currents and voltages in the circuit
to nd the currents through the inductors (actually the shorts connecting the sources
and resistors) and voltages across the capacitors (actually the open circuits among the
sources and resistors).
2. Second, we analyze the circuit at t = 0
+
. Since the inductor current cannot change in
going from t = 0
to t = 0
+
, we replace the inductors with current sources whose val-
ues are the currents at t = 0
. Moreover, since the capacitor voltage cannot change in

P1: KDD
going fromt = 0
to t = 0
+
, we replace the capacitors with voltage sources whose val-
ues are the voltages at t = 0
. Fromthis circuit we solve for all desired initial conditions

necessary to solve the differential equation.
Example 10.4. Find v
C
(0
), v
L
(0
), i
L
(0
), i
R
1
(0
), i
R
2
(0
), i
R
3
(0
), v
C
(0
+
), v
L
(0
+
),
i
L
(0
+
), i
R
1
(0
+
), i
R
2
(0
+
), i
R
3
(0
+
), and the derivative of each passive elements current and
voltage at t = 0
+
400 100
10 mH 500
10 V
5u(t) V
1
R
i
3
R
i
2
R
i
5 F
+
vC
+
vL
i
L
i
C
Solution. For t = 0
, the capacitor is replaced by an open circuit and the inductor by a short

circuit as shown in the following circuit.
400 100
+
vC(0 )
10 V
i
L
(0 )
1
R
i
2
R
i
3
R
i
iC
+
vL
Notice v
L
(0
) = 0 V because the inductor is a short circuit. Also note that the 500 resistor
is not shown in the circuit since it is shorted out by the inductor, and so i
R
3
(0
) = 0 A. Using
the voltage divider rule, we have
v
C
(0
) = 10
100
400 +100
= 2 V
and by Ohms law
i
L
(0
) =
10
100 +400
= 0.02 A
P1: KDD
It follows that i
R
1
(0
) = i
R
2
(0
) = i
L
(0
) = 0.02 A. Because voltage across a capacitor and

current through an inductor are not allowed to change fromt = 0
to t = 0
+
we have v
C
(0
+
) =
v
C
(0
) = 2 V and i
L
(0
) = i
L
(0
+
) = 0.02 A.
The circuit for t = 0
+
is drawn by replacing the inductors in the original circuit with
current sources whose values equal the inductor currents at t = 0
and the capacitors with

voltage sources whose values equal the capacitor voltages at t = 0
as shown in the following

gure with nodes C and L and reference. Note also that the input is now 10 +5u(t) = 15 V.
400 100
0.02 A 500
+
vL
15 V
C L
i
C
i
L
2V
2
R
i
1
R
i
+
vC
3 R
i
To nd v
L
(0
+
), we sum the currents leaving node L, yielding
v
L
2
100
+0.02 +
v
L
500
= 0
which gives v
L
(0
+
) = 0 V. Now i
R
3
(0
+
) =
v
L
(0
+
)
500
= 0 A, i
R
2
(0
+
) = 0.02 +i
R
3
(0
+
) =
0.02 A, andi
R
1
(0
+
) =
152
400
= 0.0325 A.
To nd i
C
(0
+
), we write KCL at node C, giving
i
R
1
(0
+
) +i
C
(0
+
) +i
R
2
(0
+
) = 0
or
i
C
(0
+
) = i
R
1
(0
+
) i
R
2
(0
+
) = 0.0325 0.02 = 0.125 A
To nd v
C
(0
+
), note that i
C
(0
+
) = C v
C
(0
+
) or
v
C
(0
+
) =
i
C
(0
+
)
C
=
0.0125
5 10
6
= 2.5 10
3
V/s.
Similarly,
di
L
(0
+
)
dt
=
v
L
(0
+
)
L
= 0 A/s
P1: KDD
Next we have i
R
1
=
15v
C
400
, and
di
R
1
(0
+
)
dt
=
1
400
dv
C
(0
+
)
dt
=
2.5 10
3
400
= 6.25 A/s
To nd
di
R
3
dt
we start with KCL i
R
3
= i
R
2
i
L
= i
R
1
i
C
i
L
, and
di
R
3
dt
=
di
R
1
dt

di
C
dt

di
L
dt
.
For the
di
c
dt
term we have
i
C
= i
R
1
i
R
2
and
di
C
dt
=
di
R
1
dt

di
R
2
dt
Using Ohms law, the
di
R
2
dt
term is given by as
i
R
2
=
v
C
v
L
100
and
di
R
2
dt
=
1
100
dv
C
dt

1
100
dv
L
dt
With v
L
= 500i
R
3
and
dv
L
dt
= 500
di
R
3
dt
, we have
di
R
2
dt
=
1
100
dv
C
dt

500
100
di
R
3
dt
Substituting
di
R
2
dt
into the
di
c
dt
equation gives
di
C
dt
=
di
R
1
dt

di
R
2
dt
=
di
R
1
dt

1
100
dv
C
dt
+
500
100
di
R
3
dt
Returning to the
di
R
3
dt
equation we have
di
R
3
dt
=
di
R
1
dt

di
C
dt

di
L
dt
=
di
R
1
dt

di
R
1
dt
+
1
100
dv
C
dt

500
100
di
R
3
dt

di
L
dt
Collecting the
di
R
3
dt
terms and canceling the
di
R
1
dt
terms, the previous equation reduces to
di
R
3
dt
=
1
6
_
1
100
dv
C
dt

di
L
dt
_
At t = 0
+
, we have
di
R
3
(0
+
)
dt
=
1
6
_
1
100
dv
C
(0
+
)
dt

di
L
(0
+
)
dt
_
=
1
6
_
2.5 10
3
100
0
_
= 4.167 A/s
From before, we have for
di
R
2
dt
di
R
2
(0
+
)
dt
=
1
100
dv
C
(0
+
)
dt

500
100
di
R
3
(0
+
)
dt
=
2.5 10
3
100
5 4.167 = 4.167 A/s
P1: KDD
and for
di
c
dt
di
C
(0
+
)
dt
=
di
R
1
(0
+
)
dt

di
R
2
(0
+
)
dt
= 6.25 4.1665 = 10.417 A/s
Finally, the derivatives of the voltages across the resistors are
dv
R
1
dt
= 400
di
R
1
dt
= 400 (6.25) = 2500 V/s
dv
R
2
dt
= 100
di
R
2
dt
= 100 4.167 = 416.7 V/s
and
dv
R
3
dt
= 500
di
R
3
dt
= 500 4.167 = 2083.5 V/s
C
for the circuit in Ex. 10.4 for t 0.
Solution. We use the node voltage method to solve this problemsince v
C
is one of the variables
used in the solution. Using the node-voltage method also results in two equations rather than
three equations with the mesh-current method. The initial conditions necessary to solve the
differential equation for this circuit were calculated in Ex. 10.4. Keep in mind that in Ex. 10.4,
we calculated many more initial conditions than are required in this example; here, we only need
v
C
(0
+
) and v
C
(0
+
).
For t 0, the circuit is redrawn for analysis in the following gure.
400 100
10 mH 500 5F
+
vC
+
v
L
15 V
C L
i
C
i
L
Summing the currents leaving node C gives
v
C
15
400
+5 10
6
v
C
+
v
C
v
L
100
= 0
which simplies to
v
C
+2500v
C
2000v
L
= 7500
P1: KDD
Summing the currents leaving node L gives
v
L
v
C
100
+
1
10 10
3
t
_
0
v
L
d +i
L
(0
+
) +
v
L
500
= 0
which, after multiplying by 500 and differentiating, simplies to
6 v
L
+50 10
3
v
L
5 v
C
= 0
Using the D operator method, our two differential equations are written as
Dv
C
+2500v
C
2000v
L
= 7500 or (D+2500)v
C
2000v
L
= 7500
6Dv
L
+50 10
3
v
L
5Dv
C
= 0 or (6D+50 10
3
)v
L
5Dv
C
= 0
We then solve for v
L
from the rst equation,
v
L
= (0.5 10
3
D+1.25)v
C
3.75
and then substitute v
L
into the second equation, giving
(6D+50 10
3
)v
L
5Dv
C
= (6D+50 10
3
)((0.5 10
3
D+1.25)v
C
3.750) 5Dv
C
= 0
Reducing this expression yields
D
2
v
C
+10.417 10
3
Dv
C
+20.83 10
6
v
C
= 62.5 10
6
Returning to the time domain gives
v
C
+10.417 10
3
v
C
+20.83 10
6
v
C
= 62.5 10
6
The characteristic equation for the previous differential equation is
s
2
+10.417 10
3
s +20.833 10
6
= 0
with roots 7.718 10
3
and 2.7 10
3
and the natural solution
v
C
n
(t) = K
1
e
7.71810
3
t
+ K
2
e
2.710
3
t
V
Next, we solve for the forced response, assuming that v
C
f
(t) = K
3
. After substituting into the
differential equation, this gives
20.833 10
6
K
3
= 62.5 10
6
P1: KDD
or K
3
= 3. Thus, our solution is now
v
C
(t) = v
C
n
(t) +v
C
f
(t) = K
1
e
7.71810
3
t
+ K
2
e
2.710
3
t
+3 V
We use the initial conditions to solve for K
1
and K
2
. First
v
C
(0) = 2 = K
1
+ K
2
+3
Next
v
C
(t) = 7.718 10
3
K
1
e
7.71810
3
t
2.7 10
3
K
2
e
2.710
3
t
and at t = 0,
v
C
(0) = 2.5 10
3
= 7.718 10
3
K
1
2.7 10
3
K
2
Solving gives K
1
= 0.04 and K
2
= 1.04. Substituting these values into the solution gives
v
C
(t) = 0.04e
7.71810
3
t
1.04e
2.710
3
t
+3 V
for t 0.
Our approach remains the same for circuits with controlled sources. We analyze the circuit
for t = 0
and t = 0
+
to establish the initial conditions with the controlled source operational.
If the voltage or current used in the controlled source is zero, we replace it with an open circuit
if it is a current source and a short circuit if it is a voltage source. If a circuit has an independent
voltage or current source that is introduced at zero via a unit step function, for t = 0
we replace
the independent source by a short circuit if it is a voltage source and an open circuit if it is a
current source.
Example 10.6. Find i
L
1
for the following circuit for t 0 using the mesh-current method.
10 10
1 H
10 V
5u(t) V
x
i
20
3ix
3 H
2 mF
1
L
i
P1: KDD
Solution. To solve this problem, we will use the mesh-current method with currents dened
in the following circuit. The steps involve:
1. Eliminate all currents except i
4
, which is i
L
1
, which gives a third-order differential
equation
2. Solve for the initial conditions
3. Solve the differential equation.
It should be clear that a third-order differential equation should describe this system, since there
are three energy storing elements.
Mesh Equations
To write the mesh-current equations, recall that the voltage across a capacitor is
v
C
=
1
C
_
t
0
i d +v
C
(0
+
), where i is the resultant current (sum of mesh currents) through
the inductor, and the voltage across a inductor v
L
= L
di
dt
where
di
dt
is the derivative of the
resultant current through the inductor. Since there is a controlled current source in the circuit,
we form a supermesh for meshes 1 and 2. Notice that mesh current i
4
= i
L
1
.
Summing the voltages around supermesh 1 +2 yields
15 +10(i
1
i
4
) +10(i
2
i
4
) +
d(i
2
i
3
)
dt
= 0
10 10
1 H 15 V
x
i
20
3i
x
3 H
2 mF
i
2
i
4
i
1
i
3
Rearranging the previous equation gives
10i
1
+
di
2
dt
+10i
2
di
3
dt
20i
4
= 15
P1: KDD
Summing the voltage drops around mesh 3 yields
d(i
2
i
3
)
dt
+20(i
3
i
4
) +
1
2 10
3
t
_
0
i
3
d +v
C
(0
+
) = 0
Differentiating and rearranging the previous equation reduces to
d
2
i
2
dt
2
+
d
2
i
3
dt
2
+20
di
3
dt
+500i
3
20
di
4
dt
= 0
3
di
4
dt
+20(i
4
i
3
) +10(i
4
i
2
) +10(i
4
i
1
) = 0
and after rearranging, we nd
10i
1
10i
2
20i
3
+3
di
4
dt
+40i
4
= 0
Applying KCL for the dependent current source gives
3i
x
= i
2
i
1
Since i
x
= 3(i
1
i
4
), we have
4i
1
i
2
3i
4
= 0
At this time, we have four equations and four unknowns. The dependent current source equa-
tion, an algebraic equation, is used to eliminate i
1
from the three mesh equations, since i
1
=
1
4
(i
2
+3i
4
). Substituting i
1
into the supermesh 1 +2 equation and collecting like terms gives
di
2
dt
+
50
4
i
2
di
3
dt

50
4
i
4
= 15
The mesh 3 equation did not have an i
1
, but is written here for convenience.
d
2
i
2
dt
2
+
d
2
i
3
dt
2
+20
di
3
dt
+500i
3
20
di
4
dt
= 0
After substituting i
1
and collecting like terms in the mesh 4 equation, we have
50
4
i
2
20i
3
+3
di
4
dt
+
130
4
i
4
= 0
P1: KDD
The mesh 4 equation is used to eliminate i
3
from the other two equations. Solving for i
3
and
taking its derivatives yields
i
3
=
1
20
_
50
4
i
2
+3
di
4
dt
+
130
4
i
4
_
di
3
dt
=
1
20
_
50
4
di
2
dt
+3
d
2
i
4
dt
2
+
130
4
di
4
dt
_
d
2
i
3
dt
2
=
1
20
_
50
4
d
2
i
2
dt
2
+3
d
3
i
4
dt
3
+
130
4
d
2
i
4
dt
2
_
Substituting the
di
3
dt
term into the supermesh 1 +2 equation and simplifying gives
13
8
di
2
dt
+
50
4
i
2
3
20
d
2
i
4
dt
2

13
8
di
4
dt

50
4
i
4
= 15
Substituting i
3
,
di
3
dt
and
d
2
i
3
dt
2
into the mesh 3 equation after collecting like terms gives
13
8
d
2
i
2
dt
2

50
4
di
2
dt
312.5i
2
+
3
20
d
3
i
4
dt
3
+
37
8
d
2
i
4
dt
2
+
350
4
di
4
dt
+812.5i
4
= 0
To eliminate i
2
, we use the D operator method on our two differential equations giving
_
13
8
D+
50
4
_
i
2
+
_
3
20
D
2
13
8
D
50
4
_
i
4
= 15
_
13
8
D
2
50
4
D312.5
_
i
2
+
_
3
20
D
3
+
37
8
D
2
+
350
4
D+812.5
_
i
4
= 0
To solve for i
4
, we pre-multiply the rst equation by (
13
8
D
2
50
4
D312.5), pre-multiply the
second equation by (
13
8
D+
50
4
), and then subtract the rst equation from the second equation.
This yields
(4.875D
3
+112.5D
2
+1750D+6250)i
4
= (
13
8
D
2
50
4
D312.5) 15
Returning to the time domain gives
4.875
d
3
i
4
dt
3
+112.5
d
2
i
4
dt
2
+1750
di
4
dt
+6250i
4
= 4687.5
P1: KDD
Note that the derivative terms on the right-hand side of the D operator equation are zero since
the derivative of a constant is zero. Dividing the previous differential equation by 4.875 to put
it in a more convenient form results in
d
3
i
4
dt
3
+23.1
d
2
i
4
dt
2
+359
di
4
dt
+6250i
4
= 1282.1
Initial Conditions
The next step in the solution involves nding the initial conditions for the circuit necessary to
solve the differential equation, i
L
1
(0
+
),
di
L
1
(0
+
)
dt
and
d
2
i
L
1
(0
+
)
dt
2
. As before, this involves:
1. Analyzing the circuit at t = 0
with the inductors replaced as short circuits and the

capacitor as an open circuit
2. Analyzing the circuit at t = 0
+
with inductors replaced as current sources whose values
equal the inductor currents at t = 0
and the capacitor as a voltage source whose value

equal the capacitor voltage at t = 0
.
For t = 0
, for a node-voltage solution the circuit is redrawn as shown in the following diagram.
10 10
10 V
20
3i
x
1
L
i
vC
+
2
L
i
x
i 4
x
i
+
v1
+
1
v
1
10
10
3
_
10 v
1
10
_
+
v
1
10
= 0
where i
x
=
10v
1
10
. Solving this equation yields v
1
(0
) = 8 V. Ohms law gives i

L
1
(0
) =
10
20
= 0.5 Aand i
x
(0
) =
10v
1
(0
)
10
=
108
10
= 0.2 A. Since the capacitor is connected across the
battery, v
C
(0
) = 10 V. KCL gives the current through the other inductor as i

L
2
(0
) =
4i
x
(0
) +i
L
1
(0
) = 0.8 +0.5 = 1.3 A.

P1: KDD
For t = 0
+
, for a node-voltage solution the circuit is redrawn as shown in the following
diagram.
10 10
15 V
20
3i
x
1
0 0 5 ( ) .
L
i A
+
=
2
0
1 3 A
( )
.
L
i
+
=
x
i
+
v
1
1 2
+
v
2
0
10 V
( )
C
v
+
=
1
L
v
+
iC
To nd the initial conditions for the circuit at t = 0
+
, we rst solve for the node-voltages
v
1
(0
+
) and v
2
(0
+
) and then solve for
di
L
1
(0
+
)
dt
and
d
2
i
L
1
(0
+
)
dt
2
. Summing the currents leaving node
1 yields
v
1
15
10
3
_
15 v
1
10
_
+
v
1
v
2
10
= 0
Simplifying the equation, yields
5v
1
v
2
= 60
Summing the currents leaving node 2 yields
v
2
v
1
10
+1.3 +
v
2
10
20
= 0
Simplifying the equation, we have
2v
1
+3v
2
= 16
Solving the two simultaneous node equations gives
v
1
(0
+
) = 12.6154 and v
2
0
+
) = 3.0769.
Recall that v
C
(0
+
) = v
C
(0
) = 10 V, i
L
1
(0
+
) = i
L
1
(0
) = 0.5 A, and i
L
2
(0
+
) = i
L
2
(0
) =
1.3 A from the analysis at t = 0
.
P1: KDD
Our next tasks involve nding
di
L
1
(0
+
)
dt
and
d
2
i
L
1
(0
+
)
dt
2
using the relationships v
L
= L
1
di
L
1
dt
and i
C
= C
dv
C
dt
. Thus
di
L
1
(0
+
)
dt
=
1
3
v
L
1
(0
+
)
and using KVL to nd v
L
1
(0
+
) gives
15 +v
L
1
(0
+
) +v
C
(0
+
) = 0
or
v
L
1
(0
+
) = 15 v
C
(0
+
) = 15 10 = 5 V
and
di
L
1
(0
+
)
dt
=
1
3
v
L
1
(0
+
) =
5
3
A
s
We also have
d
2
i
L
1
(0
+
)
dt
2
=
1
3
dv
L
1
(0
+
)
dt
, and from KVL before v
L
1
= 15 v
C
and after differentiat-
ing
dv
L
1
dt
= 0
dv
C
dt
=
dv
C
dt
. Thus
d
2
i
L
1
(0
+
)
dt
2
=
1
3
dv
L
1
(0
+
)
dt
=
1
3
dv
C
(0
+
)
dt
. Now
i
C
(0
+
) =
v
2
(0
+
) 10
20
+i
L
1
(0
+
) =
3.0796 10
20
+0.5 = 0.154 A
and
dv
C
(0
+
)
dt
=
1
C
i
C
(0
+
) =
1000
2
0.154 = 77 V/s
Therefore
d
2
i
L
1
(0
+
)
dt
2
=
1
3
dv
C
(0
+
)
dt
= 25.6667 A
2
/s.
Solving the Differential Equation
The differential equation describing the circuit is
d
3
i
4
dt
3
+23.1
d
2
i
4
dt
2
+359
di
4
dt
+6250i
4
= 1282.1
As before, the natural solution is determined rst by nding the roots of characteristic equation,
s
3
+23.1s
2
+359s +6250
as s
1
= 20.4749, s
2,3
= 1.3125 j 17.4221. The roots give rise to the natural response
i
4
n
(t) = K
1
e
20.4749t
+e
1.3125t
(K
2
cos(17.4221t) + K
3
sin(17.4221t))
P1: KDD
Next we solve for the forced response to the input by assuming
i
4
f
(t) = K
4
which, when substituted into the original differential equation, yields
6250K
4
= 1281.1
giving K
4
= 0.2050. The total solution equals the natural and forced response, written as
i
4
(t) = i
4
n
(t) +i
4
f
(t)
= K
1
e
20.4749t
+e
1.3125t
(K
2
cos(17.4221t) + K
3
sin(17.4221t)) +0.2050
The initial conditions are used to determine the constants K
1
, K
2
and K
3
. From the solution
for i
4
(t), we have
i
4
(0) =
1
2
= K
1
+ K
2
+0.2050
To use the next initial condition, we nd the derivative of the solution, giving
di
4
dt
= 20.4749K
1
e
20.4749t
1.3125e
1.3125t
(K
2
cos(17.4221t) + K
3
sin(17.4221t))
+e
1.3125t
(17.4221K
2
sin(17.4221t) +17.4221K
3
cos(17.4221t))
We evaluate this expression at t = 0, giving
di
4
(0)
dt
=
5
3
= 20.4749K
1
1.3125K
2
+17.4221K
3
Finally, we take the second derivative of the solution giving
d
2
i
4
dt
2
= 419.2215K
1
e
20.4749t
+1.7227e
1.3125t
(K
2
cos(17.4221t) + K
3
sin(17.4221t))
1.3125e
1.3125t
(17.4221K
2
sin(17.4221t) +17.4221K
3
cos(17.4221t))
1.3125e
1.3125t
(17.4221K
2
sin(17.4221t) +17.4221K
3
cos(17.4221t))
+e
1.3125t
(303.5296K
2
cos(17.4221t) 303.5296K
3
sin(17.4221t))
We evaluate this expression at t = 0, giving
d
2
i
4
(0)
dt
2
= 25.6667 = 419.2215K
1
+1.7227K
2
2.6250 17.4221K
3
303.5296K
2
= 419.2215K
1
301.807K
2
45.733K
3
P1: KDD
The three initial condition equations are put into matrix form for a straightforward solution as
AK = F or
_
_
_
_
1 1 0
20.4749 1.3125 17.4221
419.2215 301.807 45.733
_
_
_
_
_
_
K
1
K
2
K
3
_
_
=
_
_
_
_
_
0.295
5
3
25.6667
_
_
Using MATLAB, we have
A = [1 1 0; 20.4749 1.3125 17.4221; 419.2215 301.807 45.733];
F = [0.295; 5/3; 25.6667];
K = A\F
K =
0.1025
0.1925
0.2306
The complete solution is
i
L
1
(t) = i
4
(t) = 0.1025e
20.4749t
+e
1.3125t
(0.1925 cos(17.4221t)
+0.2306 sin(17.4221t)) +0.2050
for t 0.
10.2 CIRCUITS WITHSWITCHES
To nish this section, we consider circuits with multiple switches. In effect, each time a switch
is thrown, we solve the circuit using the techniques of this section. That is, at each switch time,
t
i
, we determine the necessary voltages and currents at t
i
and t
+
i
and solve the circuit problem,
move to the next switch time, determine the necessary voltages and currents at t
i +1
and t
+
i +1
and solve the circuit problem, and so on. For ease in solving the circuit after the rst switch
time at t = 0, we replace the variable t with t t
1
where t
1
is the switch time and use the unit
step function, and repeat this substitution at each switch time. Each time interval is separately
analyzed, with the only carry-over from one time interval to the next being the voltages across
the capacitor and currents through the inductors at the switch time. The next example illustrates
this approach.
P1: KDD
C
for the following circuit for t 0.
10
0.03 F 50 2 A 40 H
1
3
+
v
c
t = 1 s
t = 0
t = 4 s
Solution. There are two switches operating in this circuit, with switching times at t = 0, t =
1 and t = 4 s . We therefore break up the solution into three time intervals, 0 t < 1, 1 t <
4 and t 4 s, while realizing that we need to know the initial conditions just before and after
each switch time, and that we also need to solve for the steady-state solution for t < 0.
For t < 0
At steady state, the capacitor is replaced by an open circuit as shown in the following gure.
10
50 2 A 40
+
v
c
Using the current divider rule and Ohms law, we have v

C
(0
) = 40 V. Note that voltage cannot

instantaneously change across a capacitor, so v
C
(0
+
) = 40 V.
For 0 t < 1
During this interval, the switch on the left opens, leaving us with the following circuit to analyze.
40
+
v
c
0.03 F
P1: KDD
Notice the 10 resistor is eliminated since no current ows through it because it is an open
circuit. Using KCL we have
0.03 v
C
+
v
C
40
= 0
The differential equation has a root equal to
1
1.2
and a solution in this time interval of
v
C
= v
C
(0
+
)e
t
1.2
u(t) = 40e
t
1.2
u(t) V
For 1 t < 4
When t = 1, the switch on the right closes, introducing an inductor as shown in the following
gure.
40
+
vc
0.03 F H
1
3
i
L
i
R
i
C
Applying KCL yields
0.03
dv
C
dt
+
v
C
40
+5
t
_
1
v
C
d +i
L
(1
+
) = 0
Dividing the previous equation by 0.03 and differentiating gives
v
C
+
1
1.2
v
C
+
5
0.03
v
C
= 0
with complex roots determined from MATLAB as 0.42 12.9 j . The solution consists of
the natural solution only, since the forced response is zero, and is given by
v
C
= e
0.42(t1)
(K
1
cos(12.9(t 1)) + K
2
sin(12.9(t 1))) (u(t 1) u(t 4))
This solution requires two initial conditions. Recall that at t = 1, v
C
(1
+
) = v
C
(1
) and
i
L
(1
+
) = i
L
(1
). Moreover, all other voltages and currents and their derivatives change from
t = 1
to t = 1
+
s. Now using the solution for v
C
from the previous interval, we have
v
C
(1
+
) = v
C
(1
) = 40e
1
1.2
= 17.4 V
P1: KDD
From our solution in this interval, we have
v
C
(1
+
) = K
1
= 17.4 V
Since no current was owing through the inductor during the interval 0 t < 1, i
L
(1
+
) =
i
L
(1
) = 0 A. Now i
R
(1
+
) =
v
C
(1
+
)
40
=
17.4
40
= 0.44 A, and accordingly
i
C
(1
+
) = (i
L
(1
+
) +i
R
(1
+
)) = (0 +0.44) = 0.44 A
v
C
(1
+
) =
1
C
i
C
(1
+
) = 14.5 V
Now
v
C
=
_
_
0.42e
0.42(t1)
(K
1
cos(12.9(t 1)) + K
2
sin(12.9(t 1)))
+e
0.42(t1)
(12.9K
1
sin(12.9(t 1)) +12.9K
2
cos(12.9(t 1)))
_
_
(u (t 1) u (t 4))
and
v
C
(1
+
) = 14.5 = 0.42K
1
+12.9K
2
= 0.42 17.4 +12.9K
2
which gives K
2
= 0.557. Our complete solution is
v
C
= e
0.42(t1)
(17.4 cos(12.9(t 1)) 0.557 sin(12.9(t 1)))(u(t 1) u(t 4)) V
For t > 4.
For the last interval, the switch on the left closes, giving us the following gure to analyze.
10
0.03 F 50 2 A 40
+
v
c
i
L
H
1
5
To ease the solution, the 2 A current source with 50 resistor is transformed into a 100 V
voltage source in series with a 50 resistor. The 50 and 10 resistors are summed together,
and the 100 V voltage source and 60 resistor are transformed into a
10
6
A current source in
parallel with a 60 resistor. The 60 and 40 resistors are combined to give a 24 resistor.
The reduced circuit is shown in the following circuit.
P1: KDD
0.03 F 25
+
v
c
A
10
6
H
1
5
i
L
Applying KCL gives
10
6
+
v
C
24
+0.03 v
C
+5
t
_
1
v
C
d +i
L
(4
+
) = 0
Differentiating the previous equation and dividing by 0.03 yields
v
C
+1.4 v
C
+166.7v
C
= 55.6
with roots determined from MatLab as 0.7 12.9 j . The roots are complex, which gives rise
to the natural response
v
C
= e
0.7(t4)
(K
1
cos(12.9(t 4)) + K
2
sin(12.9(t 4))) u(t 4)
Next, we solve for the forced response to the input by assuming y
f
(t) = K
3
. When substituted
into the differential equation describing this interval, this yields
166.7K
3
= 55.6
giving 11.1. The total solution in this interval equals the natural and forced response, written
as
v
C
= 11.1 +e
0.7(t4)
(K
1
cos(12.9(t 4)) + K
2
sin(12.9(t 4))) u(t 4)
Two initial conditions (v
C
(4
+
) and v
C
(4
+
)) are needed to determine the constants K
1
and K
2
.
As before, at t = 4, v
C
(4
+
) = v
C
(4
) and i
L
(4
+
) = i
L
(4
), and all other voltages and currents

andtheir derivatives change fromt = 4
to t = 4
+
s. Using the solutionfor v
C
fromthe previous
interval, we have
v
C
(4
+
) = v
C
(4
) = e
0.42(t1)
(17.4 cos(12.9(t 1)) 0.557 sin(12.9(t 1)))
(u(t 1) u(t 4))|
t=4
= e
0.42(41)
(17.4 cos (12.9 (4 1)) 0.557 sin (12.9 (4 1)))
= 2.5 V
P1: KDD
From our solution in this interval, we have
v
C
(4
+
) = 11.1 + K
1
= 2.53 V
and K
1
= 8.6 V. The next initial condition, v
C
(4
+
) =
1
0.03
i
C
(4
+
), is determined from KCL
10
6
+
v
C
(4
+
)
24
+i
C
(4
+
) +i
L
(4
+
) = 0
where i
L
(4
+
) = i
L
(4
). To nd i
L
(4
) we use the solution for v

C
in the previous interval and
compute
i
L
(4
+
) = i
L
(4
) = 5
4
_
1
v
C
dt +i
L
(1
+
) = 5
4
_
1
v
C
dt +0
= 5
4
_
1
(e
0.42(t1)
(17.4 cos(12.9(t 1)) 0.557 sin(12.9(t 1)))) dt
= e
0.42(t1)
(0.0037 cos(12.9(t 1)) +6.74 sin(12.9(t 1)))
4
1
= 1.614 A
Now i
R
(1
+
) =
v
C
(4
+
)
24
=
2.53
24
= 0.105 A, and
i
C
(4
+
) =
10
6

v
C
(4
+
)
24
i
L
(4
+
) =
10
6

2.53
24
1.614 = 0.05 A
v
C
(4
+
) =
1
C
i
C
(4
+
) = 1.75 V
Now
v
C
=
_
0.7e
0.7(t4)
(K
1
cos(12.9(t 4)) + K
2
sin(12.9(t 4)))
+e
0.7(t4)
(12.9K
1
sin(12.9 (t 4)) +12.9K
2
cos (12.9 (t 4)))
_
u (t 4)
and
v
C
(4
+
) = 1.75 = 0.7K
1
+12.9K
2
with K
1
= 8.6, we have K
2
= 0.6. Our solution for this interval is
v
C
= 11.1 +e
0.7(t4)
(8.6 cos(12.9(t 4)) 0.6 sin(12.9(t 4))) u(t 4) V
P1: KDD
Summarizing, our complete solution is
v
C
=
_
_
40e
t
1.2
V 0 t < 1
e
0.42(t1)
(17.4 cos(12.9 (t 1)) 0.557 sin(12.9 (t 1))) V 1 t < 4
11.1 +e
0.7(t4)
(8.6 cos(12.9(t 4)) 0.6 sin(12.9(t 4))) V t 4
P1: KDD
118
P1: KDD
119
C H A P T E R 1 1
Operational Ampliers
In Section 3, we considered controlled voltage and current sources that are dependent on a
voltage or current elsewhere in a circuit. These devices were modeled as a two terminal device.
Here we consider the operational amplier, also known as an op amp, a multi-terminal device.
An operational amplier is an electronic device that consists of large numbers of transistors,
resistors and capacitorsto fully understand its operation requires knowledge of diodes and
transistors, topics not covered in this book. However, to appreciate howan operational amplier
operates in a circuit involves a topic already covered, the controlled voltage source.
As the name implies, the operation amplier is an amplier, but when combined with
other circuit element, it integrates, differentiates, sums and subtracts. One of the rst opera-
tional ampliers approved as an eight-lead dual-in-line package (DIP) is shown in Fig. 11.1.
Differing from previous circuit elements, this device has two inputs and one output terminals.
Rather than draw the operational amplier using Fig 11.1, the operational amplier is drawn
with the symbols in Fig. 11.2. The input terminals are labeled the noninverting input (+)
and the inverting input (). The power supply terminals are labeled V+ and V, which are
frequently omitted since they do not affect the circuit behavior except in saturation condi-
tions as will be described. Most people shorten the name of the operational amplier to the
op amp.
Illustrated in Fig. 11.3 is a model of the op amp focusing on the internal behavior of the
input and output terminals. The inputoutput relationship is
v
o
= A(v
p
v
n
) (11.1)
Since the internal resistance is very large, we will replace it with an open circuit to simplify
analysis leaving us with the op amp model show in Fig. 11.4.
With the replacement of the internal resistance with an open circuit, the currents i
n
=
i
p
= 0 A. In addition, current i
A
, the current owing out of the op amp, is not zero. Because i
A
is unknown, we seldom apply KCL at the output junction. In solving op amp problems, KCL
is applied at input terminals.
P1: KDD
NC
V+
Output
Offset null
Offset null
Inverting
input
Noninverting
input
V
Eight
terminal
operational
amplifier
FIGURE11.1: An eight-terminal operational amplier. The terminal NCis not connected, and the two
terminal offset nulls are used to correct imperfections (typically not connected). V
+
and V
are terminal
power to provide to the circuit. Keep in mind that a ground exists for both V
+
and V
, a ground that is
shared by other elements in the circuit. Modern operational ampliers have ten or more terminals.
V
+
Inverting
input
Noninverting
input
V
Output
FIGURE11.2: Circuit element symbol for the operational amplier.
R
i
p
i
n
i
A
v
n
vp
v
o
A (vp vn)
FIGURE11.3: An internal model of the op amp. The internal resistance between the input terminals,
R, is very large exceeding 1 M. The gain of the amplier, A, is also large exceeding 10
4
. Power supply
terminals are omitted for simplicity.
P1: KDD
OPERATIONAL AMPLIFIERS 121
i
p
i
n
i
A
v
n
v
p
v
o
= A (vp vn)
FIGURE 11.4: Idealized model of the op amp with the internal resistance, R, replaced by an open
circuit.
0
R1
R
2
i
2
V
S
i
1
v
0
v
n
v
p

Solution. Using the op amp model of Fig. 11.4, we apply KCL at the inverting terminal
giving
i
1
i
2
= 0
since no current ows into the op amps input terminals. Replacing the current using Ohms
law gives
v
s
v
1
R
1
+
v
o
v
1
R
2
= 0
Multiplying by R
1
R
2
and collecting like terms, we have
R
2
v
s
= (R
1
+ R
2
) v
1
R
1
v
o
Now v
o
= A
v
p
v
n
and since the noninverting terminal is connected to ground, v

p
= 0 so
v
o
= Av
n
P1: KDD
or
v
n
=
v
o
A
Substituting v
n
into the KCL inverting input equation gives,
R
s
v
s
= (R
1
+ R
2
)
v
o
A
R
1
v
o
=
R
1
+ R
2
A
+ R
1
v
o
or
v
o
=
R
2
v
s
R
1
+
R
1
+ R
2
A
As A goes to innity, the previous equation goes to

v
o
=
R
2
R
1
v
s
Interestingly, with A going to innity, v
0
remains nite due to the resistor R
2
. This happens
because a negative feedback path exists between the output and the inverting input terminal
through R
2
. This circuit is called an inverting amplier with an overall gain of
R
2
R
1
.
An operational amplier with a gain of innity is known as an ideal op amp. Because of
the innite gain, there must be a feedback path between the output and input and we cannot
connect a voltage source directly between the inverting and noninverting input terminals. When
analyzing an ideal op amp circuit, we simplify the analysis by letting
v
n
= v
p
Consider the previous example. With v
p
= 0 means v
n
= 0. Applying KCL at the inverting
input gives
v
s
R
1
+
v
o
R
2
= 0
or
v
o
=
R
2
R
1
v
s
Notice how simple the analysis becomes when we assume v
n
= v
p
. Keep in mind that this
approximation is valid as long as A is very large (innity) and a feedback is included.
P1: KDD
Example 11.2. Find the overall gain for the following circuit.
R
1
R2
i
1
i
2
V
S
v
p
v
0
v
n
Solution. Assuming the op amp is ideal, we start with v
n
= v
p
. Then since the op amps
noninverting terminal is connected to the source, v
n
= v
p
= v
s
. Because no current ows into
the op amp, by KCL we have
i
1
+i
2
= 0
and
v
s
R
1
+
v
s
v
o
R
2
= 0
or
v
o
=
R
1
+ R
2
R
1
v
s
The overall gain is
v
o
v
s
=
R
1
+ R
2
R
1
This circuit is a noninverting op amp circuit used to amplify the source input. Ampliers are
used in most all clinical instrumentation from ECK, EEG, EOG, etc.
P1: KDD
The next example describes a summing op amp circuit.
R
a
R
2
R
b
V
a
V
b
vn
vp
v
0

Solution. As before we start the solution with v
n
= v
p
and note that the noninverting input is
connected to ground, yielding v
n
= v
p
= 0 V. Applying KCL at the inverting input node gives
V
a
R
a
V
b
R
b
v
o
R
2
= 0
or
v
o
=
R
2
R
a
V
a
+
R
2
R
b
V
b
We can add additional source resistor inputs, so that in general

v
o
=
R
2
R
a
V
a
+
R
2
R
b
V
b
+ +
R
2
R
m
V
m
Our next op amp circuit provides an output proportional to the difference of two input
voltages. This op amp is often referred to as a differential amplier.
Solution. Assuming an ideal op amp, we note no current ows into the input terminals and
that v
n
= v
p
. Apply KCL at the inverting input terminal gives
v
n
V
a
R
1
+
v
n
v
o
R
2
= 0
P1: KDD
R2
R1
R1
i2
R2
ia
ib
V
b
V
a
v
p
vn
v0
and
(R
1
+ R
2
)v
n
R
2
V
a
= R
1
v
o
The previous equation involves two unknowns, thus we need another equation easily found by
applying voltage divider at the noninverting input.
v
p
=
R
2
R
1
+ R
2
v
b
= v
n
Substituting this result for v
n
into the KCL equation at the inverting terminal gives
R
2
V
b
R
2
V
a
= R
1
v
o
or
v
o
=
R
2
R
1
(V
b
V
a
)
As shown, this op amp circuit, also known as the differential amplier, subtracts the weighted
input signals. This amplier is used for bipolar measurements involving ECG and EEG as the
typical recording is obtained between two bipolar input terminals. Ideally, the measurement
contains only the signal of interest uncontaminated by noise from the environment. The noise
is typically called common-mode signal. Common-mode signal comes from lighting, 60-Hz
power line signals, inadequate grounding and power supply leakage. A differential amplier
with appropriate ltering can reduce the impact of the common-mode signal.
P1: KDD
The response of a differential amplier can be decomposed into differential-mode and
common-mode components,
v
dm
= v
b
v
a
and
v
c m
=
(v
a
+v
b
)
2
As described, the common-mode signal is the average of the input voltages. Using the two
previous equations, one can solve v
a
and v
b
in terms of v
dm
and v
c m
as
v
a
= v
c m
v
dm
2
and
v
b
= v
c m
+
v
dm
2
When substituted into the response in Exercise 44 gives
v
0
=
R
1
R
2
R
1
R
2
R
1
(R
1
+ R
2
)
v
c m
+
R
2
(R
1
+ R
2
) + R
2
(R
1
+ R
2
)
2R
1
(R
1
+ R
2
)
v
dm
= A
c m
v
c m
+ A
dm
v
dm
Notice the term multiplying, v
c m
, A
c m
, is zero, characteristic of the ideal op amp that amplies
only the differential-mode of the signal. Since real ampliers are not ideal and resistors are not
truly exact, the common-mode gain is not zero. So when one designs a differential amplier,
the goal is to keep A
c m
as small as possible and A
dm
as large as possible.
The rejection of the common-mode signal is called common-mode rejection, and the mea-
sure of how ideal the differential amplier is called the common-mode rejection ratio, given as
CMRR = 20 log
10
A
dm
A
c m
where the larger the value of CMRR the better. Values of CMRR for a differential amplier for
EEG, ECG, and EMG is 100120 db.
The general approach to solving op amp circuits is to rst assume that the op amp is
ideal and v
p
= v
n
. Next, we apply KCL or KVL at the two input terminals. In more complex
circuits, we continue to apply our circuit analysis tools to solve the problem as the next example
illustrates.
P1: KDD
0
R
2
R
2
R
2
R
1
1
v
0
v
1
V
S
v
p
v
n
Solution. With v
n
= v
p
, we apply KCL at the inverting input
v
n
v
1
R
2
+
v
n
v
o
R
2
= 0
and
2v
n
v
1
v
o
= 0
Next, we apply KVL from ground to node 1 to the noninverting input and back to ground
giving
v
1
V
s
+v
p
= 0
and with v
n
= v
p
we have v
n
v
1
= V
s
.
Now, we apply KCL at node 1, noting no current ows into the noninverting input
terminal
v
1
R
1
+
v
1
v
o
R
2
+
v
1
v
n
R
2
= 0
Combining like terms in the previous equation gives
R
1
v
n
+(2R
1
+ R
2
)v
1
R
1
v
o
= 0
P1: KDD
With three equations and three unknowns, we rst eliminate v
1
by subtracting the inverting
input KCL equation by the KVL equation giving
v
1
= v
o
2V
s
Next, we eliminate v
n
by substituting v
1
into the inverting input KCL equation as follows
v
n
=
1
2
(v
1
+v
o
)
=
1
2
(v
o
2V
s
+v
o
)
= v
o
V
s
Finally, we substitute the solutions for v
1
and v
n
into the node 1 KCL equation giving
R
1
v
n
+(2R
1
+ R
2
)v
1
R
1
v
o
= 0
R
1
(v
o
V
s
) +(2R
1
+ R
2
)(v
o
2V
s
) R
1
v
o
= 0
After simplication, we have
v
o
=
(3R
1
+2R
2
)
R
2
V
s
The next two examples illustrate an op amp circuit that differentiates and integrates by using a
capacitor.
0
V
S
C
R
i
R
+ v
C
i
C
v
0
v
p
v
n
P1: KDD
Solution. With the noninverting input connected to ground, we have v
p
= 0 = v
n
. From
KVL
v
C
= V
s
and it follows that
i
C
= C
dv
C
dt
= C
dV
s
dt
Since no current ows into the op amp, i
C
= i
R
. With
i
R
=
v
n
v
o
R
=
v
o
R
and
i
C
= C
dV
s
dt
= i
R
=
v
o
R
we have
v
o
= RC
dV
s
dt
If R =
1
C
, the circuit in this example differentiates the input, v
o
=
dV
s
dt
.
0
V
S
C
i
R
+ v
C
i
C
v0
v
p
v
n
R
Solution. It follows that
v
n
= v
p
= 0
P1: KDD
and
i
C
= i
R
=
V
s
R
Therefore
v
C
=
1
C
t
i
C
d =
1
C
t
V
s
R
d
From KVL, we have
v
C
+v
o
= 0
and
v
o
=
1
RC
t
V
s
d
With R =
1
C
, the circuit operates as an integrator
v
o
=
t
V
s
d
11.1 VOLTAGECHARACTERISTICS OF THEOP AMP
In the past examples involving the op amp, we have neglected to consider the supply voltage
(shown in Fig. 11.2) and that the output voltage of an ideal op amp is constrained to operate
between the supply voltages V
+
and V
. If analysis determines v
0
is greater than V
+
, v
0
saturates at V
+
. If analysis determines v
0
is less than V
, v
0
saturates at V
. The output
voltage characteristics are shown in Fig. 11.5.
V+
V+
V
V
v
0
A(vp vn)
FIGURE11.5: Voltage characteristics of an op amp.
P1: KDD
Example 11.8. For the circuit shown in Ex. 11.5, let V
+
= +10 V and V
= 10 V. Graph
the output voltage characteristics of the circuit.
Solution. The solution for Ex. 11.5 is
v
o
=
3R
1
+2R
2
R
2
V
s
which saturates whenever v
0
is less than V
and greater than V

+
as shown in the following
graph.
V+
V
v0
V
S
2
3R
1
+ 2R
2
slope is
R
P1: KDD
132
P1: KDD
133
C H A P T E R 1 2
Time-Varying Signals
An alternating current (AC) or sinusoidal source of 50 or 60 Hz is common throughout the
world as a power source supplying energy for most equipment and other devices. While most
of this chapter has focused on the transient response; when dealing with sinusoidal sources,
attention is now focused on the steady-state or forced response. In bioinstrumentation, analysis
in the steady state simplies the design by focusing only on the steady-state response, which is
where the device actually operates. A sinusoidal voltage source is a time-varying signal given by
v
s
= V
m
cos(t +) (12.1)
where the voltage is dened by angular frequency ( in radians/s), phase angle ( in radians
or degrees), and peak magnitude (V
m
). The period of the sinusoid T is related to frequency
f (Hz or cycles/s) and angular frequency by
= 2f =
2
T
(12.2)
An important metric of a sinusoid is its rms value (square root of the mean value of the squared
function), given by
V
r ms
=
1
T
T
0
V
2
m
cos
2
(t +)dt (12.3)
which reduces to V
r ms
=
V
m
2
.
To appreciate the response to a time-varying input, v
s
= V
m
cos(t +), consider the
circuit shown in Fig. 12.1 in which the switch is closed at t = 0 and there is no initial energy
stored in the inductor.
Applying KVL to the circuit gives
L
di
dt
+iR = V
m
cos(t +)
P1: KDD
t = 0
v
s
R
L
i
FIGURE12.1: A RL circuit with sinusoidal input.
and after some work, the solution is
i = i
n
+i
f
=
V
m
R
2
+
2
L
2
cos

L
R
R
L
t
+
V
m
R
2
+
2
L
2
cos
t +
L
R
The rst term is the natural response that goes to zero as t goes to innity. The second term is
the forced response that has the same form as the input (i.e., a sinusoid with the same frequency
, but a different phase angle and maximum amplitude). If all you are interested in is the
steady-state response as in most bioinstrumentation applications, then the only unknowns are
the response amplitude and phase angle. The remainder of this section deals with techniques
involving the phasor to efciently nd these unknowns.
12.1 PHASORS
The phasor is a complex number that contains amplitude and phase angle information of a
sinusoid, and for the signal in Eq. (12.1) is expressed as
V = V
m
e
j
= V
m
(12.4)
In Eq. (12.1), by practice, the angle in the exponential is written in radians, and in the

notation, in degrees. Work in the phasor domain involves the use of complex algebra in moving
between the time and phasor domain, therefore, the rectangular form of the phasor is also used,
given as
V = V
m
(cos + j sin ) (12.5)
P1: KDD
TIME-VARYINGSIGNALS 135
12.2 PASSIVECIRCUITELEMENTS INTHEPHASORDOMAIN
To use phasors with passive circuit elements for steady-state solutions, the relationship between
voltage and current is needed for the resistor, inductor and capacitor. Assume that
i = I
m
cos(t +)
I = I
m
| = I
m
e
j
For a resistor,
v = I R = RI
m
cos(t +)
and the phasor of v is
V = RI
m
| = RI (12.6)
Note that there is no phase shift for the relationship between the phasor current and voltage
for a resistor.
For an inductor,
v = L
di
dt
= LI
m
sin(t +) = LI
m
cos(t + 90
)
and the phasor of v is
V = LI
m
| 90
= LI
m
e
j (90
)
= LI
m
e
j
e
j 90
= LI
m
e
j
(j )
= j LI
m
e
j
(12.7)
= j LI
Note that inductor current and voltage are out of phase by 90
, that is current lags behind

voltage by 90
.
For a capacitor, dene v = V
m
cos(t +) and V = V
m
| . Now
i = C
dv
dt
= C
d
dt
(V
m
cos(t +))
= CV
m
sin(t +) = CV
m
cos(t + 90
)
And the phasor for i is
I = CV
m
| 90
= CV
m
e
j
e
j 90
= CV
m
e
j
(cos(90
) j sin(90
))
= j CV
m
e
j
= j C V
P1: KDD
200 mH
i
100 sin 500 t mV
s
v =
0.5 F
1000
FIGURE12.2: A circuit diagram.
or
V =
1
j C
I =
j
C
I (12.8)
Note that capacitor current and voltage are out of phase by 90
, that is voltage lags behind

current by 90
.
Equations (12.6)(12.8) all have the form of V = ZI, where Z represents the impedance
of the circuit element and is, in general, a complex number, with units of Ohms. The impedance
for the resistor is R, the inductor, j L, and the capacitor,
j
C
. The impedance is a complex
number andnot a phasor eventhoughit may looklike one. The imaginary part of the impendence
is called reactance.
The nal part to working in the phasor domain is to transform a circuit diagram from
the time to phasor domain. For example, the circuit shown in Fig. 12.2 is transformed into
the phasor domain, shown in Fig. 12.3, by replacing each circuit element with their impedance
equivalent and sources by their phasor. For the voltage source, we have
v
s
= 100 sin 500t = 100 cos(500t 90
) mV 500 |90
mV
For the capacitor, we have
0.5F
j
C
= j 4000
I
1000
500 90 mV
4000 j
100 j
FIGURE12.3: Phasor and impedance equivalent circuit for Fig. 12.2.

P1: KDD
For the resistor, we have
1000 1000
For the inductor, we have
200 mH j L = j 100
Each of the elements are replaced by their phasor and impedance equivalents as shown in
Fig. 12.3.
12.3 KIRCHHOFFS LAWS ANDOTHERTECHNIQUES
INTHEPHASORDOMAIN
It is fortunate that all of the material presented before in this chapter involving Kirchhoff s
current and voltage laws, and all the other techniques apply to phasors. That is, for KVL, the
sum of phasor voltages around any closed path is zero
V
i
= 0 (12.9)
and for KCL, the sum of phasor currents leaving any node is zero
I = 0 (12.10)
Impedances in series are given by
Z = Z
1
+ + Z
n
(12.11)
Impedances in parallel are given by
Z =
1
1
Z
1
+ +
1
Z
n
(12.12)
The node-voltage method, as well as superposition, Th evenin equivalent circuits is applicable
in the phasor domain. The following two examples illustrate the process, with the most difcult
aspect involving complex algebra.
Example Problem12.1. For the circuit shown in Fig. 12.3, nd the steady-state response i.
Solution. The impedance for the circuit is
Z = j 4000 +1000 + j 100 = 1000 j 3900
Using Ohms law,
I =
V
Z
=
0.5 |90
1000 j 3900
=
0.5 |90
4026|76
= 124|14
A
P1: KDD
Returning to the time domain, the steady-state current is
i = 124 cos (500t 14
) A
Example Problem12.2. . Find the steady-state response v using the node-voltage method for
the following circuit.
50sin10 V
s
v = ( ) 20 cos 10 20 A
s
i t = +
1
F
10
1
H
5
1
1

2

+
v
t
Solution. The rst step is to transform the circuit elements into their impedances, which for
the capacitor and inductor are
1
10
F
j
C
= j
1
5
H j L = j 2
The phasors for the two sources are:
v
s
= 50 sin t V V
s
= 50|90
V
i
s
= 20 cos (t +20
) A I
s
= 20| 20
Since the two resistors retain their values, the phasor drawing of the circuit is shown in the
following gure with the ground at the lower node.
1
1

2

+
V
=50 90 V
s
V
=20 20
s
I
j 2 j
1
P1: KDD
Writing the node-voltage equation for node 1 gives
V 50|90
+
V
j
+
V
j 2
+2V 20| 20
= 0
Collecting like terms, converting to rectangular form and converting to polar form gives
V
3 +
j
2
= 50|90
+20| 20
3 +
j
2
= 50 j +18.8 + j 6.8 = 18.8 j 43.2

V 3.04| 9.5
= 47.1|66.5
V =
47.1|66.5
3.04|9.5
= 15.5|76
The steady-state solution is

v = 15.6 cos (10t 76
) V
P1: KDD
140
P1: KDD
141
C H A P T E R 1 3
Active Analog Filters
This section presents several active analog lters involving the op amp. Passive analog lters
use passive circuit elements: resistors, capacitors and inductors. To improve performance in a
passive analog lter, the resistive load at the output of the lter is usually increased. By using the
op amp, ne control of the performance is achieved without increasing the load at the output of
the lter. Filters are used to modify the measured signal by removing noise. A lter is designed
in the frequency domain so that the measured signal to be retained is passed through and noise
is rejected.
Shown in Fig. 13.1 are the frequency characteristics of four lters: low-pass, high-pass,
band-pass and notch lters. The signal that is passed through the lter is indicated by the
frequency interval called the passband. The signal that is removed by the lter is indicated
by the frequency interval called the stopband. The magnitude of the lter, |H( j )|, is one
in the passband and zero in the stopband. The low-pass lter allows slowly changing signals
with frequency less than
1
pass through the lter, and eliminates any signal or noise above
1
. The high-pass lter allows quickly changing signals with frequency greater than
2
to pass
through the lter, and eliminates any signal or noise with frequency less than
2
. The band-pass
lter allows signals in the frequency band greater than
1
and less than
2
to pass through the
lter, and eliminates any signal or noise outside this interval. The notch lter allows signals in
the frequency band less than
1
and greater than
2
to pass through the lter, and eliminates
any signal or noise outside this interval. The frequencies
1
and
2
are typically called cutoff
frequencies for the low-pass and high-pass lters.
In reality, any real lter cannot possibly have these ideal characteristics, but instead has
a smooth transition from the passband to the stopband, as shown, for example in Fig. 13.2;
the reason for this behavior is described in a later chapter. Further, it is sometimes conve-
nient to include both amplication and ltering in the same circuit, so the maximum of the
magnitude does not need to be one, but can be a value of M specied by the needs of the
application.
P1: KDD
( j) H
( j) H
( j) H
( j) H
Passband
Passband
Passband
Passband Passband
Stopband
Stopband
Stopband Stopband
S
t
o
p
b
a
n
d
FIGURE 13.1: Ideal magnitudefrequency response for four lters, from top to bottom: low-pass,
high-pass, band-pass and notch.
Stopband
2
M
M
Passband Stopband
(j) H
FIGURE13.2: Arealistic magnitudefrequency response for a band-pass lter. Note that the magnitude
M does not necessarily need to be one. The passband is dened as the frequency interval when the
magnitude is greater than
M
2
.
142
P1: KDD
ACTIVE ANALOG FILTERS 143
To determine the lters performance, the lter is driven by a sinusoidal input. One varies
the input over the entire spectrum of interest (at discrete frequencies) and records the output
magnitude. The critical frequencies are when |H( j )| =
M
2
.
Example 13.1. Using the low-pass lter in the following circuit, design the lter to have a gain
of 5 and a cutoff frequency of 500 rad/s.
Ra
Rb
C
+
v0
VS
Solution. By treating the op amp as ideal, note that the noninverting input is connected to
ground, andtherefore, the inverting input is also connectedto ground. The operationof this lter
is readily apparent for at lowfrequencies, the capacitor acts like an open circuit, reducing the cir-
cuit to an inverting amplier that passes lowfrequency signals. At high frequencies, the capacitor
acts like a short circuit, which connects the output terminal to the inverting input and ground.
The phasor method will be used to solve this problem by rst transforming the circuit
into the phasor domain as shown in the following gure.
Ra
Rb
+
V0
VS
1
j C
P1: KDD
Summing the currents leaving the inverting input gives
V
s
R
a
V
0
1
j C
V
0
R
b
= 0
Collecting like terms and rearranging yields
V
0
1
1
j C
+
1
R
b
=
V
s
R
a
After further manipulation,
V
0
V
s
=
1
R
a
1
1
1
j C
+
1
R
b
=
1
R
a
1
j C +
1
R
b
V
0
V
s
=
1
R
a
C
1
j +
1
R
b
C
Similar to the reasoning for the characteristic equation for a differential equation, the cutoff
frequency is dened as
c
=
1
R
b
C
(i.e., the denominator term, j +
1
R
b
C
set equal to zero).
Thus, with the cutoff frequency set at
c
= 500 rad/s, then
1
R
b
C
= 500. The cutoff frequency
is also dened as when |H( j )| =
M
2
, where M= 5. The magnitude of
V
0
V
s
is given by
V
0
V
s
=
1
R
a
C
2
+
1
R
b
C
2
and at the cutoff frequency,
c
= 500 rad/s,
5
2
=
1
R
a
C
2
c
+
1
R
b
C
2
With
1
R
b
C
= 500, the magnitude is
5
2
=
1
R
a
C
2
c
+
1
R
b
C
2
=
1
R
a
C
500
2
+500
2
=
1
R
a
C
500
2
which gives
R
a
C =
1
2500
P1: KDD
Since we have three unknowns and two equations (R
a
C =
1
2500
and
1
R
b
C
= 500), there are an
innite number of solutions. Therefore, one canselect a convenient value for one of the elements,
say R
a
= 20 k, and the other two elements are determined as
C =
1
2500 R
a
=
1
2500 20000
= 20 nF
and
R
b
=
1
500 C
=
1
500 20 10
9
= 100 k
A plot of the magnitude versus frequency is shown in the following gure. As can be seen, the
cutoff frequency gives a value of magnitude equal to 3.53 at 100 Hz, which is the design goal.
0 200 400 600 800 1000 1200 1400
6
5
4
3
2
1
0
Frequency (rad/s)
M
a
g
n
i
t
u
d
e
Example 13.2. Using the high-pass lter in the following circuit, design the lter to have a
gain of 5 and a cutoff frequency of 100 rad/s.
Ra
Rb
C
+
v0
V
S

P1: KDD
Solution. Since the op amp is assumed ideal, and the noninverting input is connected to
ground, therefore the inverting input is also connected to ground. The operation of this lter
is readily apparent for at low frequencies, the capacitor acts like an open circuit and so no input
voltage is seen at the noninverting input. Since there is no input, then the output is zero. At
high frequencies, the capacitor acts like a short circuit, which reduces the circuit to an inverting
amplier that passes through high frequency signals.
As before, the phasor method will be used to solve this problem by rst transforming the
circuit into the phasor domain as shown in the following gure.
R
a
R
b
+
V
0
V
S
1
jC
Summing the currents leaving the inverting input gives
V
s
R
a
+
1
j C
V
0
R
b
= 0
Rearranging yields
V
0
V
s
=
R
b
R
a
+
1
j C
=
R
b
R
a
j
j +
1
R
a
C
At cutoff frequency
c
= 100 rad/s =
1
R
a
C
. The magnitude of
V
0
V
s
is given by
V
0
V
s
=
R
b
R
a
2
+
1
R
a
C
2
and at the cutoff frequency,
5
2
=
R
b
R
a
2
c
+
1
R
a
C
2
P1: KDD
With
1
R
a
C
= 100 and
c
= 100 rad/s, gives
5
2
=
R
b
R
a
2
c
+
1
R
a
C
2
=
R
b
R
a
1
R
a
C
100
2
+100
2
=
R
b
R
a
100
100
=
R
b
2R
a
Thus
R
b
R
a
= 5. Since we have three unknowns and two equations, one can select a convenient
value for one of the elements, say R
b
= 20 k, and the other two elements are determined as
R
a
=
R
b
5
=
20000
5
= 4 k
and
C =
1
100R
a
=
1
100 4000
= 2.5 F
A plot of the magnitude versus frequency is shown in the following gure. As can be seen, the
cutoff frequency gives a value of magnitude equal to 3.53 at 500 Hz, which is the design goal.
0 200 400 600 800 1000 1200 1400
6
5
4
3
2
1
0
Frequency (rad/s)
M
a
g
n
i
t
u
d
e
The next example demonstrates the technique to create a band-pass lters (which require
two cutoff frequencies).
Example 13.3. Using the band-pass lter in the following circuit, design the lter to have a
gain of 5 and pass through frequencies from 100 to 500 rad/s.
P1: KDD
CH
+
v0
CL
+
vL
VS
L
a
R
L
b
R
H
b
R
H
a
R

Solution. As usual, the design of the lter is done in the phasor domain, and makes use of
work done in the previous two examples. Note the elements around the op amp on the left are
the low-pass lter circuit elements, and those on the right, the high-pass lter. In fact, when
working with op amps, lters can be cascaded together to form other lters; thus a low-pass
and high-pass lter cascaded together form a band-pass. The phasor domain circuit is given in
the next gure.
+
V0
+
VL
VS
L
a
R
L
b
R
H
b
R
H
a
R
1
L
j C
1
H
j C
As before, the noninverting input to the op amps are connected to ground, which means
that the inverting input is also connected to ground. Summing the currents leaving the inverting
input for each op amp gives
V
s
R
a
L
V
L
1
j C
L
V
L
R
b
L
= 0
V
L
R
a
H
+
1
j C
H
V
0
R
b
H
= 0
P1: KDD
Solving the rst equation for V
L
gives
V
L
=
1
R
a
L
C
L
1
j +
1
R
b
L
C
L
V
s
Solving the second equation for V
0
gives
V
0
=
R
b
H
R
a
H
j
j +
1
R
a
H
C
H
V
L
Substituting V
L
into the previous equation yields
V
0
=
R
b
H
R
a
H
j
j +
1
R
a
H
C
H
1
R
a
L
C
L
1
j +
1
R
b
L
C
L
V
s
The form of the solution is simply the product of each lter. The magnitude of the lter is
V
0
V
s
=
R
b
H
R
a
H
2
+
1
R
a
H
C
H
2
1
R
a
L
C
L
2
+
1
R
b
L
C
L
2
Since there are two cutoff frequencies, two equations evolve,
c
H
=
1
R
a
H
C
H
= 100 rad/s
and
c
L
=
1
R
b
L
C
L
= 500 rad/s
At the either cutoff frequency, the magnitude is
5
2
, such that at
c
H
= 100 rad/s
5
2
=
R
b
H
R
a
H
c
H
2
c
H
+
1
R
a
H
C
H
2
1
R
a
L
C
L
2
C
H
+
1
R
b
L
C
L
2
=
R
b
H
R
a
H
100
100
2
+100
2
1
R
a
L
C
L
100
2
+500
2
P1: KDD
Therefore,
500
26 =
R
b
H
R
a
H
R
a
L
C
L
The other cutoff frequency gives the same result as the previous equation. There are now
three equations (
1
R
a
H
C
H
= 100,
1
R
b
L
C
L
= 500 and 500
26 =
R
b
H
R
a
H
R
a
L
C
L
), and six unknowns.
For convenience, set R
b
L
= 100 k and R
a
H
= 100 k, which gives C
L
=
1
500R
b
L
= 20nF and
C
H
=
1
100R
a
H
= 0.1 F. Now from 500
26 =
R
b
H
R
a
H
1
R
a
L
C
L
,
R
b
H
R
a
L
= 500
26C
L
R
a
H
= 5.099
Once again, one can specify one of the resistors, say R
a
L
= 10 k, giving R
b
H
= 50.099 k.
Aplot of the magnitude versus frequency is shown in the following gure. As can be seen,
the cutoff frequency gives a value of magnitude equal to 3.53 at 500 Hz, which is the design
goal.
3.5
4
4.5
3
1
1.5
0.5
0
2.5
2
0 200 400 600 800 1000 1200 1400
Frequency (rad/s)
M
a
g
n
i
t
u
d
e
None of the lters in Examples 13.113.3 have the ideal characteristics of Fig. 13.1. To improve
the performance from the passband to stopband in a low-pass lter with a sharper transition,
one can cascade identical lters together, i.e., connect the output of the rst lter to the input of
the next lter and so on. The more cascaded lters, the better the performance. The magnitude
of the overall lter is the product of the individual lter magnitudes.
P1: KDD
v
0
V
S
R2
C
2
R1
C1
V
S
R2
R
1
C
2
C
1
v
0
C
3
R3
FIGURE 13.3: (Top) Second-order Butterworth low-pass lter. (Bottom) Third-order Butterworth
low-pass lter.
While this approach is appealing for improving the performance of the lter, the overall
magnitude of the lter does not remain a constant in the passband. Better lters are available
with superior performance such as a Butterworth lter. Two Butterworth lters are shown in
Fig. 13.3. Analysis of these lters is carried out in Exercises 183 and 184.
P1: KDD
152
P1: KDD
153
C H A P T E R 1 4
Bioinstrumentation Design
Figure 14.1 described the various elements needed in a biomedical instrumentation system. The
purpose of this type of instrument is to monitor the output of a sensor or sensors and to extract
information from the signals that are produced by the sensors.
Acquiring a discrete-time signal and storing this signal in computer memory from a
continuous-time signal is accomplished with an analog-to-digital (A/D) converter. The A/D
converter uniformly samples the continuous-time waveform and transforms it into a sequence
of numbers, one every t
k
seconds. The A/D converter also transforms the continuous-time wave
forminto a digital signal (i.e., the amplitude takes one of 2
n
discrete values) which are converted
into computer words and stored in computer memory. To adequately capture the continuous-
time signal, the sampling instants t
k
must be selected carefully so that information is not lost.
The minimum sampling rate is twice the highest frequency content of the signal (based on the
sampling theorem from communication theory). Realistically, we often sample at ve to ten
times the highest frequency content of the signal so as to achieve better accuracy by reducing
aliasing error.
14.1 NOISE
Measurement signals are always corrupted by noise in a biomedical instrumentation system.
Interference noise occurs when unwanted signals are introduced into the system by outside
sources, e.g. power lines and transmitted radio and television electromagnetic waves. This
kind of noise is effectively reduced by careful attention to the circuits wiring conguration to
minimize coupling effects.
Interference noise is introduced by power lines (50 or 60 Hz), uorescent lights, AM/FM
radio broadcasts, computer clock oscillators, laboratory equipment, cellular phones, etc. Elec-
tromagnetic energy radiating from noise sources is injected into the amplier circuit or into
the patient by capacitive and/or inductive coupling. Even the action potentials from nerve
conduction in the patient generate noise at the sensor/amplier interface. Filters are used to
reduce the noise and to maximize the signal-to-noise (S/N) ratio at the input of the A/D
converter.
P1: KDD
Sensor Calibration
A/D
Analog
processing
Signal
processing
Data
storage
Control &
feedback
Output
display
Data
transmission

FIGURE 14.1: Basic instrumentation systems using sensors to measure a signal with data acquisition,
storage and display capabilities, along with control and feedback.
Low frequency noise (amplier DC offsets, sensor drift, temperature uctuations, etc.)
is eliminated by a high-pass lter with the cutoff frequency set above the noise frequencies
and below the biological signal frequencies. High frequency noise (nerve conduction, radio
broadcasts, computers, cellular phones, etc.) is reduced by a low-pass lter with the cutoff set
below the noise frequencies and above the frequencies of the biological signal that is being
monitored. Power-line noise is a very difcult problem in biological monitoring since the
50 or 60 Hz frequency is usually within the frequency range of the biological signal that is
being measured. Band-stop lters are commonly used to reduce power-line noise. The notch
frequency in these band-stop lters is set to the power-line frequency of 50 or 60 Hz with the
cutoff frequencies located a few Hertz to either side.
The second type of corrupting signal is called inherent noise. Inherent noise arises from
random processes that are fundamental to the operation of the circuits elements and, hence, is
reduced by good circuit design practice. While inherent noise can be reduced, it can never be
eliminated. Low-pass lters can be used to reduce high frequency components. However, noise
signals within the frequency range of the biosignal being amplied cannot be eliminated by this
ltering approach.
14.2 COMPUTERS
Computers consist of three basic units: the central processing unit (CPU), the arithmetic and
logic unit (ALU), and memory. The CPU directs the functioning of all other units and controls
P1: KDD
BIOINSTRUMENTATION DESIGN 155
the ow of information among the units during processing procedures. It is controlled by
program instructions. The ALU performs all arithmetic calculations (add, subtract, multiply,
and divide) as well as logical operations (AND, OR, NOT) that compare one set of information
to another.
Computer memory consists of read only memory (ROM) and random access memory
(RAM). ROM is permanently programmed into the integrated circuit that forms the basis of
the CPU and cannot be changed by the user. RAM stores information temporarily and can be
changed by the user. RAM is where user-generated programs, input data, and processed data
are stored.
Computers are binary devices that use the presence of an electrical signal to represent 1
and the absence of an electrical pulse to represent 0. The signals are combined in groups of
8 bits , a byte, to code information. A word is made up of 2 bytes. Most desktop computers
that are available today are 32-bit systems, which means that they can address 4.29 109
locations in memory. The rst microcomputers were 8-bit devices that could interact with only
256 memory locations.
Programming languages relate instructions and data to a xed array of binary bits so that
the specic arrangement has only one meaning. Letters of the alphabet and other symbols, e.g.
punctuation marks, are represented by special codes. ASCII stands for the American Standard
Code for Information Exchange. ASCII provides a common standard that allows different
types of computers to exchange information. When word processing les are saved as text les,
they are saved in ASCII format. Ordinarily, word processing les are saved in special program-
specic binary formats, but almost all data analysis programs can import and export data in
ASCII les.
The lowest level of computer languages is machine language and consists of the 0s and
1s that the computer interprets. Machine language represents the natural language of a partic-
ular computer. At the next level, assembly languages use English-like abbreviations for binary
equivalents. Programs written in assembly language can manipulate memory locations directly.
These programs run very quickly and are often used in data acquisition systems that must rapidly
acquire a large number of samples, perhaps froman array of sensors, at a very high sampling rate.
Higher level languages, e.g. FORTRAN, PERL, and C++, contain statements that
accomplish tasks that require many machine or assembly language statements. Instructions in
these languages often resemble English and contain commonly used mathematical notations.
Higher level languages are easier to learn than machine and assembly languages. Program
instructions are designed to tell computers when and how to use various hardware components
to solve specic problems. These instructions must be delivered to the CPU of a computer in
the correct sequence in order to give the desired result.
When computers are used to acquire physiological data, programming instructions tell
the computer when data acquisition should begin, howoften samples should be taken fromhow
P1: KDD
many sensors, how long data acquisition should continue, and where the digitized data should
be stored. The rate at which a system can acquire samples is dependent upon the speed of the
computers clock, e.g. 233 MHz, and the number of computer instructions that must completed
in order to take a sample. Some computers can also control the gain on the input ampliers
so that signals can be adjusted during data acquisition. In other systems, the gain of the input
ampliers must be manually adjusted.
P1: KDD
MOBK036-exe MOBK036-Enderle.cls November 1, 2006 16:12
157
Exercises
1. Suppose the current owing through the circuit element in Fig. 3.5 is
i (t) =
0 t < 0
5e
2t
A t 0
Find q(t).
2. The charge entering the upper terminal in the circuit element in Fig. 3.5 is
3 sin(2000t) C. (a) How much charge enters the terminal from t = 0 to t = 0.5 ms?
(b) Find i (t).
3. Let i (t) shown in the following diagram ow through the circuit element in Fig. 3.5.
With i (t) = 0 for t < 0, nd the total charge at: (a) 1 s, (b) 2 s, (c) 3 s and (d) 4 s.
i(t)
(A)
2
1
1
1 2 3 4
t
(s)
4. Let the charge entering the upper terminal in the circuit element in Fig. 3.5 be q(t) =
e
1000t
sin(2000t) C for t 0. Determine the current for t 0.
5. Find the power absorbed for the circuit element in Fig. 3.5 if (a) v = 10 V
and i = 2 A, (b) v = 10 V and i = 2 A, (c) v = 5 V and i = 2 A, (d) v = 10 V
and i = 3 A.
6. Findthe power absorbedfor the circuit element inFig. 3.5if (a) v = 5 V and i = 2 A,
(b) v = 5 V and i = 12 A, (c) v = 5 V and i = 5 A, (d) v = 5 V and i = 2 A.
P1: KDD
7. Find the power absorbed for the circuit element in Fig. 3.5 if
a.
t
2 0
t
2 0
i
(A)
v
(V)
1
2
1
1 1
(s) (s)
b.
v
(V)
i
(A)
2
1
1 2 3
t
1
1 2 3
t
0 0
(s) (s)
c.
v
(V)
1
1 2 3
t
i
(A)
2
1
1 2
t
0 0
(s)
(s)
P1: KDD
EXERCISES 159
d.
i
(A)
t
v
(V)
2 0
t
2 0
(s)
(s)
1 1
e.
t
2
1
1 2
i
(A)
0
v
(V)
1
1 2
t
0
(s) (s)
8. Find the total energy delivered to the circuit element in Fig. 3.5 if
v = 3e
1000t
u(t) V
i = 5e
1000t
u(t) A
9. The voltage and current at the terminals in Fig. 3.5 are
v = e
500t
u(t) V
i = 2te
500t
u(t) A
(a) Find the time when the power is at its maximum.
(b) Find the energy delivered to the circuit element at t = 0.004 s.
(c) Find the total energy delivered to the circuit element.
10. The voltage and current at the terminals in Fig. 3.5 are
v = te
10,000t
u(t) V
i = (t +10)e
10,000t
u(t) A
(a) Find the time when the power is at its maximum.
(b) Find the maximum power.
P1: KDD
(c) Find the energy delivered to the circuit at t = 1 10
4
s.
(d) Find the total energy delivered to the circuit element.
11. The voltage at the terminals in Fig. 3.5 is
v =
0V
t V
2 t V
0 V
t < 0
0 t 1
1 < t 2
t > 2
If
p =
0 W t < 0
t
2
W 0 t 1
t
2
4t +4 W 1 < t 2
0 W t > 2
how much charge enters the terminal between t = 0 and t = 2 s?
12. For the following circuit, nd: (a) I
1
, V
2
and V
3
, (b) the power absorbed and delivered.
3V
4 V
2 A
V2
2V
2V
+
+ V3
I1
3 A
13. For the following circuit nd (a) V
1
, (b) I
2
, (c) the power absorbed and delivered.
2V1 5A 2V
4V 4V
+
V1
I2
P1: KDD
EXERCISES 161
14. For the following circuit nd (a) V
1
, (b) the power absorbed and delivered.
3 V
3A
2A
2 V1
2 V
+ V1
I1 5 V
+
6 V
15. For the following circuit, nd the power in each circuit element.
2 A 4 A
3 A
5 V 3 V
4 V
10 V
16. For the following circuit, nd (a) I
1
and I
2
, (b) power dissipated in each resistor, (c)
show that the power dissipated equals the power generated.
2 2
6 2
2 2
I2
I1
14 V
P1: KDD
17. (a) Find the power dissipated in each resistor. (b) Showthat the power dissipated equals
the power generated.
5 V
2 V
5 V
1
4
3
18. Find V
R
in the following circuit.
10 V
2 VR
2
5
3
3 V
+
VR
19. Find I in the following circuit.

12 V
8 V
4
5
2
3I
I
P1: KDD
EXERCISES 163
20. Find I
R
4 A 2 A 3 IR 2 1
IR
21. Find I
2
3 A 3 I1
I1
I2
1
3
1
8
1
4
22. Find i
b
5 A 2Va
ib
3 6 8 2
+
Va
23. Find the equivalent resistance R

ab
4
4
2
3 4
a
b
P1: KDD
ab
a
b
7
4 2
8
4
3
3
1
2
3
ab
8
8
a
b
2
6 4
6
3
2
ab
9
a b
2 4
4 2
6
6
P1: KDD
EXERCISES 165
ab
1
3 6
4
12
12
5
4 1
a
b
ab
17
20
7
8
15
5
20
10
b a
29. Find I
1
2
3
4
2 5 A
I1
30. Find I
1
and V
1
2
16 80
5
3
12
20 A
+
V1
I1
P1: KDD
31. Find I
1
and V
1
5
15
20
60
10 A
I
1
+ V1
32. Find I
1
, V
1
and V
2
18 V
3
6 9
6
4.5 9
+
V1
+
V2
I1
33. Use the node-voltage method to determine v
1
and v
2
.
5 2
3 3 35 V 50 V
10
+
v2
+
v1

1
and v
2
.
2 A 5 A 16 10
2
+
v2
+
v1
P1: KDD
EXERCISES 167
1
and v
2
.
15 V 5 A
2 3
4 5
1
+
v1
v2 +
1
and v
2
.
2 A 2 i1 16 10
2
+
v2
+
v1
i1
1
and v
2
.
3
2 5 1 3 A
2 A
2Va
+
v1
+
v2
+ Va
P1: KDD
1
and v
2
.
+
v1
+
v2
+ Vb
3 2
10
10 V
2 Vb
2 A
5
3
6 5 3ia
ia
1
and v
2
.
10 4 A
4 V
6 3
8
8
5
4
5 V
+
v2
+
v1

1
and v
2
.
5 V
2
4
5
3
10 V
+
v2
+
v1
3v1 4 V
2
P1: KDD
EXERCISES 169
1
and v
2
.
3 5
3ia
5 A 2 2 A 20
40
10 V
+
v1
+
v2
ia
1
and v
2
.
3 V
3
+
v1
+
v2
6
2v1
5
5
4
4ia
5
8 2 A
ia
1
and v
2
.
15 V 5 A
3ia
3
5
2 5
2 1
+
v1
+
v2
ia
P1: KDD
44. Use the mesh-current method to determine i
1
and i
2
.
10
15
10 5
5 V 2 V
20
i 2 i1
1
and i
2
.
5 4
20 10
3
10 V
i2
i1
1
and i
2
.
5 V 3i2
10 5
2
3 5
i1 i2
1
and i
2
.
2
2 V
5 3 6
4 20
3 V 2 i2 5 V
i1
i2
P1: KDD
EXERCISES 171
1
and i
2
.
5
3 5
2
3i1
20 V
10
10 V
4 15
i2 i1
1
and i
2
.
10
4
20 V
10 V 2va
10
6
2 5 3
4
+
va
i1
i2
1
and i
2
.
2 V
3 A
4 V
8 4
3
2 5
i1
i2
P1: KDD
1
and i
2
.
+ va
5 3
5 V 5 A
3
3va
3 2
2
i1 i2
1
and i
2
.
6 V
2 A
10 V
4
2
3 2
3 4
5 3i1 6
5
i1
i2
1
and i
2
.
2i1
2 A
5 V
5 6
10
3 4
5 1
4
2 V
2
2va
+
va
i2
i1
P1: KDD
EXERCISES 173
1
and i
2
.
2 3 5
5
3
6
5
2
6 4
8
2 V
3 va
5 V
5 V
10 V 3 A
va
+
i1 i2
55. Use a series of source transformations and resistor combinations to nd v
o
.
+
vo
2 A 5 4 A
3
3 5
6
2 V
o
.
15
5
10 10 5 A 2
2 4
4
10 V
+
vo
P1: KDD
o
.
+
vo
5
3 A
10
3
2 V
10 2 2 A 6
4 2
5 V
58. Use the superposition method to nd v
o
.
5 V
4 3
2 2
+
v0
10 V
o
.
3
3 4 V
0.5
2 V
3 10 A 2
+
vo

o
.
3 A 2
3
5
4 V
0.5
2ia 3 V
2
4
+
vo
ia
3
P1: KDD
EXERCISES 175
o
.
5 V
2
5 3
3
5 A
2
3va
+va
+
vo
62. Find the Th evenin equivalent with respect to terminals a and b.

5 A
a
b
5 2
3
5 2 10
3 35 V
a
b
50 V
2 3
4 15 V
a b
5 A
1
5
P1: KDD
2 A 16
2
10 2i1
a
b
i1
a
b
3 A 2
5 A
3
5 2va
+va
a
b
3ia
3 5 40
10 V 2 A 2 5 A
ia
68. Find the Norton equivalent with respect to terminals a and b.
5 V 8 10
a
b
8 6
P1: KDD
EXERCISES 177
8 2
2
a
b
3 5 A 5 A
a b
3 8
6
2 4
2 V 2 A
5 V
3ia
3
a
b
2 2
6
ia
2 V
5
5ia
3
a
b
3
5
6 4
8
2va
+ va
ia
P1: KDD
10 V 6
a
b
3 5
3 V
2
5i1
i
1
74. A current pulse given by i (t) = (2 +10e
2t
)u(t) is applied through a 10 mH inductor.
(a) Find the voltage across the inductor. (b) Sketch the current and voltage. (c) Find
the power as a function of time.
75. A current pulse given by i (t) = (5 +3 sin(2t))u(t) is applied through a 2 mH inductor.
Determine the voltage across the inductor.
76. The current pulse shown in the following gure is applied through a 5 mH inductor.
Find the voltage, power and energy.
i(t)
(A)
1
1 2 3
t
0
1
4
(s)
77. The voltage across an L = 2.5 mH inductor is v(t) = 10 cos(1000t) mV, with i (0) =
1 mA. (a) Find i (t) for t 0. (b) Find the power and energy.
P1: KDD
EXERCISES 179
78. The voltage across an inductor is given by the following gure. If L = 30 mH and
i (0) = 0 A, nd i (t) for t 0.
v
(mv)
4
1 2 3
t
0
(s)
79. The voltage across an inductor is given by the following gure. If L = 50 mH and
i (0) = 0 A, nd i (t) for t 0.
v
(mv)
1
t
(s)
1 2 0
80. The voltage across a 4 F capacitor is v(t) = (200,000t 50,000)e
2000t
u(t) V. Find
(a) current through the capacitor, (b) power as a function of time, (c) energy.
81. The voltage across a 0.5 F capacitor is v(t) = (3 +5e
2t
)u(t) V. Find the current and
power.
82. The voltage across a 1 Fcapacitor is v(t) = (5t +3 sin(2t))e
3t
u(t) V. Findthe current
and power.
83. The current through a 5 F capacitor is
i (t) =
0 mA t < 0 ms
5t
2
mA 0 t < 1 ms
5
2 t
2
mA 1 <t
2 ms
0 mA t >
2 ms
Find the voltage across the capacitor.
P1: KDD
84. The current through a 10 F capacitor is given by the following gure. If v(1) = 0 V,
nd v(t) for t > 1 s.
i
(mA)
1
1 2 0
t
(ms)
3
85. The current through a 100 F capacitor is given by the following gure. If v(0) is 0 V,
nd v(t) for t 0 s.
2
t
(ms)
1 2 0
i(t)
(mA)
86. Find equivalent inductance between terminals a and b for the circuit in the following
gure.
a
b
3 H
3 H
2 H
4 H 2 H
P1: KDD
EXERCISES 181
gure.
a
b
4 H
8 H
7 H 4 H 1 H
3 H
2 H 3 H 2 H
3 H
gure.
a
b
8 H
8 H
2 H 2 H
6 H
6 H
4 H
89. Find the equivalent capacitance between terminals a and b for the following circuit.
4 F 6 F
6 F
3 F 4 F
1
2
F
a
b
P1: KDD
a b
3 F
8 F
6 F 4 F
5 F
6 F
4 F 4 F
a b
7 F
9 F
8 F
5 F
5 F 4 F
16 F
92. Reduce the following circuit to a single capacitor and inductor.
a
b
6 H
3 H
6 H
1 H
4 H
4 H
8 F
2 F
10 F
1
2
H
P1: KDD
EXERCISES 183
93. Reduce the following circuit to a single capacitor and inductor.
a
b
6 F
4 F
5 F
18 F
6 H
3 H
1 H
4 H
1 H
94. For the following circuit, I
S
= 2(1 e
5t
)u(t) Aand i (0) = 2 A. (a) Find v(t) for t 0.
(b) Find i (t) for t 0.
20 H 5 H
i
+
v
( )
5
2 1 ( ) A
t
e u t

S
= 5 sin 2t A and i (0) =
1
2
A. (a) Find v(t) for t 0. (b)
Find i (t) for t 0.
20 H 5 H
+
v
4 H
i
I
S
P1: KDD
S
= 5(1 e
3t
) u(t) A, i
1
(0) = 1 A, and i
2
(0) = 2 A. Find
the following for t 0: (a)v
o
(t), (b)v
1
(t), (c) i
o
(t), (d) i
1
(t), (e) i
2
(t).
1 H
20 H 5 H
+
v
1
i
2
+v
0

i
1
i
0
IS
97. For the following circuit, V
S
= 3(1 e
5t
) u(t) V and v(0) = 2 V. Find the following
fort 0: (a)i (t), (b) v(t).
+
v
6 F
3 F
i
V
S
S
= 5 cos 3t Vand v(0) = 1 V. Find the following for t 0:
(a) i (t), (b) v(t).
+
v
20 F
5 F
i
V
S
P1: KDD
EXERCISES 185
S
= 2(1 e
3t
) u(t) V, v
1
(0) = 3 V and v
2
(0) = 2 V. Find
the following for t 0: (a) i
1
(t), (b) v
1
(t), (c) v
2
(t), (d) i
2
(t).
5 F
18 F 2 F
+
v
2
+v
1
i
1
i
2
V
S
100. The switch has been in position a for a long time. At t = 0, the switch instantaneously
moves to position b. Find i
L
and v
1
for t > 0.
+
v
1
i
L
2 H
b
a
t = 0
10
3
6 V
L
and v
1
for t > 0.
b
a
t = 0
5
4 6
10
8 A
+
v
1
4 H
i
L
P1: KDD
L
and v
1
for t > 0.
b
a
t = 0
5 V
2
12 4
6
5 H
+
v
1
i
L
L
and v
1
for t > 0.
3
6
5 H
i
L
b
a
t = 0
8
6 10 V
+
v
1
L
and v
1
for t > 0.
2 H
b
a
t = 0
2
4 5 A
i
L
5 20 2
+
v
1
P1: KDD
EXERCISES 187
L
and v
1
for t > 0.
10 V
2
3
b
a
t = 0
4 4 H
i
L
16
+
v
1
L
and v
1
for t > 0.
b
a
t = 0
10 V
8
8
12
5 2 H
i
L
+
v
1
L
and v
1
for t > 0.
b
a
t = 0
20 H 5 H 16
2
3 20 V
i
L
+
v
1
P1: KDD
L
, i
1
and v
1
for t > 0.
b
a
t = 0
3 H
2
10 V 4 5i
1
12
+
v
1
i
1
i
L
L
, i
1
and v
1
for t > 0.
b
a
t = 0
6 H 6 A
2i
1
5
20
4 40 10
+
v1
i
L
i
1
moves to position b. Find v
c
and i
1
for t > 0.
b
a
t = 0
2 F 10 V
5
10
+
v
C
i
1
P1: KDD
EXERCISES 189
c
and i
1
for t > 0.
b
a
t = 0
10 F
2 10
10 40 10 V 8 A
+
v
C
i
1
c
and i
1
for t > 0.
b
a
t = 0
3 F
4
3 6
8
+
v
C
5 V
i
1
c
and i
1
for t > 0.
b
a
t = 0
10 F
+
v
C
40 40
12
10 8 A
i
1
P1: KDD
c
and i
1
for t > 0.
b
a
t = 0
5 F
2
12 12 4 10 V
i1
+
vC
c
and i
1
for t > 0.
b
a
t = 0
4 F 5
i1
+
vC
153
8
8
12
5 A
c
and i
1
for t > 0.
b
a
t = 0
4 F
8
40 20 V
i1
+
vC
4 F 10
c
and i
1
for t > 0.
b
a
t = 0 5
20 V 4 2i1 12
+
vC
3 F
i1
P1: KDD
EXERCISES 191
c
and i
1
for t > 0.
b
a
t = 0
5i
1
5
20
8 12
+
v
C
3 3 F
6
15 V
i
1
119. The switch has been in position a for a very long time. At t = 0, the switch moves to
position b. Find i
L
and v
1
for t > 0.
b
a
t = 0
10 V 3 A 3 H
5 20
+v
1
i
L
L
and v
1
for t > 0.
3 H
i
L
+
v
1
b
a
t = 0
12
5 V
10 V
4
8
P1: KDD
L
and v
1
for t > 0.
b
a
t = 0
10 H 5 V 10 A 5 A 40
10 2
+
v
1
i
L
L
and v
1
for t > 0.
b
a
t = 0
10 V
+
v
1
12
2
5 V
6
5 H
4
L
i
1
and v
1
for t > 0.
b
a
t = 0
10 V
5 V
4
2
+
v
1
12 3 H 3i1
i1
P1: KDD
EXERCISES 193
L
, i
1
and v
1
for t > 0.
b
a
t = 0
6 A
4 V
4
20
5 40 10 3 H
2i
1
+
v
1
i
L
i
1
125. The switch has been position a for a very long time. At t = 0, the switch closes. Find
v
C
and i
1
for t > 0.
t = 0
5 V 3 A 2 F
5 20
5
+
vC
i1
c
and i
1
for t > 0.
b
a
t = 0
10 V
6
+
vC
3 3 F
2
20 3 A
i1
P1: KDD
c
and i
1
for t > 0.
b
a
t = 0
+
vC
120 V 5 A
40
10
10 F
12
i1
c
and i
1
for t > 0.
b
a
t = 0
2 F 8 F
10 V 5 V
5 10
+
v
C
i
1
c
and i
1
for t > 0.
b
a
t = 0
3 F
10 V
+
v
C
6
4
6 F
5
6 V
i
1
P1: KDD
EXERCISES 195
130. The switches have been in positions a and c for a long time. At t = 0, switch ab
instantaneously moves to position b. At t = 0.06, switch cd instantaneously moves to
position d. Find i
1
and v
c
for t > 0.
5 A 2
b
a
t = 0
5 F
+
v
C
3 A 5
d c
t = 0.06s
5 V
4
20 F
2
i
1
131. The switches have been in positions a and c for a long time. At t = 0, switch ab
instantaneously moves to position b. At t = 0.15, switch cd instantaneously moves to
position d. Find i
1
and v
c
for t > 0.
c
d
t = 0.15
b
a
t = 0
3 A
6
4
3 F
+
v
C
10
4 V 6 V
i
1
132. Find i
L
and v
c
for t > 0 for the following circuit if: (a) i
s
= 3u(t) A; (b) i
s
=
1 +3u(t) A.
4 H 3 F is 5
+
vC
iL
P1: KDD
133. Find i
L
and v
c
for t > 0 for the following circuit if: (a) v
s
= 5u(t) V; (b) v
s
=
2 +5u(t) V.
3 H 6 F vs
+
vC
iL
5
20
134. Find i
L
and v
c
s
= 10u(t) A; (b) i
s
=
1 +10u(t) A.
2 H 15 F is 10
+
vC
iL
135. Find i
L
and v
c
s
= 20u(t) V; (b) v
s
=
4 +20u(t) V.
16 H 1 F vs 4
+
vC
iL
4
136. Find i
L
and v
c
s
= 3u(t) A; (b) i
s
=
1 +3u(t) A.
200 H 2 F is 5
+
vC
i
L
P1: KDD
EXERCISES 197
137. Find i
L
and v
c
s
= 5u(t) V; (b) v
s
=
12 +5u(t) V.
360 H 10 F vs 6
+
vC
iL 6
138. Find i
L
and v
c
s
= 5u(t) A; (b) i
s
=
5 +5u(t) A.
350 H 3 F is 5
+
vC
iL
139. Find i
L
and v
c
s
= 3u(t) V; (b) v
s
=
2 +3u(t) V.
20 H 1 F vs 4
+
vC
iL
4
140. Find i
L
and v
c
s
= 10u(t) A; (b) i
s
= 1 +
10u(t) A.
25 H 5 F is 1
+
vC
iL
P1: KDD
141. Find i
L
and v
c
for t >0 for the following circuit if: (a) v
s
= 5u(t) V; (b) v
s
=
5u(t) +3 V.
4 H
1.5 F
2
iL
+vC
vs
142. Findi
L
andv
c
for t >0for the following circuit if: (a) i
s
= 3u(t) A; (b) i
s
= 3u(t) 1 A.
10 H
1 F
4
iL
+ vC
is
143. Find i
L
and v
c
s
=10u(t) A; (b) i
s
= 10u(t) +
5 A.
20 H
4 F
1
iL
+vC
2 is
144. Find i
L
, i
1
and v
c
s
= 5u(t) V; (b) v
s
=
5u(t) +2 V.
12 H
12 F
iL
+vC
8
12
4
5i1 vs
i1
P1: KDD
EXERCISES 199
145. Find i
L
and v
c
s
= 6u(t) A; (b) i
s
=
3u(t) +1 A.
64 H
16 F
4
i
L
+ v
C

i
s
146. Find i
L
and v
c
s
= 4u(t) V; (b) v
s
=
4u(t) 2 V.
25 H
4 F
5
i
L
+ v
C
v
s
147. Find i
L
and v
c
s
= 2u(t) V; (b) v
c
=
2u(t) +2 V.
5 H
3 F
6
i
L
+ v
C
v
s
P1: KDD
148. Find i
L
and v
c
s
= 2u(t) A; (b) i
s
=
2u(t) 1 A.
20 H
2 F
9
i
L
+v
C
i
s
149. Find i
L
and v
c
s
= 5u(t) V; (b) v
s
=
5u(t) 2 V.
2 H
10 F
1
i
L
+v
C
v
s
150. For the following circuit we are given that i
L
1
(0) = 2 A, i
L
2
(0) = 5 A, v
c
1
(0) = 2 V,
v
c
2
(0) = 3 V and i
s
= 2e
2t
u(t) A. (a) Write the node-voltage equations necessary to
solve this circuit. (b) Write the mesh-current equations necessary to solve this circuit.
(c) Use the node-voltage method to nd v
b
for t > 0. (d) Use the mesh-current method
to nd v
b
for t > 0.
+ v
C1
i
s
2 F
2 F
3
1
1
L
i
3 H
1
2 H
+
2
C
v
2
L
i
+
b
v
P1: KDD
EXERCISES 201
151. Find v
c
1
for t > 0 for the following circuit: (a) using the node-voltage method if v
s
=
2e
3t
u(t) V; (b) using the mesh-current method if v
s
= 2e
3t
u(t) V; (c) using the node-
voltage method if v
s
= 3 cos(2t) u(t) V; (d) using the mesh-current method if v
s
=
3 cos(2t) u(t) V; (e) using the node-voltage method if v
s
= 3u(t) 1 V; (f ) using the
mesh-current method if v
s
= 3u(t) 1 V.
v
s
4 F
3 F
3 H
6 3
2
+
1
C
v
152. Find i
L
1
for t > 0 for the following circuit: (a) using the node-voltage method if i
s
=
2e
3t
u(t) A; (b) using the mesh-current method if i
s
= 2e
3t
u(t) A; (c) using the node-
voltage method if i
s
= 3 cos(2t) u(t) A; (d) using the mesh-current method if i
s
=
3 cos(2t) u(t) A; (e) using the node-voltage method if i
s
= 2u(t) +2 A; (f ) using the
mesh-current method if i
s
= 2u(t) +2 A.
i
s
2 4
2 H
1
2
H 3 F
1
L
i
153. Find v
c
for t > 0 for the following circuit: (a) using the node-voltage method if
v
s
= 3e
5t
u(t) V; (b) using the mesh-current method if v
s
= 3e
5t
u(t) V; (c) using
the node-voltage method if v
s
= 3 sin(5t) u(t) V; (d) using the mesh-current method if
P1: KDD
v
s
= 3 sin(5t) u(t) V; (e) using the node-voltage method if v
s
= 5u(t) 2 V; (f ) using
the mesh-current method if v
s
= 5u(t) 2 V.
+
1
C
v
3 H 2 H
4 F 2 F
5
1
2
F v
s
154. Find i
L
for t > 0 for the following circuit: (a) using the node-voltage method if i
s
=
5e
3t
u(t) A; (b) using the mesh-current method if i
s
= 5e
3t
u(t) A; (c) using the node-
voltage method if i
s
= 2 sin(3t) u(t) A; (d) using the mesh-current method if i
s
=
2 sin(3t) u(t) A; (e) using the node-voltage method if i
s
= 2u(t) +3 A; (f ) using the
mesh-current method if i
s
= 2u(t) +3 A.
i
s 5
3 H 5 H
2 F 4 F 2
i
L
155. The switch has been in position a for a long time. At t = 0, the switch moves to position
b, then at t = 4, the switch moves back to position a. Find v
c
for t > 0.
b
a
t = 4 s
12 10
10 V
5 V
4
2 F
3 H
3
+
v
C
t = 0 s
P1: KDD
EXERCISES 203
156. The switches operate as indicated in the following circuit. Find v
c
for t > 0.
t = 0
3
10 V 3 A
4
5
3 F
+v
C

2 H
t = 1 s
10
157. The switch has been in position a for a long time. At t = 0, the switch moves to position
b, and then back to position a at t = 2 s. Find v
c
for t > 0.
b
a
t = 2 s
2
5 V
10 V
4
t = 0 s
3 H 5i
1 12
2
3 F
+
v
C
i
1
158. The switches operate as indicated in the following circuit. Find i
L
for t > 0.
t = 2 s
3 H
iL
5 F
b
a
t = 0
6 A
20
5
4
4 V
40
2i
1
i1
P1: KDD
159. The operational amplier shown in the following gure is ideal. Find v
o
and i
o
.
20 k v0
100 k
+12 V
12 V
i0
25 k
5 k
2 V
3 V
+
o
and i
o
.
5 k
v0
120 k
+10 V
10 V
i0
30 k
2 V
o
and i
o
.
25 k
v0
200 k
+12 V
12 V
i0
50 k
5 V
6 V

P1: KDD
EXERCISES 205
o
.
20 k
5 k
20 k
10 V
5 V
100 k
+12 V
12 V
v0
80 k
90 k

163. Find the overall gain for the following circuit if the operational amplier is ideal. Draw
a graph of v
o
versus V
s
if V
s
varies between 0 and 10 V.
v0
+12 V
12 V
10 k
20 k
5 k
VS
164. Find v
o
in the following circuit if the operational amplier is ideal.
6 k
3 k
4 V
9 V
v0
2 k
+9 V
9 V
5 V
5 k
10
3
k
+
P1: KDD
165. Find v
o
in the following circuit if the operational amplier is ideal.
v0
3 k
+12 V
12 V
3 V
10 V
1 k
5 V
6 k
+
166. Find i
o
in the following circuit if the operational ampliers are ideal.
i0
10 k
+12 V
12 V
3 k
4 k
5 V
3 V
20 k
+12 V
12 V
5 k
4 V
2 k
5 V
167. Find v
o
in the following circuit if the operational ampliers are ideal.
v0
20 k
+12 V
12 V
5 k
3 k
8 V
5 V
1 V
3 k
+12 V
12 V
1 k
3 k
+
P1: KDD
EXERCISES 207
168. Suppose the input V
s
is given as a triangular waveformas shown in the following gure.
If there is no stored energy in the following circuit with an ideal operational amplier,
nd v
o
.
VS
2 F
1
2
+12 V
12 V
v0
V
s
(V)
1
1 2 3
t
0
1
4
(s)
+

s
is given in the following gure. If there is no stored energy in the
following circuit with an ideal operational amplier, nd v
o
.

10
1 2 3
t
0
10
4
(s)
Vs
(V)

P1: KDD
VS
0 6 . F
+12 V
12 V
v0
1 M
+

s
o
.
2
Vs
(V)
2
t
(s)
1 2 0
VS
1F
+12 V
12 V
v0
250 k
+
P1: KDD
EXERCISES 209
s
o
.
V
s
(V)
0.2
t
(s)
0.2
0.25
0.5
0.75
1
V
S
0 25 . F
+12 V
12 V
v
0
50 k
+
172. The following circuit is operating in the sinusoidal steady state. Find the steady-state
expression for i
L
if i
s
= 30 cos 20t A.
4 H 3 F i
s 5
+
v
C
i
L
P1: KDD
expression for v
c
if v
s
= 10 sin 1000t V.
3 H 6 F v
s
+
v
C
i
L
5
20
expression for i
L
if i
s
= 5 cos 500t A.
2 H 15 F i
s 10
+
v
C
i
L
expression for v
c
if i
s
= 25 cos 4000t V.
16 H 1 F v
s 4
+
v
C
i
L
4
176. Design a low-pass lter with a magnitude of 10 and a cutoff frequency of 250 rad/s.
177. Design a high-pass lter with a magnitude of 20 and a cutoff frequency of 300 rad/s.
P1: KDD
EXERCISES 211
178. Design a band-pass lter a gain of 15 and pass through frequencies from 50 to 200
rad/s.
179. Design a low-pass lter with a magnitude of 5 and a cutoff frequency of 200 rad/s.
180. Design a high-pass lter with a magnitude of 10 and a cutoff frequency of 500 rad/s.
181. Design a band-pass lter a gain of 10 and pass through frequencies from 20 to 100
rad/s.
182. Suppose the operational amplier in the following circuit is ideal. (The circuit is a low-
pass rst-order Butterworth lter.) Find the magnitude of the output v
o
as a function
of frequency.
v
0
V
S
R
C
+
183. With an ideal operational amplier, the following circuit is a second-order Butterworth
low-pass lter. Find the magnitude of the output v
o
as a function of frequency.
v
0
VS
R
2
C2
R
1
C1
+
P1: KDD
184. Athird-order Butterworth low-pass lter is shown in the following circuit with an ideal
operational amplier. Find the magnitude of the output v
o
as a function of frequency.
VS
R2
R1
C2
C1
v0
C3
R3
+

Bioinstrumentation - John D. Enderle

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Bioinstrumentation - John D. Enderle

Uploaded by

Copyright:

Available Formats

P1: IML/FFX P2: IML/FFX QC: IML/FFX T1: IML

Morgan-FM MOBK036-Enderle.cls November 1, 2006 15:55

FIGURE4.2: An ideal resister with resistance R in Ohms ().

FIGURE4.8: Voltage divider rule circuit.

and solved with MATLAB as follows:

Solving with MATLAB gives

Summing the voltages around mesh 1 gives

Solution using MATLAB gives

Therefore, we can replace the voltage source and R

FIGURE 6.2: The open circuit voltage, V

The sum of currents leaving the node is

. Recall that when a circuit is at steady state, an

, we replace all inductors by short circuits and capacitors by open circuits

. Moreover, since the capacitor voltage cannot change in

. Fromthis circuit we solve for all desired initial conditions

, the capacitor is replaced by an open circuit and the inductor by a short

) = 0.02 A. Because voltage across a capacitor and

and the capacitors with

as shown in the following

with the inductors replaced as short circuits and the

and the capacitor as a voltage source whose value

) = 8 V. Ohms law gives i

) = 10 V. KCL gives the current through the other inductor as i

) = 0.8 +0.5 = 1.3 A.

Using the current divider rule and Ohms law, we have v

) = 40 V. Note that voltage cannot

), and all other voltages and currents

) we use the solution for v

and since the noninverting terminal is connected to ground, v

As A goes to innity, the previous equation goes to

We can add additional source resistor inputs, so that in general

and greater than V

, that is current lags behind

, that is voltage lags behind

FIGURE12.3: Phasor and impedance equivalent circuit for Fig. 12.2.

= 50 j +18.8 + j 6.8 = 18.8 j 43.2

The steady-state solution is

19. Find I in the following circuit.

23. Find the equivalent resistance R

34. Use the node-voltage method to determine v

40. Use the node-voltage method to determine v

60. Use the superposition method to nd v

62. Find the Th evenin equivalent with respect to terminals a and b.

95. For the following circuit, I

169. Suppose the input V

170. Suppose the input V

You might also like