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Digital Logic Design No 6 Counters and Registers
Digital Logic Design No 6 Counters and Registers
Q
0
Q
1
0
0
1
0
0
1
1
1
0
0
F
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3-bit ripple binary counter using JK
flip flops (asynchronous counters)
J
K
J
K
Q
1
Q
1
Q
0
Q
0
1
CP
J
K
Q
2
Q
2
Q
0
Q
0
CP
Q
1
Q
2
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Simple Registers
No external gates.
!
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4-bit register with parallel load
Load
Clear
CP
"
"
"
"
#
#
#
#
I
1
I
2
I
3
I
4
A
1
A
2
A
3
A
4
((ontrol Signal)
F
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Register "it) *arallel +oa# ,sing - .lip
.lops
!
!
!
!
Load
Clear
CP
I
1
I
2
I
3
I
4
A
1
A
2
A
3
A
4
$oa% A
1
& $oa% I
1
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'sing #egisters to i(ple(ent "e)uential
Circuits
/
A se01ential &ir&1it ma% &onsist o2 a register (memor%) an# a
&om!inational &ir&1it.
Nextstate $al1e
/
3)e external inp1ts an# present states o2 t)e register #etermine
t)e next states o2 t)e register an# t)e external o1tp1ts4 t)ro1g)
t)e &om!inational &ir&1it.
/
3)e &om!inational &ir&1it ma% !e implemente# !% an% o2 t)e
met)o#s &o$ere# in 5S6 &omponents an# *rogramma!le
+ogi& -e$i&es.
Combinational
Circuit
Register
Inputs
Outputs
Clock
Pulse
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,sing Registers to implement
Se01ential (ir&1its
/
*+a(ple 1: -esign a Se01ential (ir&1it ")ose state ta!le is gi$en !elo" 1sing t"o 2lip2lops.
A
1
+
7 8 m(449) 7 A
1
. x
:
A
;
+
7 8 m(14;4<49) 7 A
;
.x: + A
:
;
.x 7 A
;
x
% 7 8 m(=4>) 7 A
;
.x
Present
State
A
1
A
2
Input
Next
State
A
1
+
A
2
+
x
Output
y
"tate ,able
1 0 0 1 1 1
0 1 1 0 1 1
0 1 0 1 0 1
0 0 1 0 0 1
1 0 0 1 1 0
0 1 0 0 1 0
0 1 0 1 0 0
0 0 0 0 0 0
A
1
- +.
A
2
+
x
y
$ogic !iagra(
"e)uential Circuit I(ple(entation
A1
A2
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,sing Registers to implement Se01ential
(ir&1its
/
Example ;: Repeat example 14 !1t 1se a R?5 @Register.
A%%ress /utputs
1 2 3 1 2 3
A
1
A
2
+ A
1
A
2
y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 1 0
0 1 1 0 0 1
1 0 0 1 0 0
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 0 0 1
R?5 tr1t) ta!le
1 1
2 2
3 3
A
1
A
2
8 X 3
ROM
!
Sequential circuit using a register and a ROM
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Serial 6NASerial ?1t S)i2t Registers
"
Accepts #ata seriall! $ one bit at a time an# also
pro#uces output seriall!%
! !
!
!
C$K
"erial Input
("I)
3
"erial /utput
("/)
"hift #egister
F
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"erial In1"erial /ut "hift #egisters
/
Appli&ation: Serial trans2er o2 #ata 2rom one register to anot)er.
S)i2t register A S)i2t register B
S?
S? S6
S6
(*
(lo&'
S)i2t (ontrol
(lo&'
&or#time
1011 0010
3
1
3
;
3
=
3
4
(*
S)i2t (ontrol
F
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"erial In1"erial /ut "hift #egisters
Serialtrans2er example.
3iming *1lse
6nitial $al1e
A2ter 3
1
A2ter 3
2
A2ter 3
=
A2ter 3
4
S)i2t Register A
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
0
1
1
S)i2t Register B
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
Serial o1tp1t o2 B
0
1
0
0
1
F
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Q
-
Q
-
Q
-
Q
-
'1
()*
0 1 2 3
'1
()*
0 1 2 3
'1
()*
0 1 2 3
'1
()*
0 1 2 3
A
=
A
;
A
4
A
1
6
=
6
;
6
4
6
1
Serial
inp1t 2or
s)i2tle2t
Serial
inp1t 2or
s)i2trig)t
*arallel inp1ts
*arallel o1tp1ts
(lear
(+K
S
1
S
0
2i%irectional "hift #egisters
J K
K K K
(o1nt
ena!le
(*
3o
next
stage
J K Q(t+1)
0
0
1
1
0
1
0
1
Q(t)
0
1
Q(t)
4-bit synchronous binary counter
1
F
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A
4
A
3
A
2 A
1
CP
1
,
, ,
,
'P
!o3n
4-bit up-down binary counter
3o
Next
stage
3 Q(t+1)
0
1
Q(t)
Q(t)
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1 1 0 0 1 1 0 0 1
0 1 0 0 0 0 0 0 1
0 1 1 1 1 1 1 1 0
0 1 0 0 0 0 1 1 0
0 1 1 0 0 1 0 1 0
0 1 0 0 0 0 0 1 0
0 1 1 1 0 1 1 0 0
0 1 0 0 0 0 1 0 0
0 1 1 0 0 1 0 0 0
0 1 0 0 0 0 0 0 0
% 3Q
1
3Q
;
3Q
4
3Q
G
Q
1
Q
;
Q
4
Q
G
?1tp1t (arr% .lip2lop inp1ts (o1nt Se01en&e
,sing Kmaps4 "e get
3Q
1
71
3Q
;
7 Q
A
G
Q
1
3Q
4
7 Q
;
Q
1
3Q
G
7 Q
G
Q
1
+ Q
4
Q
;
Q
1
% 7 Q
G
Q
1
Q(t) Q(t+1) 3
0
0
1
1
0
1
0
1
0
1
1
0
!esign a 2C! counter using , flip-flops
*+citation table for a 2C! counter
4o3 logic %iagra( can be %ra3n for 2C! synchronous
counter
F
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CP
Q
1
Q
;
Q
4
Q
G
Q
1
Q
;
Q
4
Q
G
, , , ,
1
3Q
1
71
3Q
;
7 Q
A
G
Q
1
3Q
4
7 Q
;
Q
1
3Q
G
7 Q
G
Q
1
+ Q
4
Q
;
Q
1
% 7 Q
G
Q
1
F
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J
J
J
J
K
K
K
K
Count
+oa#
A
4
A
3
A
2
A
1
I
4
I
3
I
2
I
1
Clear
CP Carr!
out
Counters 3ith Parallel $oa%