1

CSC 242 :-Computer-Aided Systems Design

and Verification

Assignment=5
Lecture instructor: Submitted By:
Dr. Behnam Arad Chintan G Govani
Nikunj K Patel
Contribution:

Project Partner Name Percentage of contribution
Chintan Govani 50%
Nikunj Patel 50%

Date of Submission: - May 11, 2009.
Department of Electrical and Electronic Engineering
California State University
Sacramento
2

Table of contents

1. Status Report 3
2. Block Diagram for Design 4

3. Block Diagram for Test bench 5

4. Source code of DUT
(a) Top Module 6
(b) Interface 7
(c) DMA Client Module 8
(d) Arbiter Module 11
(e) Memory module 14

5. Source code for Testbench
Program for DUT 19

6. Simulation results 24





3

1. Status Report

This project is functionally working perfect.

Class/Object was successfully implemented and the test cases of DUT
were validated using constrained-based randomization to generate
test vectors (varying transaction type, size, width, data etc.).

Mod-ports, clocking blocks and program were successfully
implemented.

Also, we have done functionality coverage with cover-point like
width, size and type. And we are getting the functionality coverage
of 100%.

After implementing all these (Class/Object, Mod-ports, Clocking-
block, program and Functionality Coverage), simulation results for
all transfers are coming correct.


4


2. Block Diagram for Design

TESTBENCH
(Program)
[31:0]dma_wdata
CLIENT
[0,1,2,3]
ARBITER
MEMORY
SEL
CPU_PROMPT
CPU_TYPE
CPU_WIDTH
CPU_ADDR
CPU_DATA
CPU_SIZE
CLOCK RESET
CLOCK RESET
CLOCK
RESET
[31:0]DMA_ADDR
[31:0]DMA_WDATA
[31:0]DMA_RDATA
DMA_COMPLETE
[2:0]DMA_WIDTH
[3:0]DMA_SIZE
DMA_TRANS
DMA_TYPE
INTERFACE (dbus)
R
e
q
[
3
:
0
]
G
n
t
[
3
:
0
]
CLOCK
RESET
S
i
z
e
[
3
:
0
]
Master[1:0]

5

3. Block Diagram of Testbench



RESET
SEL
CPU_PROMPT
CPU_SIZE
CPU-DATA
CPU_WIDTH
BUSY
CONFIG_DONE
CPU_TYPE
CPU_ADDR
PROGRAM (client_test)
CLASS(config_client)
Bit RESET
randc bit CPU_TYPE
Logic [31:0]CPU_ADDR
randc bit[2:0]CPU_WIDTH
Bit CPU_PROMPT
rand bit [31:0]CPU_DATA
rand logic [4:0]CPU_SIZE
Logic[1:0]SEL








6

4. Source Code for DUT
(a) Top Module


`include "client0.sv"
`include "arb.sv"
`include "memory.sv"
`include "DMA_MEM.sv"
`include "test_bench.sv"

module top();

wire [3:0]req;
wire [3:0]gnt;
wire [1:0]master;
wire [31:0]dma_wdata;
wire done;
wire [3:0]config_done;
wire [3:0]busy;
wire [31:0]DMA_RDATA;
wire [63:0]cov;

assign DMA_RDATA=dbus.DMA_RDATA;

bit CLOCK;
always #5 CLOCK=~CLOCK;

DMA_MEM dbus(CLOCK);

client0 #(2'b00) c0
(dbus.cli,CLOCK,RESET,gnt[0],req[0],config_done[0],busy[0]);

client0 #(2'b01) c1
(dbus.cli,CLOCK,RESET,gnt[1],req[1],config_done[1],busy[1]);

client0 #(2'b10) c2
(dbus.cli,CLOCK,RESET,gnt[2],req[2],config_done[2],busy[2]);

client0 #(2'b11) c3
(dbus.cli,CLOCK,RESET,gnt[3],req[3],config_done[3],busy[3]);

memory m1 (dbus.mem,CLOCK,RESET,dma_wdata,done);

arb n1(CLOCK,RESET,req,gnt,master,dbus.DMA_SIZE,done);

client_test p1(dbus.prog,RESET,config_done,busy,cov);

endmodule


7

(b) Interface between DMA Client and Memory



interface DMA_MEM (input logic CLOCK);

logic [31:0]DMA_ADDR;
logic DMA_TRANS;
logic [2:0]DMA_WIDTH;
logic [4:0]DMA_SIZE;
logic DMA_TYPE;
logic [31:0]DMA_WDATA;
logic [31:0]DMA_RDATA;
logic DMA_COMPLETE;

logic CPU_TYPE;
logic [31:0]CPU_ADDR;
logic[2:0] CPU_WIDTH;
logic[4:0] CPU_SIZE;
logic CPU_PROMPT;
logic [1:0]SEL;
logic [31:0]CPU_DATA;
logic STATUS;

modport mem(input
DMA_ADDR,DMA_TRANS,DMA_WIDTH,DMA_SIZE,DMA_TYPE,DMA_WDATA,
output DMA_COMPLETE,DMA_RDATA);

modport cli( input CPU_TYPE,
CPU_ADDR,
CPU_WIDTH,
CPU_SIZE,
CPU_PROMPT,
SEL,CPU_DATA,
output
DMA_ADDR,DMA_TRANS,DMA_WIDTH,DMA_SIZE,DMA_TYPE,DMA_WDATA,STATUS,
input DMA_COMPLETE,DMA_RDATA);

clocking cb @(posedge CLOCK);
output CPU_TYPE;
output CPU_ADDR;
output CPU_WIDTH;
output CPU_SIZE;
output CPU_PROMPT;
output CPU_DATA;
output SEL;
input STATUS;
endclocking;

modport prog(clocking cb);

endinterface


8




(c) DMA Client Module

module client0( DMA_MEM dbus,
input bit CLOCK,RESET,
input GRANT,
output logic REQ,output logic config_done,output logic busy
);
parameter ID=2'b00;

logic cpu_type;
logic [31:0]cpu_addr;
logic [2:0]cpu_width;
logic [4:0]cpu_size;
logic cpu_prompt;
logic sel;
logic grant;
logic [31:0]cpu_data;



enum logic
[2:0]{idle,config,wait_config,wait_grant,address_phase,data_phase}state,ne
xtstate;



always @ (posedge CLOCK,negedge RESET)
begin
if(!RESET)
state<=idle;
else
state<=nextstate;
end

always_comb
begin
case(state)
idle:
if(dbus.SEL==ID)
nextstate=config;
else
nextstate=idle;

config:
nextstate<=wait_config;

wait_config:
if(dbus.CPU_PROMPT==1)
nextstate=wait_grant;
else
9

nextstate=wait_config;
wait_grant:
if(GRANT==1)
nextstate=address_phase;
else
nextstate=wait_grant;

address_phase:

nextstate=data_phase;

data_phase:
if(dbus.DMA_SIZE==5'b00001)
begin
nextstate=idle;
end
else
nextstate=data_phase;


endcase
end

always_ff @ (posedge CLOCK)
begin
case(state)
idle:
begin
REQ<=0;
config_done<=1'b0;
busy<=1'b0;
end

config:
begin
cpu_type<=dbus.CPU_TYPE;
cpu_addr<=dbus.CPU_ADDR;
cpu_width<=dbus.CPU_WIDTH;
cpu_size<=dbus.CPU_SIZE;
cpu_data<=dbus.CPU_DATA;
config_done<=1'b1;
busy<=1'b1;
end

wait_config:
begin
config_done<=1'b1;
busy<=1'b1;

if(dbus.CPU_PROMPT==1) begin
REQ<=1'b1;
dbus.STATUS<=1'b1; end
else begin
REQ<=1'b0;
10

dbus.STATUS<=1'b0; end
end

wait_grant:
begin

REQ<=1;
busy<=1'b1;
config_done<=1'b1;
end

address_phase:
begin
REQ<=1'b0;
busy<=1'b1;
config_done<=1'b1;

dbus.DMA_WDATA<=32'bz;
dbus.DMA_TRANS<=1'b1;
dbus.DMA_ADDR<=cpu_addr;
dbus.DMA_WIDTH<=cpu_width;
dbus.DMA_SIZE<=cpu_size;
dbus.DMA_TYPE<=cpu_type;
end

data_phase:
begin
dbus.DMA_TRANS<=1'b0;
config_done<=1'b1;
busy<=1'b1;
REQ<=1'b0;

if(cpu_type)
dbus.DMA_WDATA<=cpu_data;
else
dbus.DMA_WDATA<=32'bz;

if (dbus.DMA_COMPLETE)
dbus.DMA_SIZE<=dbus.DMA_SIZE-1;
else
dbus.DMA_SIZE<=dbus.DMA_SIZE;

end
endcase
end

endmodule







11



(d) Arbiter Module


module arb( input bit CLOCK,
input bit RESET,
input logic [3:0]req,
output logic [3:0]gnt,
output logic [1:0] master,input [4:0]size,input done);

logic [1:0]bm;
assign master=bm;

enum logic[2:0] {idle,bm0,bm1,bm2,bm3}cs,ns;

always_ff@(posedge CLOCK or negedge RESET)
begin
if(!RESET)
cs<=idle;
else
cs<=ns;
end

always_comb
begin
case(cs)
idle:
if(!RESET)
ns=idle;
else
if(req[0])
ns=bm0;
else if(req[1])
ns=bm1;
else if(req[2])
ns=bm2;
else if(req[3])
ns=bm3;
else
ns-idle;

bm0:
if(size==5'b00001 && done==1'b1)
begin
if (req[1])
ns=bm1;
else if(req[2])
ns=bm2;
else if(req[3])
ns=bm3;
else if(req[0])
ns=bm0;
else
12

ns=bm0;
end
else
ns=bm0;

bm1:
if(size==5'b00001 && done==1'b1)
begin
if(req[2])
ns=bm2;
else if(req[3])
ns=bm3;
else if(req[0])
ns=bm0;
else if(req[1])
ns=bm1;
else
ns=bm0;
end
else
ns=bm1;

bm2:
if(size==5'b00001 && done==1'b1)
begin
if(req[3])
ns=bm3;
else if(req[0])
ns=bm0;
else if(req[1])
ns=bm1;
else if(req[2])
ns=bm2;
else
ns=bm0;
end
else
ns=bm2;

bm3:
if(size==5'b00001 && done==1'b1)
begin
if(req[0])
ns=bm0;
else if(req[1])
ns=bm1;
else if(req[2])
ns=bm2;
else if(req[3])
ns=bm3;
else
ns=bm0;
end
else
ns=bm3;
endcase

13

end

always @ (posedge CLOCK)
begin
case(cs)

idle:
begin
gnt[0]=0;
gnt[1]=0;
gnt[2]=0;
gnt[3]=0;
bm=2'bzz;
end

bm0:
begin
gnt[0]=1;
gnt[1]=0;
gnt[2]=0;
gnt[3]=0;
bm=2'b00;
end

bm1: begin
gnt[0]=0;
gnt[1]=1;
gnt[2]=0;
gnt[3]=0;
bm=2'b01;
end

bm2: begin
gnt[0]=0;
gnt[1]=0;
gnt[2]=1;
gnt[3]=0;
bm=2'b10;
end

bm3: begin
gnt[0]=0;
gnt[1]=0;
gnt[2]=0;
gnt[3]=1;
bm=2'b11;
end
endcase

end

endmodule




14

(e) Memory module



module memory (DMA_MEM dbus,input bit CLOCK,RESET,output logic
[31:0]dma_wdata,output logic done);

logic [7:0]mem[255:0];
logic [31:0]dma_addr;
logic dma_trans;
logic [2:0]dma_width;
logic dma_type;
logic [31:0]temp;
logic [4:0]dma_size;
logic [4:0]size;


enum logic [1:0]{idle,read_more,write_more} cs,ns;

always_ff @ (posedge CLOCK,negedge RESET)
begin
if(!RESET)
cs<=idle;
else
cs<=ns;
end

always_comb
begin
case(cs)

idle:
begin
done=1'b0;
if(dbus.DMA_TRANS)
if(dbus.DMA_TYPE)
ns=write_more;
else
ns=read_more;
else
ns=idle;
end



write_more:
if(dbus.DMA_SIZE==5'b00001)
begin
ns=idle;
done=1'b1;
end
else begin
done=1'b0;
15

ns=write_more;
end


read_more:
if(dbus.DMA_SIZE==5'b00001)
begin
ns=idle;
done=1'b1;
end
else
begin
ns=read_more;
done=1'b0;
end

endcase
end

always_comb
begin

case(cs)

idle:
begin
mem[0]=8'h00;
mem[1]=8'h01;
mem[2]=8'h02;
mem[3]=8'h03;
mem[4]=8'h04;
mem[5]=8'h05;
mem[6]=8'h06;
mem[7]=8'h07;
mem[8]=8'h08;
mem[9]=8'h09;

mem[10]=8'h10;
mem[11]=8'h11;
mem[12]=8'h12;
mem[13]=8'h13;
mem[14]=8'h14;
mem[15]=8'h15;
mem[16]=8'h16;
mem[17]=8'h17;
mem[18]=8'h18;
mem[19]=8'h19;
mem[20]=8'h20;
mem[21]=8'h21;
mem[22]=8'h22;
mem[23]=8'h23;
mem[24]=8'h24;
mem[25]=8'h25;
mem[26]=8'h39;
16

mem[27]=8'h40;
mem[28]=8'h41;
mem[29]=8'h42;
mem[30]=8'h43;
mem[31]=8'h44;
mem[32]=8'h45;
mem[33]=8'h46;
mem[34]=8'h47;

dbus.DMA_COMPLETE=1'b0;
dbus.DMA_RDATA=32'hz;
dma_wdata=32'bz;
temp=32'b0;

if(dbus.DMA_TRANS)
begin
dma_width=dbus.DMA_WIDTH;
dma_size=dbus.DMA_SIZE;
dma_addr=dbus.DMA_ADDR;
size=5'b00000;
end
else
begin
dma_width=3'bz;
dma_size=5'bz;
dma_addr=32'bz;
end

end


write_more:

begin
temp=dma_addr;

if(dma_width==3'b100)
begin
mem[temp]=dbus.DMA_WDATA[7:0];
mem[temp+1]=dbus.DMA_WDATA[15:8];
mem[temp+2]=dbus.DMA_WDATA[23:16];
mem[temp+3]=dbus.DMA_WDATA[31:24];
dma_wdata[7:0]=mem[temp];
dma_wdata[15:8]=mem[temp+1];
dma_wdata[23:16]=mem[temp+2];
dma_wdata[31:24]=mem[temp+3];
if(dbus.DMA_SIZE > 5'b00001)
dma_addr=dma_addr+4;
else
dma_addr=32'bz;
end
else if(dma_width==3'b010)
begin
mem[temp]=dbus.DMA_WDATA[7:0];
17

mem[temp+1]=dbus.DMA_WDATA[15:8];
dma_wdata[7:0]=mem[temp];
dma_wdata[15:8]=mem[temp+1];
dma_wdata[31:16]=16'h0;
if(dbus.DMA_SIZE > 5'b00001)
dma_addr=dma_addr+2;
else
dma_addr=32'bz;

end
else
begin
mem[temp]=dbus.DMA_WDATA[7:0];
dma_wdata[7:0]=mem[temp];
dma_wdata[31:8]=24'h0;
if(dbus.DMA_SIZE > 5'b00001)
dma_addr=dma_addr+1;
else
dma_addr=32'bz;
end

dbus.DMA_COMPLETE=1'b1;
end


read_more:
begin

temp=dma_addr;
dbus.DMA_COMPLETE=1'b1;
dma_wdata<=32'bz;

if(dma_width==3'b100)
begin
dbus.DMA_RDATA[7:0]=mem[temp];
dbus.DMA_RDATA[15:8]=mem[temp+1];
dbus.DMA_RDATA[23:16]=mem[temp+2];
dbus.DMA_RDATA[31:24]=mem[temp+3];
if(dbus.DMA_SIZE > 5'b00001)

dma_addr=dma_addr+4;
else
dma_addr=32'bz;
end
else if(dma_width==3'b010)
begin
dbus.DMA_RDATA[7:0]=mem[temp];
dbus.DMA_RDATA[15:8]=mem[temp+1];
dbus.DMA_RDATA[31:16]=16'h0;
if(dbus.DMA_SIZE > 5'b00001)
dma_addr=dma_addr+2;
else
dma_addr=32'bz;
end
18

else if(dma_width==3'b001)
begin
dbus.DMA_RDATA[7:0]=mem[temp];
dbus.DMA_RDATA[31:8]=24'h0;
if(dbus.DMA_SIZE > 5'b00001)
dma_addr=dma_addr+1;
else
dma_addr=32'bz;
end
else begin
dbus.DMA_RDATA[31:0]=32'b1;
dma_addr=32'bz;
end
end
endcase
end




endmodule
































19

5. Source code for Testbench

Program for DUT



program automatic client_test(DMA_MEM dbus,output bit RESET,input
[3:0]config_done,input [3:0]busy,output real cov);


class config_client;
bit RESET;
randc bit CPU_TYPE;
logic [31:0]CPU_ADDR;
randc bit [2:0] CPU_WIDTH;
rand logic [4:0] CPU_SIZE;
bit CPU_PROMPT;
rand bit [31:0]CPU_DATA;
logic [1:0]SEL;

constraint data_width {
(CPU_WIDTH inside
{3'b001,3'b010,3'b100});
CPU_SIZE > 5'b00000;
}
covergroup Cov_All;

coverpoint this.CPU_WIDTH {ignore_bins unwanted= {0,3,5,6,7};}
coverpoint this.CPU_SIZE { option.auto_bin_max = 2; }
coverpoint this.CPU_TYPE;

endgroup

function automatic new(input bit RESET,
input logic CPU_TYPE,
input logic [31:0]CPU_ADDR,
input logic[2:0] CPU_WIDTH,
input logic[4:0] CPU_SIZE,
input logic CPU_PROMPT,
input logic [1:0]SEL,
input logic [31:0]CPU_DATA);


this.RESET=RESET;
this.CPU_TYPE=CPU_TYPE;
this.CPU_ADDR=CPU_ADDR;
this.CPU_WIDTH=CPU_WIDTH;
this.CPU_SIZE=CPU_SIZE;
this.CPU_PROMPT=CPU_PROMPT;
this.CPU_DATA=CPU_DATA;
this.SEL=SEL;
Cov_All=new();
20

endfunction

endclass

task give;
RESET=c1.RESET;
dbus.cb.CPU_TYPE<=c1.CPU_TYPE;
dbus.cb.CPU_ADDR<=c1.CPU_ADDR;
dbus.cb.CPU_WIDTH<=c1.CPU_WIDTH;
dbus.cb.CPU_SIZE<=c1.CPU_SIZE;
dbus.cb.CPU_PROMPT<=c1.CPU_PROMPT;
dbus.cb.SEL<=c1.SEL;
dbus.cb.CPU_DATA<=c1.CPU_DATA;

endtask

config_client c1;

initial
begin

cov = 0.0;

c1=new(1'b0,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'bz);
give;

//wait(config_done[0])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b01,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;


wait(config_done[1])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b10,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;


wait(config_done[2])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b11,32'hz);
21

assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

wait(config_done[3] && !busy[0])
c1=new(1'b1,1'bz,32'd1,3'bz,5'bz,1'b1,2'b00,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

wait(config_done[0] && !busy[1])
c1=new(1'b1,1'bz,32'd1,3'bz,5'bz,1'b1,2'b01,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

wait(config_done[1] && !busy[2])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b10,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

wait(config_done[2] && !busy[3])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b11,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

wait(config_done[3] && !busy[0])
22

c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b00,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

wait(config_done[3] && !busy[1])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b01,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

wait(config_done[1] && !busy[2])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b10,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;


wait(config_done[2] && !busy[3])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b11,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

wait(config_done[3] && !busy[0])
23

c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b00,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

wait(config_done[0] && !busy[2])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b10,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;

wait(config_done[2] && !busy[1])
c1=new(1'b1,1'bz,32'b1,3'bz,5'bz,1'b1,2'b01,32'hz);
assert (c1.randomize());
c1.Cov_All.sample();
cov = $get_coverage;
give;

repeat (3) @dbus.cb;
c1=null;
c1=new(1'b1,1'bz,32'dz,3'bz,5'bz,1'b0,2'bzz,32'hz);
give;


end

initial
#3000 $finish;
endprogram












24

6. Simulation Results

Chronologic VCS simulator copyright 1991-2005
Contains Synopsys proprietary information.
Compiler version Y-2006.06-SP1; Runtime version Y-2006.06-SP1; May 11
13:43 2009

0 sel=xx prompt=x req=xxxx grant=xxxx trans=x type=x
addr=0 width=xxx size=x rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=xx cov=44
5 sel=01 prompt=1 req=0000 grant=0000 trans=x type=x
addr=0 width=xxx size=x rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=zz cov=44
25 sel=10 prompt=1 req=0000 grant=0000 trans=x type=x
addr=0 width=xxx size=x rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=zz cov=61
35 sel=10 prompt=1 req=0010 grant=0000 trans=x type=x
addr=0 width=xxx size=x rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=zz cov=61
55 sel=11 prompt=1 req=0110 grant=0010 trans=x type=x
addr=0 width=xxx size=x rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=61
75 sel=11 prompt=1 req=0100 grant=0010 trans=1 type=0
addr=0 width=001 size=19 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=61
85 sel=00 prompt=1 req=1100 grant=0010 trans=0 type=0
addr=1 width=001 size=19 rdata=00000001 wdata=zzzzzzzz comp=1bm=01 cov=89
95 sel=00 prompt=1 req=1100 grant=0010 trans=0 type=0
addr=2 width=001 size=18 rdata=00000002 wdata=zzzzzzzz comp=1bm=01 cov=89
105 sel=00 prompt=1 req=1100 grant=0010 trans=0 type=0
addr=3 width=001 size=17 rdata=00000003 wdata=zzzzzzzz comp=1bm=01 cov=89
115 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=4 width=001 size=16 rdata=00000004 wdata=zzzzzzzz comp=1bm=01 cov=89
125 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=5 width=001 size=15 rdata=00000005 wdata=zzzzzzzz comp=1bm=01 cov=89
135 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=6 width=001 size=14 rdata=00000006 wdata=zzzzzzzz comp=1bm=01 cov=89
145 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=7 width=001 size=13 rdata=00000007 wdata=zzzzzzzz comp=1bm=01 cov=89
155 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=8 width=001 size=12 rdata=00000008 wdata=zzzzzzzz comp=1bm=01 cov=89
165 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=9 width=001 size=11 rdata=00000009 wdata=zzzzzzzz comp=1bm=01 cov=89
175 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=10 width=001 size=10 rdata=00000010 wdata=zzzzzzzz comp=1bm=01 cov=89
185 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=11 width=001 size=9 rdata=00000011 wdata=zzzzzzzz comp=1bm=01 cov=89
195 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=12 width=001 size=8 rdata=00000012 wdata=zzzzzzzz comp=1bm=01 cov=89
205 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=13 width=001 size=7 rdata=00000013 wdata=zzzzzzzz comp=1bm=01 cov=89
215 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=14 width=001 size=6 rdata=00000014 wdata=zzzzzzzz comp=1bm=01 cov=89
225 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=15 width=001 size=5 rdata=00000015 wdata=zzzzzzzz comp=1bm=01 cov=89
235 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=16 width=001 size=4 rdata=00000016 wdata=zzzzzzzz comp=1bm=01 cov=89
245 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
25

addr=17 width=001 size=3 rdata=00000017 wdata=zzzzzzzz comp=1bm=01 cov=89
255 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=18 width=001 size=2 rdata=00000018 wdata=zzzzzzzz comp=1bm=01 cov=89
265 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=19 width=001 size=1 rdata=00000019 wdata=zzzzzzzz comp=1bm=01 cov=89
275 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=89
285 sel=01 prompt=1 req=1101 grant=0100 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=89
305 sel=01 prompt=1 req=1001 grant=0100 trans=1 type=0
addr=0 width=001 size=4 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=89
315 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=1 width=001 size=4 rdata=00000001 wdata=zzzzzzzz comp=1bm=10 cov=89
325 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=2 width=001 size=3 rdata=00000002 wdata=zzzzzzzz comp=1bm=10 cov=89
335 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=3 width=001 size=2 rdata=00000003 wdata=zzzzzzzz comp=1bm=10 cov=89
345 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=4 width=001 size=1 rdata=00000004 wdata=zzzzzzzz comp=1bm=10 cov=89
355 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=89
365 sel=10 prompt=1 req=1011 grant=1000 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=11 cov=89
385 sel=10 prompt=1 req=0011 grant=1000 trans=1 type=0
addr=0 width=001 size=21 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=11 cov=89
395 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=1 width=001 size=21 rdata=00000001 wdata=zzzzzzzz comp=1bm=11 cov=89
405 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=2 width=001 size=20 rdata=00000002 wdata=zzzzzzzz comp=1bm=11 cov=89
415 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=3 width=001 size=19 rdata=00000003 wdata=zzzzzzzz comp=1bm=11 cov=89
425 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=4 width=001 size=18 rdata=00000004 wdata=zzzzzzzz comp=1bm=11 cov=89
435 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=5 width=001 size=17 rdata=00000005 wdata=zzzzzzzz comp=1bm=11 cov=89
445 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=6 width=001 size=16 rdata=00000006 wdata=zzzzzzzz comp=1bm=11 cov=89
455 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=7 width=001 size=15 rdata=00000007 wdata=zzzzzzzz comp=1bm=11 cov=89
465 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=8 width=001 size=14 rdata=00000008 wdata=zzzzzzzz comp=1bm=11 cov=89
475 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=9 width=001 size=13 rdata=00000009 wdata=zzzzzzzz comp=1bm=11 cov=89
485 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=10 width=001 size=12 rdata=00000010 wdata=zzzzzzzz comp=1bm=11 cov=89
495 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=11 width=001 size=11 rdata=00000011 wdata=zzzzzzzz comp=1bm=11 cov=89
505 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=12 width=001 size=10 rdata=00000012 wdata=zzzzzzzz comp=1bm=11 cov=89
515 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=13 width=001 size=9 rdata=00000013 wdata=zzzzzzzz comp=1bm=11 cov=89
525 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=14 width=001 size=8 rdata=00000014 wdata=zzzzzzzz comp=1bm=11 cov=89
535 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
26

addr=15 width=001 size=7 rdata=00000015 wdata=zzzzzzzz comp=1bm=11 cov=89
545 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=16 width=001 size=6 rdata=00000016 wdata=zzzzzzzz comp=1bm=11 cov=89
555 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=17 width=001 size=5 rdata=00000017 wdata=zzzzzzzz comp=1bm=11 cov=89
565 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=18 width=001 size=4 rdata=00000018 wdata=zzzzzzzz comp=1bm=11 cov=89
575 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=19 width=001 size=3 rdata=00000019 wdata=zzzzzzzz comp=1bm=11 cov=89
585 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=20 width=001 size=2 rdata=00000020 wdata=zzzzzzzz comp=1bm=11 cov=89
595 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=21 width=001 size=1 rdata=00000021 wdata=zzzzzzzz comp=1bm=11 cov=89
605 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=11 cov=89
615 sel=11 prompt=1 req=0111 grant=0001 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=89
635 sel=11 prompt=1 req=0110 grant=0001 trans=1 type=1
addr=0 width=100 size=5 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=89
645 sel=11 prompt=1 req=1110 grant=0001 trans=0 type=1
addr=1 width=100 size=5 rdata=zzzzzzzz wdata=52accc7e comp=1bm=00 cov=89
655 sel=11 prompt=1 req=1110 grant=0001 trans=0 type=1
addr=5 width=100 size=4 rdata=zzzzzzzz wdata=52accc7e comp=1bm=00 cov=89
665 sel=11 prompt=1 req=1110 grant=0001 trans=0 type=1
addr=9 width=100 size=3 rdata=zzzzzzzz wdata=52accc7e comp=1bm=00 cov=89
675 sel=11 prompt=1 req=1110 grant=0001 trans=0 type=1
addr=13 width=100 size=2 rdata=zzzzzzzz wdata=52accc7e comp=1bm=00 cov=89
685 sel=11 prompt=1 req=1110 grant=0001 trans=0 type=1
addr=17 width=100 size=1 rdata=zzzzzzzz wdata=52accc7e comp=1bm=00 cov=89
695 sel=11 prompt=1 req=1110 grant=0001 trans=0 type=1
addr=0 width=100 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=89
705 sel=00 prompt=1 req=1110 grant=0010 trans=0 type=1
addr=0 width=100 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=89
725 sel=00 prompt=1 req=1100 grant=0010 trans=1 type=0
addr=0 width=001 size=6 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=89
735 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=1 width=001 size=6 rdata=00000001 wdata=zzzzzzzz comp=1bm=01 cov=89
745 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=2 width=001 size=5 rdata=00000002 wdata=zzzzzzzz comp=1bm=01 cov=89
755 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=3 width=001 size=4 rdata=00000003 wdata=zzzzzzzz comp=1bm=01 cov=89
765 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=4 width=001 size=3 rdata=00000004 wdata=zzzzzzzz comp=1bm=01 cov=89
775 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=5 width=001 size=2 rdata=00000005 wdata=zzzzzzzz comp=1bm=01 cov=89
785 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=6 width=001 size=1 rdata=00000006 wdata=zzzzzzzz comp=1bm=01 cov=89
795 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=89
805 sel=01 prompt=1 req=1101 grant=0100 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=100
825 sel=01 prompt=1 req=1001 grant=0100 trans=1 type=0
addr=0 width=001 size=7 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=100
835 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
27

addr=1 width=001 size=7 rdata=00000001 wdata=zzzzzzzz comp=1bm=10 cov=100
845 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=2 width=001 size=6 rdata=00000002 wdata=zzzzzzzz comp=1bm=10 cov=100
855 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=3 width=001 size=5 rdata=00000003 wdata=zzzzzzzz comp=1bm=10 cov=100
865 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=4 width=001 size=4 rdata=00000004 wdata=zzzzzzzz comp=1bm=10 cov=100
875 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=5 width=001 size=3 rdata=00000005 wdata=zzzzzzzz comp=1bm=10 cov=100
885 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=6 width=001 size=2 rdata=00000006 wdata=zzzzzzzz comp=1bm=10 cov=100
895 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=7 width=001 size=1 rdata=00000007 wdata=zzzzzzzz comp=1bm=10 cov=100
905 sel=zz prompt=0 req=1011 grant=0100 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=100
915 sel=10 prompt=1 req=1011 grant=1000 trans=0 type=0
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=11 cov=100
935 sel=10 prompt=1 req=0011 grant=1000 trans=1 type=1
addr=0 width=100 size=23 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=11 cov=100
945 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=1 width=100 size=23 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
955 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=5 width=100 size=22 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
965 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=9 width=100 size=21 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
975 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=13 width=100 size=20 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
985 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=17 width=100 size=19 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
995 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=21 width=100 size=18 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
1005 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=25 width=100 size=17 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
1015 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=29 width=100 size=16 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
1025 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=33 width=100 size=15 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
1035 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=37 width=100 size=14 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
1045 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=41 width=100 size=13 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
1055 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=45 width=100 size=12 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
1065 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=49 width=100 size=11 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
28

cov=100
1075 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=53 width=100 size=10 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11
cov=100
1085 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=57 width=100 size=9 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
1095 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=61 width=100 size=8 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
1105 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=65 width=100 size=7 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
1115 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=69 width=100 size=6 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
1125 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=73 width=100 size=5 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
1135 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=77 width=100 size=4 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
1145 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=81 width=100 size=3 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
1155 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=85 width=100 size=2 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
1165 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=89 width=100 size=1 rdata=zzzzzzzz wdata=f60438c9 comp=1bm=11 cov=100
1175 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=1
addr=0 width=100 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=11 cov=100
1185 sel=11 prompt=1 req=0111 grant=0001 trans=0 type=1
addr=0 width=100 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=100
1205 sel=11 prompt=1 req=0110 grant=0001 trans=1 type=0
addr=0 width=100 size=4 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=100
1215 sel=zz prompt=0 req=1110 grant=0001 trans=0 type=0
addr=1 width=100 size=4 rdata=04030201 wdata=zzzzzzzz comp=1bm=00 cov=100
1225 sel=zz prompt=0 req=1110 grant=0001 trans=0 type=0
addr=5 width=100 size=3 rdata=08070605 wdata=zzzzzzzz comp=1bm=00 cov=100
1235 sel=zz prompt=0 req=1110 grant=0001 trans=0 type=0
addr=9 width=100 size=2 rdata=12111009 wdata=zzzzzzzz comp=1bm=00 cov=100
1245 sel=zz prompt=0 req=1110 grant=0001 trans=0 type=0
addr=13 width=100 size=1 rdata=16151413 wdata=zzzzzzzz comp=1bm=00 cov=100
1255 sel=zz prompt=0 req=1110 grant=0001 trans=0 type=0
addr=0 width=100 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=100
1265 sel=00 prompt=1 req=1110 grant=0010 trans=0 type=0
addr=0 width=100 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=100
1285 sel=00 prompt=1 req=1100 grant=0010 trans=1 type=1
addr=0 width=010 size=18 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=100
1295 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=1 width=010 size=18 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1305 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=3 width=010 size=17 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1315 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=5 width=010 size=16 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1325 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=7 width=010 size=15 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1335 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=9 width=010 size=14 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1345 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=11 width=010 size=13 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01
29

cov=100
1355 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=13 width=010 size=12 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01
cov=100
1365 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=15 width=010 size=11 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01
cov=100
1375 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=17 width=010 size=10 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01
cov=100
1385 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=19 width=010 size=9 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1395 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=21 width=010 size=8 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1405 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=23 width=010 size=7 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1415 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=25 width=010 size=6 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1425 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=27 width=010 size=5 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1435 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=29 width=010 size=4 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1445 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=31 width=010 size=3 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1455 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=33 width=010 size=2 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1465 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=35 width=010 size=1 rdata=zzzzzzzz wdata=000089f3 comp=1bm=01 cov=100
1475 sel=zz prompt=0 req=1101 grant=0010 trans=0 type=1
addr=0 width=010 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=100
1485 sel=zz prompt=0 req=1101 grant=0100 trans=0 type=1
addr=0 width=010 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=100
1505 sel=zz prompt=0 req=1001 grant=0100 trans=1 type=0
addr=0 width=010 size=29 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=100
1515 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=1 width=010 size=29 rdata=00000201 wdata=zzzzzzzz comp=1bm=10 cov=100
1525 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=3 width=010 size=28 rdata=00000403 wdata=zzzzzzzz comp=1bm=10 cov=100
1535 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=5 width=010 size=27 rdata=00000605 wdata=zzzzzzzz comp=1bm=10 cov=100
1545 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=7 width=010 size=26 rdata=00000807 wdata=zzzzzzzz comp=1bm=10 cov=100
1555 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=9 width=010 size=25 rdata=00001009 wdata=zzzzzzzz comp=1bm=10 cov=100
1565 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=11 width=010 size=24 rdata=00001211 wdata=zzzzzzzz comp=1bm=10
cov=100
1575 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=13 width=010 size=23 rdata=00001413 wdata=zzzzzzzz comp=1bm=10
cov=100
1585 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=15 width=010 size=22 rdata=00001615 wdata=zzzzzzzz comp=1bm=10
cov=100
1595 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
30

addr=17 width=010 size=21 rdata=00001817 wdata=zzzzzzzz comp=1bm=10
cov=100
1605 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=19 width=010 size=20 rdata=00002019 wdata=zzzzzzzz comp=1bm=10
cov=100
1615 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=21 width=010 size=19 rdata=00002221 wdata=zzzzzzzz comp=1bm=10
cov=100
1625 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=23 width=010 size=18 rdata=00002423 wdata=zzzzzzzz comp=1bm=10
cov=100
1635 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=25 width=010 size=17 rdata=00003925 wdata=zzzzzzzz comp=1bm=10
cov=100
1645 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=27 width=010 size=16 rdata=00004140 wdata=zzzzzzzz comp=1bm=10
cov=100
1655 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=29 width=010 size=15 rdata=00004342 wdata=zzzzzzzz comp=1bm=10
cov=100
1665 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=31 width=010 size=14 rdata=00004544 wdata=zzzzzzzz comp=1bm=10
cov=100
1675 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=33 width=010 size=13 rdata=00004746 wdata=zzzzzzzz comp=1bm=10
cov=100
1685 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=35 width=010 size=12 rdata=000089f3 wdata=zzzzzzzz comp=1bm=10
cov=100
1695 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=37 width=010 size=11 rdata=000038c9 wdata=zzzzzzzz comp=1bm=10
cov=100
1705 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=39 width=010 size=10 rdata=0000f604 wdata=zzzzzzzz comp=1bm=10
cov=100
1715 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=41 width=010 size=9 rdata=000038c9 wdata=zzzzzzzz comp=1bm=10 cov=100
1725 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=43 width=010 size=8 rdata=0000f604 wdata=zzzzzzzz comp=1bm=10 cov=100
1735 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=45 width=010 size=7 rdata=000038c9 wdata=zzzzzzzz comp=1bm=10 cov=100
1745 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=47 width=010 size=6 rdata=0000f604 wdata=zzzzzzzz comp=1bm=10 cov=100
1755 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=49 width=010 size=5 rdata=000038c9 wdata=zzzzzzzz comp=1bm=10 cov=100
1765 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=51 width=010 size=4 rdata=0000f604 wdata=zzzzzzzz comp=1bm=10 cov=100
1775 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=53 width=010 size=3 rdata=000038c9 wdata=zzzzzzzz comp=1bm=10 cov=100
1785 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=55 width=010 size=2 rdata=0000f604 wdata=zzzzzzzz comp=1bm=10 cov=100
1795 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
addr=57 width=010 size=1 rdata=000038c9 wdata=zzzzzzzz comp=1bm=10 cov=100
1805 sel=zz prompt=0 req=1001 grant=0100 trans=0 type=0
31

addr=0 width=010 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=100
1815 sel=10 prompt=1 req=1001 grant=1000 trans=0 type=0
addr=0 width=010 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=11 cov=100
1835 sel=10 prompt=1 req=0001 grant=1000 trans=1 type=0
addr=0 width=010 size=19 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=11 cov=100
1845 sel=01 prompt=1 req=0101 grant=1000 trans=0 type=0
addr=1 width=010 size=19 rdata=00000201 wdata=zzzzzzzz comp=1bm=11 cov=100
1855 sel=01 prompt=1 req=0101 grant=1000 trans=0 type=0
addr=3 width=010 size=18 rdata=00000403 wdata=zzzzzzzz comp=1bm=11 cov=100
1865 sel=01 prompt=1 req=0101 grant=1000 trans=0 type=0
addr=5 width=010 size=17 rdata=00000605 wdata=zzzzzzzz comp=1bm=11 cov=100
1875 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=7 width=010 size=16 rdata=00000807 wdata=zzzzzzzz comp=1bm=11 cov=100
1885 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=9 width=010 size=15 rdata=00001009 wdata=zzzzzzzz comp=1bm=11 cov=100
1895 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=11 width=010 size=14 rdata=00001211 wdata=zzzzzzzz comp=1bm=11
cov=100
1905 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=13 width=010 size=13 rdata=00001413 wdata=zzzzzzzz comp=1bm=11
cov=100
1915 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=15 width=010 size=12 rdata=00001615 wdata=zzzzzzzz comp=1bm=11
cov=100
1925 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=17 width=010 size=11 rdata=00001817 wdata=zzzzzzzz comp=1bm=11
cov=100
1935 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=19 width=010 size=10 rdata=00002019 wdata=zzzzzzzz comp=1bm=11
cov=100
1945 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=21 width=010 size=9 rdata=00002221 wdata=zzzzzzzz comp=1bm=11 cov=100
1955 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=23 width=010 size=8 rdata=00002423 wdata=zzzzzzzz comp=1bm=11 cov=100
1965 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=25 width=010 size=7 rdata=00003925 wdata=zzzzzzzz comp=1bm=11 cov=100
1975 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=27 width=010 size=6 rdata=00004140 wdata=zzzzzzzz comp=1bm=11 cov=100
1985 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=29 width=010 size=5 rdata=00004342 wdata=zzzzzzzz comp=1bm=11 cov=100
1995 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=31 width=010 size=4 rdata=00004544 wdata=zzzzzzzz comp=1bm=11 cov=100
2005 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=33 width=010 size=3 rdata=00004746 wdata=zzzzzzzz comp=1bm=11 cov=100
2015 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=35 width=010 size=2 rdata=000089f3 wdata=zzzzzzzz comp=1bm=11 cov=100
2025 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=37 width=010 size=1 rdata=000038c9 wdata=zzzzzzzz comp=1bm=11 cov=100
2035 sel=zz prompt=0 req=0111 grant=1000 trans=0 type=0
addr=0 width=010 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=11 cov=100
2045 sel=zz prompt=0 req=0111 grant=0001 trans=0 type=0
addr=0 width=010 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=100
2065 sel=zz prompt=0 req=0110 grant=0001 trans=1 type=1
addr=0 width=010 size=28 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=100
32

2075 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=1 width=010 size=28 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2085 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=3 width=010 size=27 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2095 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=5 width=010 size=26 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2105 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=7 width=010 size=25 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2115 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=9 width=010 size=24 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2125 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=11 width=010 size=23 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2135 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=13 width=010 size=22 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2145 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=15 width=010 size=21 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2155 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=17 width=010 size=20 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2165 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=19 width=010 size=19 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2175 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=21 width=010 size=18 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2185 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=23 width=010 size=17 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2195 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=25 width=010 size=16 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2205 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=27 width=010 size=15 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2215 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=29 width=010 size=14 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2225 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=31 width=010 size=13 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2235 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=33 width=010 size=12 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2245 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=35 width=010 size=11 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2255 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=37 width=010 size=10 rdata=zzzzzzzz wdata=0000341e comp=1bm=00
cov=100
2265 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=39 width=010 size=9 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
33

2275 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=41 width=010 size=8 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2285 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=43 width=010 size=7 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2295 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=45 width=010 size=6 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2305 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=47 width=010 size=5 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2315 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=49 width=010 size=4 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2325 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=51 width=010 size=3 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2335 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=53 width=010 size=2 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2345 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=55 width=010 size=1 rdata=zzzzzzzz wdata=0000341e comp=1bm=00 cov=100
2355 sel=zz prompt=0 req=0110 grant=0001 trans=0 type=1
addr=0 width=010 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=100
2365 sel=zz prompt=0 req=0110 grant=0010 trans=0 type=1
addr=0 width=010 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=100
2385 sel=zz prompt=0 req=0100 grant=0010 trans=1 type=1
addr=0 width=100 size=4 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=100
2395 sel=zz prompt=0 req=0100 grant=0010 trans=0 type=1
addr=1 width=100 size=4 rdata=zzzzzzzz wdata=5bff78f7 comp=1bm=01 cov=100
2405 sel=zz prompt=0 req=0100 grant=0010 trans=0 type=1
addr=5 width=100 size=3 rdata=zzzzzzzz wdata=5bff78f7 comp=1bm=01 cov=100
2415 sel=zz prompt=0 req=0100 grant=0010 trans=0 type=1
addr=9 width=100 size=2 rdata=zzzzzzzz wdata=5bff78f7 comp=1bm=01 cov=100
2425 sel=zz prompt=0 req=0100 grant=0010 trans=0 type=1
addr=13 width=100 size=1 rdata=zzzzzzzz wdata=5bff78f7 comp=1bm=01 cov=100
2435 sel=zz prompt=0 req=0100 grant=0010 trans=0 type=1
addr=0 width=100 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=01 cov=100
2445 sel=zz prompt=0 req=0100 grant=0100 trans=0 type=1
addr=0 width=100 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=100
2465 sel=zz prompt=0 req=0000 grant=0100 trans=1 type=1
addr=0 width=001 size=25 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=100
2475 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=1 width=001 size=25 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2485 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=2 width=001 size=24 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2495 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=3 width=001 size=23 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2505 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=4 width=001 size=22 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2515 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=5 width=001 size=21 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2525 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=6 width=001 size=20 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2535 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=7 width=001 size=19 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2545 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=8 width=001 size=18 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2555 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=9 width=001 size=17 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
34

2565 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=10 width=001 size=16 rdata=zzzzzzzz wdata=00000012 comp=1bm=10
cov=100
2575 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=11 width=001 size=15 rdata=zzzzzzzz wdata=00000012 comp=1bm=10
cov=100
2585 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=12 width=001 size=14 rdata=zzzzzzzz wdata=00000012 comp=1bm=10
cov=100
2595 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=13 width=001 size=13 rdata=zzzzzzzz wdata=00000012 comp=1bm=10
cov=100
2605 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=14 width=001 size=12 rdata=zzzzzzzz wdata=00000012 comp=1bm=10
cov=100
2615 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=15 width=001 size=11 rdata=zzzzzzzz wdata=00000012 comp=1bm=10
cov=100
2625 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=16 width=001 size=10 rdata=zzzzzzzz wdata=00000012 comp=1bm=10
cov=100
2635 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=17 width=001 size=9 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2645 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=18 width=001 size=8 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2655 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=19 width=001 size=7 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2665 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=20 width=001 size=6 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2675 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=21 width=001 size=5 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2685 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=22 width=001 size=4 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2695 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=23 width=001 size=3 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2705 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=24 width=001 size=2 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2715 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=25 width=001 size=1 rdata=zzzzzzzz wdata=00000012 comp=1bm=10 cov=100
2725 sel=zz prompt=0 req=0000 grant=0100 trans=0 type=1
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=10 cov=100
2735 sel=zz prompt=0 req=0000 grant=0001 trans=0 type=1
addr=0 width=001 size=0 rdata=zzzzzzzz wdata=zzzzzzzz comp=0bm=00 cov=100
$finish at simulation time 3000
V C S S i m u l a t i o n R e p o r t
Time: 3000
CPU Time: 0.020 seconds; Data structure size: 0.0Mb
Mon May 11 13:43:23 2009